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CUPL is a programmable logic device (PLD) compiler design language, which allows one to convert complicated sequential and combinatorial SSI designs to their PLD equivalents. A self documenting syntaxs allows fewer keystrokes. The bit-field capability also saves keystrokes. There is a diagram of the registered output signals, and a figure explaining two possible locations for the memory map. A table covers the logic description file, for RFSHCNT and another for MEMDEC.

Although circuits that incorporate programmable logic devices (PLD) take up less board space than SSI-based systems and require less design time than eigther SSI or custom-IC devices, designers have been hesitant to use PLDs until recently because of their unusual architecture and lack of software support. Compiler based software frees the designer from being concerned with the PLD's internal details when implementing logic functions. PLDs are easier to modify and cost less that SSI based circuits. They bridge the gap between bulky discrete designs and long custom-IC design cycles. Part one of this three-part series discusses basic PLD architecture and shows how to replace two simple logic designs with PLDs using a compiler based PLD design language. Part two will discuss how to replace more complicated combinatorial and registered-TTL designs with PLDs. Part three will show how to implement a logic design directly, without developing a gate level description of the system. Circuit diagrams illustrate the discussion.