79 results on '"Oh, Jae Sub"'
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2. Improved Responsivity of an a-Si-based Micro-bolometer Focal Plane Array with a SiNx Membrane Layer
3. 3D gate-all-around bandgap-engineered SONOS flash memory in vertical silicon pillar with metal gate
4. 300 mm Large Area Wire Grid Polarizers with 50 nm Half-Pitch by ArF Immersion Lithography
5. Characterization of polycrystalline silicon-oxide-nitride-oxide-silicon devices on a SiO2 or Si3N4 buffer layer
6. Electrical Characterization in Pillar Type Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory using Bandgap Engineering Method
7. RTS Noise Analysis in Fin-type Silicon-Oxide-High-k-Oxide-Silicon Flash Memory
8. Downscaling Study of Uncooled a-Si Infrared Microbolometer Cell based on Simulation
9. Mechanical and Electrical Reliability Analysis of Flexible Si Complementary Metal-Oxide-Semiconductor Integrated Circuit
10. A SONOS device with a separated charge trapping layer for improvement of charge injection
11. Low-Frequency Noise Characteristics in SONOS Flash Memory With Vertically Stacked Nanowire FETs
12. Tunneling oxide engineering by ion implantation of nitrogen for 3D vertical silicon pillar SONOS flash memory
13. High-power tunable matching circuit using SOI-CMOS digitally programmable capacitor array for 4G mobile handsets
14. Cofabrication of Vacuum Field Emission Transistor (VFET) and MOSFET
15. Pillar Type Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory Cells with Modulated Tunneling Oxide
16. Body engineering structure for ZnO thin-film transistors: a Schottky-contact-merged ZnO TFT
17. The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation
18. Polycrystalline Silocon-Oxide-Nitride-Oxide-Silicon Flash Memory on SiO2 and Si3N4 Buffer Layer for System on Panels Application
19. The analysis of 3-Level Charge Pumping in SOHOS Flash Memory
20. Highly endurable floating body cell memory: Vertical biristor
21. A sub-1-volt nanoelectromechanical switching device
22. Improvement of Charge Retention in Flash Memory Devices by Very Light Doping of Lanthanum into an Aluminum-Oxide Blocking Layer
23. The 1/f Noise Analysis of 3D SONOS Multi Layer Flash Memory Devices Fabricated on Nitride or Oxide Layer
24. A Study on the Corner Effect of Fin-type SONOS Flash Memory Using TCAD Simulation
25. Comparative Analysis of Bandgap-Engineered Pillar Type Flash Memory with HfO2 and S3N4 as Trapping Layer
26. Vertically Integrated Unidirectional Biristor
27. Lanthanum-Oxide-Doped Nitride Charge-Trap Layer for a TANOS Memory Device
28. Performance Study on a Tri-Gate SONOS Flash Memory with Gate Stack Engineering
29. Crystallized HfLaO embedded tetragonal ZrO2 for dynamic random access memory capacitor dielectrics
30. Silicon Nanowire All-Around Gate MOSFETs Built on a Bulk Substrate by All Plasma-Etching Routes
31. Mechanism of Date Retention Improvement by High Temperature Annealing of Al2O3 Blocking Layer in Flash Memory Device
32. Mechanism of Date Retention Improvement by High Temperature Annealing of Al2O3Blocking Layer in Flash Memory Device
33. Dual-Gate ZnO Thin-Film Transistors with SiNx as Dielectric Layer
34. Improvement of reliability characteristics using the N2 implantation in SOHOS flash memory
35. Characteristics Analysis Related with Structure and Size of SONOS Flash Memory Device
36. Cubic-Structured HfLaO for the Blocking Layer of a Charge-Trap Type Flash Memory Device
37. Analysis of Fin-Type SOHOS Flash Memory using Hafnium Oxide as Trapping Layer
38. Improvement of memory performance by high temperature annealing of the Al2O3 blocking layer in a charge-trap type flash memory device
39. Structural and compositional dependence of gadolinium-aluminum oxide for the application of charge-trap-type nonvolatile memory devices
40. SONOS-Type Flash Memory with HfO2 Thinner than 4 nm as Trapping Layer Using Atomic Layer Deposition
41. Refinement of Unified Random Access Memory
42. Energy-Band-Engineered Unified-RAM (URAM) Cell on Buried $\hbox{Si}_{1 - y}\hbox{C}_{y}$ Substrate for Multifunctioning Flash Memory and 1T-DRAM
43. Partially Depleted SONOS FinFET for Unified RAM (URAM)—Unified Function for High-Speed 1T DRAM and Nonvolatile Memory
44. A Bulk FinFET Unified-RAM (URAM) Cell for Multifunctioning NVM and Capacitorless 1T-DRAM
45. Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire
46. A Unified-RAM (URAM) Cell for Multi-Functioning Capacitorless DRAM and NVM
47. A Nanowire Transistor for High Performance Logic and Terabit Non-Volatile Memory Devices
48. A sub-1-volt nanoelectromechanical switching device.
49. High Injection Efficiency and Low-Voltage Programming in a Dopant-Segregated Schottky Barrier (DSSB) FinFET SONOS for NOR-type Flash Memory.
50. A Novel FinFET With High-Speed and Prolonged Retention for Dynamic Memory.
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