Search

The impact of back-gate bias on the total ionizing dose (TID) response of silicon-on-insulator (SOI) nanowire field-effect transistors (NWFETs) is investigated. The voltage shift induced by TID is studied using different NWFET geometries and as function of the bias applied to the back-gate made of the silicon substrate. Modifications induced on static electrical characteristics, that is, drain current versus gate-to-source voltage $I_{\mathrm {D}}(V_{\mathrm {GS}})$ characteristics, are investigated. Experimental results highlight that the bias applied to the back-gate during $I{-}V$ measurements strongly impacts the NWFET TID response. At 0 V applied to the back-gate, a usual TID behavior is observed. $I{-}V$ curves are shifted to negative $V_{\mathrm {GS}}$ values, which is consistent with the literature. In contrast, two competing mechanisms are shown when negative biases are applied to the back-gate. $I_{\mathrm {D}}(V_{\mathrm {GS}})$ curves are first shifted to positive $V_{\mathrm {GS}}$ values for low TID before showing a more usual negative TID-induced voltage shifts. This two-step behavior may be attributed to several phenomena. They include either a modification of the net trapped charge sign for several back-gate biases and/or a motion of carriers trapped into the Buried OXide (BOX). The major goal of this article is to identify the mechanism at stake which drives this combined TID/electrostatic behavior.

This paper aims at analyzing the analog characteristics of n-type vertically stacked nanowires with 2 channels, varying the fin width and channel length. The basic electrical parameters such as threshold voltage and subthreshold slope are extracted in the linear region, whereas the transconductance, output conductance, and intrinsic voltage gain are extracted in saturation.

We combine advanced transmission electron microscopy (TEM) and numerical models to draw the evolution of strains over the integration of horizontally stacked Gate-All-Around Nanosheet transistors (GAANS). In particular, we measured compressive strains of -0.5% to -1% after channel release in transistors at 10 nm design rule. With support on model calculations, we speculate that the effect is related to a compressive inter-layer dielectric (ILD). As another method to manipulate channel stresses, in a specifically designed GAANS we demonstrate a transition from compressive to tensile strain introduced by a gate stack/contact test modules. Finally, a demonstration of GAANS Si-channel cladded with SiGe opens a way for the co-integration of compressive SiGe channels with limited modification of the integration flow. The findings provide insights and guidelines for strain engineering in GAANS.

The total ionizing dose (TID) response of pMOS nanowire field-effect transistors (NWFETs) is investigated using X-ray irradiations. The TID-induced voltage shift is studied using two NWFET widths and four bias configurations. Both the impact of the geometry and the influence of the bias configuration during irradiation on the radiation-induced trapped charges into the buried oxide are thus addressed. The impact of gate length downsizing on the NWFET’s electrical characteristics in several bias configurations is studied and compared to one of the nMOS NWFETs to state on the mechanisms which leads to their TID response.

This paper investigates the total ionizing dose (TID) sensitivity of nanowire (NW) field-effect transistors (NWFETs). Both X-ray irradiations and self-consistent calculations of charge trapping in dielectrics are performed to study their TID response. First of all, the impact of the NW geometry is investigated. The NWFET TID behavior exhibits a strong dependence as a function of the NWs width while shortening the gate length does not significantly change the TID characteristics of optimized narrow NWFETs. Furthermore, the effect of the bias configuration used during irradiation is discussed to state if nMOS NWFETs could withstand significant amount of TID in several operation conditions.

This paper presents the fundamental analog figures of merit, such as the transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and harmonic distortion (or non-linearity), of n-type vertically stacked nanowires with variable fin width and channel length. To have a physical insight on the results, the basic electrical parameters such as threshold voltage, subthreshold slope and low field electron mobility of the analyzed transistors were also studied. The studied analog parameters are presented in function of the transconductance over drain current, to allow for the comparison at the same inversion level.

In this work, an experimental analysis on the carrier mobility of p- and n-type Ω-gate SOI nanowire MOS transistors with different fin widths is done by varying substrate bias. Y-function method was used to extract mobility and its degradation coefficients. Differently from previously reported data from pMOS transistors, in which carrier mobility degrades with substrate bias increase, an improvement in carrier mobility is verified for n-type devices when back bias is increased from negative voltages up to 10V. However, by raising back bias up to 100V, causes carrier mobility degradation. Three-dimensional simulations confirmed this effect and showed that strong back bias attract the channel to the bottom interface, causing carrier confinement and, thus, increasing scattering mechanisms.

Made available in DSpace on 2019-10-06T15:39:25Z (GMT). No. of bitstreams: 0 Previous issue date: 2019-01-30 This paper presents a comparison between nMOS and pMOS Ω-Gate Nanowire for different channel width (W NW ) down to 10 nm as a function of the large back gate bias variation (from +20 to -20 V) experimentally and by simulation. The main digital and analog parameters are analyzed in these devices as threshold voltage, subthreshold swing (SS), transconductance, transistor efficiency, Early Voltage and intrinsic voltage gain for transistor channel width from 220 nm down to 10 nm. It is shown that narrow channel devices (W NW = 10 nm) present a small variation on the analyzed parameters as a function of back gate voltage due to stronger electrostatic control between gate and channel considering that they are effectively working like a gate-all-around devices. In general, all the nMOS parameters presents better results compared to pMOS due to the mobility enhancements. For wider devices (W NW = 220 nm), it depends on the back interface condition. For a large enough back gate bias that tends to create a back interface conduction (+20 V for nMOS and -20 V for pMOS), the SS degrades from 61 mV dec -1 (W NW = 10 nm) to 68 mV dec -1 (W NW = 220 nm). However for a large enough back gate bias that induces a non-conduction region (tends to accumulation) at back interface (-20 V for nMOS and +20 V for pMOS) the SS changes from 60 to 62 mV dec -1 at the same W NW range, which is a very acceptable results. Additionally, the drain current (I ON ) and transconductance (linear and saturation regions) increase for this back gate bias condition (tends to accumulation), working almost like a pseudo nanosheet device for these parameters, avoiding also the parasitic conduction at the back interface. However, in spite of the intrinsic voltage gain is almost independent of the back gate bias, it improves of at least 10 dB for narrow devices due to the higher Early voltage and almost similar transistor efficiency than the wider ones. LSI/PSI/USP University of Sao Paulo Faculdade de Tecnologia de Sao Paulo e Faculdade de Tecnologia de Osasco CEETEPS Sao Paulo State University (UNESP) Sao Joao da Boa Vista CEA LETI, Minatec Campus and University Grenoble Alpes Sao Paulo State University (UNESP) Sao Joao da Boa Vista

In this work we investigated the impact of back bias on the effective mobility of p-type Ω-gate nanowire SOI MOSFETs. Evaluation is performed through both measurements and 3D numerical simulations. Electrostatic potential, electric field and holes density are studied through simulations to explain transconductance degradation with back bias increase. Holes mobility linear dependence on back bias is found to be related to the inversion channel density and its position along the silicon thickness. Besides, this work also sheds light on the dependence of the drain current in vertically stacked NW with back bias, as its behavior is determined by the bottom Ω-gate level.

In this work, we experimentally investigate the impact of measurement speed (μs-800 ps) on the characterization of reliability behaviors, hot carrier injection (HCI) and positive bias temerature instability (PBTI), for FDSOI nMOSFETs. The results show that, due to the severe self-heating effect (SHE) in the FDSOI nMOSFETs, the I-V measurement speed could significantly affects the characterization of threshold voltage V th shift and saturation drive current I dsat degradation after HCI and PBTI stress. Due to the inevitable SHE in the transistor channel caused by the long measurement time, the V th shift and I dsat degradation would be underestimated, leading to an overestimation of the HCI and PBTI lifetime. To precisely characterize the SHE-free reliability behaviors in FDSOI or FinFETs, a nanosecond-level measurement speed would be necessary to eliminate the SHE.

Pre-strained fin-patterned Si/SiGe multilayer structures for sub-7 nm stacked gate-all-around Si-technology transistors that have been grown onto bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator, and compressive SiGe-On-Insulator were investigated. From strain maps with a nanometer spatial resolution obtained by transmission electron microscopy, we developed 3D quantitative numerical models describing the mechanics of the structures. While elastic interactions describe every other system reported here, the patterning on the compressive SiGe-On-Insulator substrate that is fabricated by Ge-condensation results in relaxation along the semiconductor/insulator interface, revealing a latent plasticity mechanism. As a consequence, Si layers with a uniaxial stress of 1.4 GPa are obtained, bringing fresh perspectives for strain engineering in advanced devices. These findings could be extended to other semiconductor technologies.

We propose a TID effect hardening strategy for nanoscaled ultra-thin BOX and body SOI technologies. Experiments performed on NMOS and PMOS transistors demonstrate that TID effects can be mitigated by applying a dynamic back-bias technique. These data are used to calibrate the back-bias that has to be applied on UTSOI transistors to efficiently mitigate TID-induced effects. Elementary circuit cells made of inverters are then modeled using dedicated mixed TCAD calculations in order to validate the proof of concept of this hardening strategy at circuit level. Finally, results obtained on Ultra-Thin BOX devices typical of future FDSOI technologies show that the proposed hardening strategy efficiency increases with BOX thinning and then with technology downscaling.

This paper aims at presenting, for the first time, an experimental comparative analysis between the main electrical parameters of Junctionless (JNT) and inversion mode nanowire (IM) transistors fabricated in SOI technology down to channel length of 10 nm. The analysis has shown that JNTs present larger immunity to SCEs with respect to IM nanowires of similar dimensions. However, JNTs have shown poorer Ion than IM devices, which could be compensated through the application of multifin JNTs, at cost of increasing area consumption.

This paper experimentally explores the analog performance of Self-Cascode structures composed by SOI Nanowire nMOSFETs operating near the subthreshold regime. The composite structure uses transistors with distinct channel widths, biased in several back-gate voltages, to promote different threshold voltages.

session: Monolithic 3D 3; International audience; In this study we investigate the effect of some of the steps during a low temperature gate stack process flow, necessary for 3D sequential integration. These are: the nitridation of the high-k layer, the post nitridation annealing temperature and finally, the back end forming gas. Using Time Dependent Defect Spectroscopy, we could evaluate the impact of pre-existing traps on the quality of the gate stack (t 0 reliability) which shows no major differences between the splits, since they all have a low temperature dopant activation process. However, by applying Negative Bias Temperature Instability measurements, we observe that with the split of N 2 /H 2 nitridation, we have the best compromise of a small Equivalent Oxide Thickness and a low degradation. At the same time we see no difference at the stress impact between the two Post Nitridation Anneal temperatures. In that way we are able to move to lower temperatures. Finally, using the Deuterium as a back end forming gas we can have a set of guidelines, for some of the major process steps, to achieve high performance and low degradation, necessary for future scaling.

The goal of this work is analyze for the first time the low-energy proton irradiation elfects on p and n-channel SOI Ω — Gate Nanowire transistors for total ionization dose of 500 krad. After radiation, it is noticed a slight variation on a drain current and in a transconductance, for large devices, due to the back leakage current.

This paper shows the influence of back gate bias on transistor efficiency of nMOS SOI Ω-gate nanowire, for different width and channel length. Threshold voltage and subthreshold swing present a higher variation with the back gate bias variation in wider devices. Long channel devices present better efficiency due to the better subthreshold swing, the same reason for the narrow devices have a better efficiency. Wider devices have a higher variation in efficiency when the back gate is biased. The transistor efficiency increases when the back gate is negative biased due to the better electrostatic coupling between gate and channel.

Self-heating effect (SHE) has become a significant concern for device performance, variability and reliability co-optimization due to more confined layout geometry and lower-thermal-conductivity materials adopted in advanced transistor technology, which substantially impacts the integrated circuit (IC)'s design schemes. In this work, a new methodology for evaluation of SHE in both digital and analog circuits is demonstrated by using pulse-aware and existing sine-aware analytical models respectively. Correlating SHE to physics-based thermal-aware reliability models provides insights for design and sign-offs of advanced digital and analog ICs.

session 3E: Reliability Testing; International audience; In this paper we present a direct comparison of the two basic techniques for trap extraction, the Random Telegraph Noise (RTN) and the Time Dependent Defect Spectroscopy (TDDS). By using the method of histograms, extracted from the measured drain current transients, we divided the recorded defects in three different categories. Results show that we night be able to detect traps deeper in the oxide and, also, near the dielectric/channel interface. As we scale down, we found a better correlation between the two methods, while the after stress results show a merging of the slopes compared to the bimodal distribution that appeared at the beginning.

In this paper the analog performance of the Self-Cascode structure composed by SOI Nanowire nMOSFETs has been evaluated through experimental results. The influence of the channel width of the transistors near the source and the drain, and the back gate voltage variation have been evaluated.

This paper shows for the first time, the influence of back gate bias (V B ) in some analog parameters on pMOS Silicon-On-Insulator (SOI) omega-gate nanowire (ΩG-NW) devices down to 10 nm width (W). An excellent electrostatic control is observed in devices down to 40 nm of channel length. The saturated transconductance slightly increase while the output conductance slightly decrease with V B increment, resulting in an increase of intrinsic voltage gain (AV) up to 30% for wider devices.

We investigate the impact of performance boosters using mechanical stress on the Single-Event Transient (SET) response of nanometer scaled Fully-Depleted Silicon-On-Insulator (SOI) devices. Laser SET measurements show that the active silicon layer thickness is the most important contributor to the SET response of highly scaled Ultra-Thin SOI (UTSOI) devices compared to the impact of strain. This is then demonstrated by dedicated TCAD calculations performed without taking into account any strain engineering technique. Finally, heavy ion-induced charge collection mechanisms are analyzed through the measurement of fast transients to get additional insights into the impact of short channel effects on the SET response of nanometer scaled SOI devices.

International audience; We report on vertically stacked horizontal Si NanoWires (NW) p-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si p-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs p-FETs.

We demonstrate that FDSOI transistors co-integrated with a diode implemented below the buried oxide (BOX) become strongly sensitive to visible light. The carriers photogenerated in the diode create a Light-Induced Vt Shift (LIVS) in both NFET & PFET transistors by means of capacitive coupling, without direct electrical connection between the photodiode and the sensing transistor. This optical back biasing effect is carefully examined as a function of both transistor and diode technological parameters. The experimental results are supported by TCAD simulations, suggesting that the proposed FDSOI/photodiode co-integration scheme can be used for efficient photodetectors. We also study the transient effects, and propose an efficient reset mechanism. Finally, we demonstrate for the first time that SRAM cells can be made controllable by light illumination.

For the first time we performed the CMOS integration on hybrid SOI/Bulk wafers obtained by the local internal dissolution technique of the buried oxide (BOX). We compared the electrical performance of transistors fabricated on hybrid wafers and co-processed Ultra-Thin Body and Buried oxide (UTBB) and bulk silicon wafers. Devices on the FDSOI and bulk parts of hybrid substrates present similar carrier mobility than the references. Moreover, diodes with high forward current are achieved on the bulk part of the hybrid wafers.

International audience; In this paper we investigate the Total Ionizing Dose (TID) response of an UltraThin Buried-OXide (UTBOX) on a Fully Depleted Silicon-On-Insulator (FDSOI) high-k/metal gate technology. The impact of thinning the BOX and of the use of a Ground Plane (GP) at the back side of the BOX on the TID behavior are discussed by comparing their results to ionizing radiation experiments performed on reference FDSOI devices.

We investigate for the first time the influence of the back gate bias (V B ) in the main digital and analog parameters on Silicon-On-Insulator (SOI) omega-gate nanowire devices down to 10 nm width (W). For wider channel, it was observed that for high negative V B the subthreshold swing (SS) and DIBL are decreased due to the better channel confinement while the intrinsic voltage gain is almost insensitive in all studied devices. For omega-gate nanowire of 10 nm width, no relevant influence was observed in both digital and analog parameters, once that for 11 nm height and rounded structure it is working effectively like a gate all around structure.

3D VLSI with a CoolCube™ monolithic integration flow allows vertically stacking several layers of devices with a unique connecting via density above tens of million/mm2. This results in increased devices density and gains in power and performance thanks to wire-length reduction without the extra cost associated to transistor scaling. In addition to power saving, this true 3D integration opens perspectives in terms of heterogeneous integration. We will review the opportunities brought by CoolCube™ and will present the most advanced technological demonstration of 3D CMOS over CMOS CoolCube™ integration.

For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

International audience; In this work, a predictive and physical compact model for NanoWire/NanoSheet (NW/NS) Gate-All-Around (GAA) MOSFET is presented. Based on a novel methodology for the calculation of the surface potential including quantum confinement, this model is able to handle arbitrary NW/NS cross-section shape of stacked-planar and vertical GAA MOSFETs (circular, square, rectangular). This Nanowire Surface Potential (NSP) based model, validated both by numerical simulations and experimental data, is demonstrated to be very accurate in all operation regimes of GAA MOSFETs.

International audience; The effect of strain on carrier mobility in triple gate Fully Depleted Silicon On Insulator (FDSOI) nanowires (NWs) is experimentally investigated through piezoresistance measurements. The piezoresitive coefficients have been extracted and analyzed for rectangular cross-section with varying aspect ratio (width vs. height). We propose an empirical model based on mobility separation between top and sidewall conduction surfaces of the NWs, and on the carrier density calculation in the cross-section of the NWs. The model allows fitting the piezoresistive coefficients and the carrier mobility for the different device geometries. We highlight an enhanced strain effect for Trigate nanowires with channel thickness below 11 nm. (C) 2016 Elsevier Ltd. All rights reserved.

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

This paper analyzes and models the drain-induced barrier lowering (DIBL) for ultrathin silicon body and ultrathin silicon body and thin buried oxide (UTBB) SOI MOSFETs. The channel depth appears as the primary factor in controlling DIBL when the substrate is in accumulation or inversion, whereas space-charge thickness in the substrate is the dominant parameter when the substrate is depleted. Under substrate depletion condition, UTBB devices lose their low DIBL features due to the increased coupling through the effective insulating layer underneath the transistor channel. The proposed model extending MASTAR equations is in agreement with experimental DIBL.

International audience; We investigate Single-Event Transients (SET) in different designs of multiple-gate devices made of FinFETs with various geometries. Heavy ion experimental results are explained by using a thorough charge collection analysis of fast transients measured on dedicated test structures. Multi-level simulations are performed to get new insights into the charge collection mechanisms in multiple-gate devices. Implications for multiple-gate device design hardening are finally discussed.

This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.

In this paper, an in-depth variability analysis, i.e., from the threshold voltage VT of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local VT variability σ(V)T lower than A(V)T = 1.4 mV · μm is demonstrated. We investigated how this good VT variability is reported on the SNM fluctuations σSNM at the SRAM circuit level. It is found experimentally that σSNM is correlated directly to the σ(V)T of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The VT variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V)T in drive nMOSFETs is the key parameter to control for minimizing σSNM.

The impact of local deep-amorphization (DA) and subsequent solid-phase epitaxial regrowth (SPER) are studied for the co-integration of devices with hybrid surface orientation. Thin-body p-channel transistors with 20nm thick film and HfO"2 gate insulator/metal gate along several directions on a (110) substrate were fabricated and characterized. No deterioration of transconductance or threshold voltage was induced by DA/SPER process. Device co-integration using DA/SPER process is therefore a realistic option. channel on (110) SOI film yields a 200% gain on the current for the (100) surface orientation. However, the benefit of it decreases with the channel length.

In this paper, we present a new numerical model of the inversion charge power spectral density in FDSOI MOSFET devices with ultra thin body. Numerical simulation results are compared to those of the classical formulation and to experimental data. A good agreement of measurements is obtained with the proposed model. The results show that the noise behavior in FDSOI MOSFETs is strongly related to the front and buried oxides defects, even if the channel is located at the front interface. In other words, the classical formulation of the flat-band voltage power spectral density (PSD) overestimate the front oxide trap density and no more holds true in SOI MOSFETs LFN characterization.

An alternative technology is studied here to elaborate hybrid orientation silicon on insulator (SOI) films above a continuous buried oxide (BOX). To this purpose, a “deep-amorphization” followed by solid phase epitaxial regrowth (SPER) of SOI films is investigated. The effect of the deep-amorphization and SPER on p-type fully-depleted metal oxide semiconductor field effect transistors (FD-MOSFETs) electrical characteristics is presented and discussed for both (1 0 0) and (1 1 0) oriented SOI films. High performance pMOS were realized on (1 1 0) substrates. Our results show a +30% gain on the drive current for the (1 1 0) surface orientation, and we further demonstrate that no degradation of the performance is introduced by the amorphization and SPER processes.

Ultra-thin (UT) SOI MOSFETs provide better control of short-channel effects. The introduction of high-k dielectric and metal gate enables to use undoped channels in UT SOI-MOSFETs. A single mid-gap metal gate in undoped channels provides suitable threshold voltage (VTH) for low supply voltage and low-power applications. For the further generations, the use of thin buried oxide (BOX) is needed to achieve better control of short channel effects and prevent variability in the device performance[1]. A thin BOX is also attractive for dynamic threshold voltage operation using low supply voltage to the back gate (Vg2). Dynamic threshold voltage operation can suppress leakage when the device is in the off state and can enhance the channel current when it is in the on state. This paper presents a study on the impact of Vg2 on the channel current in UT SOI MOSFETs with 8 nm film and 10 nm BOX. The test devices were fabricated at STMicroelectronics (Crolles) using (100) UNIBOND SOI wafers. The SOI films were thinned down using thermal oxidation and wet etching to a final thickness of around 8 nm. The transistor bodies were kept undoped during the entire process with an initial doping of around 10/cm. A 2.5 nm high-k dielectric (HfO2), a metal gate (ALD TiN 10 nm) and a poly-Si (80 nm) were deposited. Selective epitaxy in the extension regions was performed to reduce the external resistance.

After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650^oC). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.

SOI technology offers ample room for scaling, performance improvement, and innovations. The current status is reviewed by focusing on several technological options for boosting the transport properties in SOI MOSFETs. The impact of series resistance, high-K dielectrics, and metal gate in advanced transistors is discussed. Carrier mobility measurements as a function of channel length and temperature reveal the beneficial effect of strain, mitigated however by various types of defects. The experimental data is exclusively collected from state-of-the-art, ultrathin body, fully depleted MOSFETs. Simple models are presented to clarify the mobility behavior.

The microelectronics industry is facing historical challenges to down scale CMOS devices through the demand for low voltage, low power, high performance and increased functionalities. The implementation of new materials and devices architectures will be necessary. HiK gate dielectric and metal gate are among the most strategic options to reduce power consumption and manage low supply voltage. Multigate architectures increase MOSFETs drivability, reduce power, and allow new memory devices opportunities for future applications. By introducing new materials(HiK, Ge, III-V, Carbon based materials like diamond, graphene and CNTs, molecules,…), and new functions such as sensing and actuation allowing to interface the outside world (M/NEMS, filters, Imagers,…), Si based CMOS will be scaled beyond the ITRS as the System-on- Chip/Wafer Platform. The Heterogeneous integration of these devices with CMOS will require new 3D and Packaging schemes leading to the increase of effective packing density, improving systems figures of merit. Index Terms- CMOSFETs, Diamond, Germanium, Nanocrystals, Flash Memories, Silicon on insulator technology, Strain, Wafer bonding, Heterogeneous, MEMS, NEMS, BAW, RF, Switch, Optical interconnect, Imagers, 3D-TSV, 3D SOW. The International Technology Roadmap of Semiconduct three types of products: High Performance (HP), Low Operating Power (LOP) and Low Standby Power (LSTP) devices. In the HP case, an historical fact happens by the 32nm node: the contribution of static power dissipation become close to the dynamic power somewhat this evolution by improving the saturation current to leakage current ratio. In this review, we will first analyze the main limitations and showstoppers affecting CMOS scaling. Issues on gate stack, channel and source and drain engineering as well as new devices architectures(FDSOI or multigate devices) are discussed. Low power consumption and Heterogeneous functions integration will be leveraged by future nomadic systems. The increased number of devices and different types of signals will, in turn, leverage 3D IN Package or ON chip co-integration.

In this paper we explore for the first time the impact of an ultra-thin BOX (UTBOX) with and without ground plane (GP) on a 32 nm fully-depleted SOI (FDSOI) high-k/metal gate technology. The performance comparison versus thick BOX architecture exhibits a 50 mV DIBL reduction by using 10 nm BOX thickness for NMOS and PMOS devices at 33 nm gate length. Moreover, the combination of DIBL reduction and threshold voltage modulation by adding GP enables to reduce the Isb current by a factor 2.8 on a 0.299μm2 SRAM cell while maintaining an SNM of 296 mV@Vdd 1.1 V.

In this study, Silicon-On-Diamond (SOD) micro-structures have been fabricated using either Smart Cut™ or bonded and Etched-Back Silicon On Insulator (BESOI) technology. Thanks to the development of an innovative smoothening process, polycrystalline diamond layers (C*) can be integrated as a buried oxide layer offering new opportunities in terms of thermal management. We describe different technological process flow investigations leading to SOD by bonding C* layer in the stack. As starting material we used poly-crystalline thin diamond films in the 200 nm to 7000 nm range of thickness. The C* is deposited by Chemical Vapour Deposition assisted by Microwave Plasma (MPCVD) onto various 50 mm wafers such as Si, SOI and polycrystalline silicon carbide (pSiC). As the roughness of the diamond layer is not directly compatible with a wafer bonding integration, an innovative smoothening process in 3 steps has been developed and named “DPE” for Deposition, Planarization and Etching. Using the DPE process, the roughness of 5 µm thick diamond layer could be reduced from 50 to 3 nm RMS and down to 1.5 nm RMS for a thin 200 nm layer. In order to demonstrate the feasibility of a GaN on SOD micro-structure design for HEMT applications, layer transfers have been carried out by a bonding and thinning process from C*/Si bulk using oxide bonding layers. From thermal spreading efficiency consideration, new processes of fabrication of SOD/poly-SiC substrate are in progress involving BESOI or Si Smart Cut™ technologies and poly-Si bonding layer starting from C*/poly-SiC. Pure SOD substrate were also fabricated by using C*/SOI and poly-Si bonding layer in a BESOI technology. A thin active silicon layer (70 nm) of 50 mm diameter onto a 140 nm thick diamond BOX layer has been transferred on 200 mm diameter Si substrate for future MOSFET's devices demonstrations. Significant progress has been done in diamond layer integration by wafer bonding.

International audience; The synthesis of diamond films with extreme insulating properties is of great interest for most diamond film applications in nanoelectronics. SOD (Silicon-On-Diamond) is a promising alternative to standard SOI (Silicon-On-Insulator) because of the high heat-spreading capability of diamond material. Current Fully Depleted MOS processing technologies require a thickness of the dielectric buried layer of 150 nm. Synthesis of polycrystalline diamond films is already well documented. Nonetheless, the difficulties here are to keep their high thermal conductivity and their high electrical resistivity in spite of the reduction of the diamond layer thickness. This study aims at the fine control of both the nucleation density and the growth process to enable the fabrication of optimized fully covered diamond films as thin as possible.A mathematical model describing the coalescence was used to determine the surface coverage of the diamond film according to the linear growth of the diamond nanocrystals for different nucleation densities. The model gives information on the nucleation density needed to obtain a covering diamond film within ultrathin diamond layer thickness. To corroborate the coalescence model, diamond layers with different surface coverages were characterized. Our work led to ultrathin diamond layers (thickness below 140 nm) exhibiting electrical resistivities above 2 × 10^13 Ω cm.

In this paper, Silicon on Diamond (SOD) substrates were fabricated using the direct bonding process in two different technologies: the BESOI (Bonded and Etched-back SOI) and the Smart-Cut™ process. The polycrystalline diamond (C∗) film deposited by Chemical Vapor Deposition assisted by Microwave Plasma (MPCVD) was planarized by an innovative process which induces a significant decrease of the diamond surface roughness (1.2 nm for the 200 nm diamond layer). The planarization method as well as the entire SOD substrate process by the BESOI or the Smart-Cut™ technology are described in the paper. Cross sectional high-resolution transmission microscopy reveals the good quality of the future silicon channel on top of the thin diamond layer.

Power consumption and matching are the principal issues at the 32 nm node and below. In this context, Ultra-Thin Body devices are extensively studied for the end-of-roadmap CMOS. In this paper we present thin-film technologies (FDSOI, LSOI and bulk+) leading to the integration of single gated thin films devices for 22 nm nodes and below.