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To improve the threshold voltage and gate reliability of conventional enhancement-mode p-GaN-gated AlGaN/GaN high electron mobility transistors while maintaining a low on-resistance, an improved design solution for p-GaN HEMTs with P-I-N junction gate (PIN-HEMTs) has been proposed. Simulation results show that energy band modulation is achieved by adjusting the doping concentration and thickness of each layer of the PIN junction, and high-performance p-GaN gate HEMTs with adjustable threshold voltages ranging from 0.56 V to 4.75 V and gate breakdown voltages ranging from 19.8 V to 30.3 V would be prepared. The PIN-HEMT has a quasi-self-alignment property, which means that good gate control is independent of gate metal alignment. This not only improves the production efficiency but also solves the problems of weak gate control and electric field aggregation at the gate edge caused by the gate misalignment in conventional p-GaN gate HEMTs, thus realizing lower on-resistance and higher gate breakdown voltage, which demonstrates this proposed structure has excellent potentials for realizing effective and reliable high-power transistors. [ABSTRACT FROM AUTHOR]

GaN-based enhancement-mode high-electron-mobility transistors (HEMTs) with a 25-nm-thick undoped GaN (u-GaN) cap underneath the gate metallization on ultrathin-barrier (UTB) AlGaN (<6 nm)/GaN heterostructures have been demonstrated. The presence of a thick u-GaN cap contributes to the increased depletion of the two-dimensional electron gas (2DEG) beneath the gate by polarization effects, resulting in an improvement of the threshold voltage (Vth) and a suppression of the off-state gate leakage (Ioff). The UTB HEMTs with a thick u-GaN cap exhibit normally-off operation with a Vth of 0.5 V, a maximum on-current of 232.1 mA/mm, an Ioff of 10−6 mA/mm, and a gate voltage swing of 7 V at a drain bias of 10 V. Thanks to the p-doping-free GaN cap, the device demonstrates excellent Vth stability under positive gate bias, which positions it as a promising candidate for future low-voltage GaN power applications. [ABSTRACT FROM AUTHOR]

AlGaN/GaN devices for both power and RF applications have been investigated in this work. In particular, regarding power applications, 100 V p-GaN gate transistors have been analysed both in DC and in dynamic conditions with specific attention to the high temperature behaviour.As a first step, the high temperature behaviour of the on-resistance (RON) of a reference process (STD process) has been investigated. The role of the different resistive components of the transistor has been analysed by evaluating how their relative weight changes with the temperature increase. Then, two different p-GaN process variations (process A and process B) have been proposed and compared to the STD process to show their improvement in terms of a limited RON increase at 150 °C, highlighting the relevance of an improved p-GaN gate processing.Secondly, the temperature effect on the RON-degradation induced by off-state drain voltage stress has been investigated in process B-like devices. The impact of temperature on the time required to reach a steady state degradation has been addressed, enabling the comparison of the RON degradation (RON/ RON0) at equilibrium. Tests performed on several samples have demonstrated the invariance of the RON/ RON0 ratio in the 25 °C to 150 °C range, suggesting the possibility to reduce the measurements required for dynamic-RON evaluation at different T.Finally, RF devices (featuring Schottky metal gate) have been characterized in terms of DC/RF performances and long-term reliability (through HTRB tests). Different trials with increasing aluminium content of the AlGaN barrier have been compared, showing the correlation with the maximum saturation current and the output power. Moreover, the trade-off with reliability specifications has been put in evidence.

The role of the magnesium (Mg) doping and its electrical activation on the off-state of p-GaN/AlGaN/GaN HEMTs has been investigated in this work. Firstly, the effect of different Mg doping profiles has been studied via the help of Technology Computer-Aided Design (TCAD) simulations, with the objective of analyzing the band diagrams of the structure. Then, it has been shown how experimental Capacitance–Voltage measurements can be useful to obtain information on the net acceptor concentration in the p-GaN. As a result, devices with an undoped (magnesium-free) GaN gate have been experimentally compared to devices whose p-GaN gate has been activated via a reference annealing process. Finally, results on a device characterized by an improved p-GaN activation have been presented and compared, showing improvements on several parameters of both off- and on-state, thus underlining the key role of the Mg activation process in the overall performances of normally-off GaN HEMTs. [ABSTRACT FROM AUTHOR]

A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up approach on a highly n-doped silicon substrate. The electrical performance is studied as a function of various epi-structure parameters, including region lengths and doping levels, nanowire diameter, and the impact of the surface states. The results reveal that the optimized structure has a Normally-OFF mode with a threshold voltage higher than 0.8 V and exhibits minimized leakage current, low on-state resistance, and maximized breakdown voltage. To the best of our knowledge, this is the first exhaustive study of GaN-based nanowire transistors, providing valuable insights for the scientific community and contributing to a deeper understanding of the impact of GaN nanowire parameters on device performance.

High temperature operation of enhancement-mode (E-mode) and depletion-mode (D-mode) AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) was demonstrated. By using the circular device structure, off-state current was effectively suppressed, and record high Ion/Ioff ratio around 108 was obtained at 400 °C. Atomic layer etching was used for formation of the gate recess structure in the E-mode device, and good interface was made which enabled stable normally-off operation up to 400 °C. D-mode device experienced positive threshold voltage shift during the high temperature operation and after cooling down to room temperature, due to strain relaxation. On the other hand, due to the very thin AlGaN layer retained under the gate of the E-mode device, the threshold voltage of the E-mode device is nearly unchanged when the sample is heated up and cooled down. A direct coupled field-effect transistor logic (DCFL) inverter was fabricated based on the E-mode and D-mode devices and showed stable operation up to 400 °C.

An experimentally calibrated technology computer-aided design (TCAD) simulation was conducted to study P-GaN gate AlGaN/GaN heterostructure field-effect transistors with gate-connected P-AlGaN field plates (PAFP-HFETs). The P-AlGaN field plates modulated the distribution of an electric field along the GaN channel, suppressed electric field crowding at the edge of the gate, and remarkably improved the breakdown voltage (BV). The PAFP-HFET with a gate-to-drain distance of Lgd = 6 μm, showed a BV of 1560 V with an average breakdown electric field of 2.6 MV/cm. The PAFP with structural parameters of length Lp, thickness Tp, doping density NP, and gate connected metal length Lm were optimized by the charge balance principle of the RESURF concept. The highest Baliga figure-of-merit (BFOM) of 2.4 GW/cm2 was obtained under the conditions of Tp = 500 nm, Np = 1 × 1017 cm−3, Lp = 5.8 μm and Lm = 0.8 μm. The capacitance–voltage (C–V) characteristics indicated that the PAFP-HFET had a lower Coss, Ciss and Crss than the HFET with metal field plates. Above all, the PAFP-HFET shows promise for achieving a high BFOM with conventional III-N fabrication processes. [ABSTRACT FROM AUTHOR]

This paper reviews the prospects of normally-off (N-off) JFET switch in SiC. The potential of selected vertical JFET concepts and all-JFET cascode solutions for N-off operation is analyzed using simulations. The performance of analyzed concepts is compared in terms of blocking voltage, specific on-state resistance, maximum output current density and switching performance in the temperature range from 25°C to 250°C. The main objective of the analysis is to ascertain consequences of different design and technology options for the total losses and high temperature performance of the devices.

A new design for an enhancement mode Gallium Nitride (GaN)-based High Electron Mobility Transistor (HEMT) is proposed along with a novel fabrication technique. Normally-off operation is achieved through the introduction of a localized P-region below the AlGaN/GaN interface underneath the gate electrode. Since achieving high hole concentration through ion implantation is experimentally challenging, the effect of a localized buried P-region was replicated through the growth of an epitaxial P-layer in which N-wells will be later introduced. Simulation results conducted under ATLAS, a TCAD simulation tool from Silvaco, demonstrated a successful shift in the threshold voltage to positive values. The physics behind this shift is explained through the band diagram. A sensitivity analysis is conducted showing the effect of device parameters on the threshold voltage and the current density. [ABSTRACT FROM AUTHOR]

Fabrication of hydrogen-terminated (H-terminated) diamond field effect transistor (FET) with low work function cerium hexaboride (CeB 6) gate material has been successfully performed. For the 8 μm gate length device, the threshold voltage (V TH) is extracted to be −0.46 V, demonstrating a normally-off characteristics. The maximum drain source current density (I Dmax) is −83.8 mA/mm, and the competitive I Dmax may be ascribed to the undamaged two-dimensional hole gas channel. The interface state density (D it) is evaluated to be 1.93 × 1012 cm−2·eV−1, and the relatively low value may be attributed to the uncontaminated interface in gate material. This work provides a promising strategy to realize normally-off H-terminated diamond FET for fail-safety and energy-efficient power electronic devices. [Display omitted] [ABSTRACT FROM AUTHOR]

• Normally-off GaN MOSFET is successfully demonstrated by using the selective regrowth of AlGaN layer on source/drain (S/D) regions. • Wide regrown AlGaN layer is applied to GaN MOSFET to accommodate the poor structural quality of narrow regrown AlGaN on the S/D regions. • The proposed device with wide regrown AlGaN S/D has the potential to serve as a robust and uniform normally-off GaN MOSFET. A normally-off GaN MOSFET is successfully fabricated by using the selective regrowth technique (SRT) with regrown AlGaN layer on source/drain (S/D) region. The GaN MOSFET with regrown AlGaN layer and L g of 10 μm shows enhanced electrical performance such as maximum drain current (I D,max) of 57 mA/mm, maximum transconductance (g m,max) of 11 mS/mm, and field-effect mobility (μ FE) of 59 cm2/V·s, respectively, compared to the GaN MOSFET with n+-GaN selective regrowth in S/D region. This is because of the high 2DEG density formed by AlGaN/GaN heterojunction in S/D region. Moreover, to accommodate the poor structural quality of the narrow region regrowth of AlGaN layer on the S/D region, wide regrown AlGaN layer is applied to the GaN MOSFET. Especially, the off-state breakdown voltage improves from 25 V to 192 V with the improved structural quality of wide regrown AlGaN layer and optimized structure and the application of the 70-nm thick SiO 2 passivation. These result shows that GaN MOSFET with wide regrown AlGaN layer on S/D region is beneficial to achieving high-quality and uniform normally-off GaN MOSFETs with excellent electrical performance. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

The role of the magnesium (Mg) doping and its electrical activation on the off-state of p-GaN/AlGaN/GaN HEMTs has been investigated in this work. Firstly, the effect of different Mg doping profiles has been studied via the help of Technology Computer-Aided Design (TCAD) simulations, with the objective of analyzing the band diagrams of the structure. Then, it has been shown how experimental Capacitance–Voltage measurements can be useful to obtain information on the net acceptor concentration in the p-GaN. As a result, devices with an undoped (magnesium-free) GaN gate have been experimentally compared to devices whose p-GaN gate has been activated via a reference annealing process. Finally, results on a device characterized by an improved p-GaN activation have been presented and compared, showing improvements on several parameters of both off- and on-state, thus underlining the key role of the Mg activation process in the overall performances of normally-off GaN HEMTs.

In this work, the current transient method was conducted for trap analysis in the p-GaN gate high-electron-mobility transistors (HEMTs) in the OFF-state. Based on the traditional detrapping transient measurements, the pure recovery transients can be isolated by subtracting the undetected part caused by the measurement conditions. A comparison of the measured and actual recovery transients under different drain filling voltages was presented. It suggested that this method can be effective to analyze the unregular transient curves and distinguish the charge trapping type preliminarily. In addition, three traps were identified based on the time constant spectra and the hidden absolute amplitudes of traps can be corrected using the differential amplitude spectra. The information of trap levels in the buffer layer and AlGaN barrier layer was revealed, consisting of three electron traps with energy levels of 0.313, 0.265, and 0.467 eV. The identification of the traps may provide a physical foundation for better understanding of the drain-induced trapping effect during the OFF-state in p-GaN HEMTs. [ABSTRACT FROM AUTHOR]

Based on the self-terminating thermal oxidation-assisted wet etching technique, two kinds of enhancement mode Al2O3/GaN MOSFETs (metalâ€"oxideâ€"semiconductor field-effect transistors) separately with sapphire substrate and Si substrate are prepared. It is found that the performance of sapphire substrate device is better than that of silicon substrate. Comparing these two devices, the maximum drain current of sapphire substrate device (401 mA/mm) is 1.76 times that of silicon substrate device (228 mA/mm), and the field-effect mobility (ÎĽ FEmax) of sapphire substrate device (176 cm2/Vâ‹...s) is 1.83 times that of silicon substrate device (96 cm2/Vâ‹...s). The conductive resistance of silicon substrate device is 21.2Ω â‹...mm, while that of sapphire substrate device is only 15.2Ω â‹...mm, which is 61% that of silicon substrate device. The significant difference in performance between sapphire substrate and Si substrate is related to the differences in interface and border trap near Al2O3/GaN interface. Experimental studies show that (i) interface/border trap density in the sapphire substrate device is one order of magnitude lower than in the Si substrate device, (ii) Both the border traps in Al2O3 dielectric near Al2O3/GaN and the interface traps in Al2O3/GaN interface have a significantly effect on device channel mobility, and (iii) the properties of gallium nitride materials on different substrates are different due to wet etching. The research results in this work provide a reference for further optimizing the performances of silicon substrate devices. [ABSTRACT FROM AUTHOR]

A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

A novel method to fabricate the oxidized silicon-terminated (C–Si–O) diamond metal-oxide-semi- conductor field-effect transistors (MOSFETs) by replacing the retained SiO2 masks with an atomic layer deposition (ALD)-Al2O3 film as the main gate insulator was proposed for the first time. Compositional analysis across the SiO2 masks and on the air-exposed C–Si–O (111) diamond surface has been carried out by utilizing secondary ion mass spectroscopy (SIMS) and Auger electron spectroscopy (AES) techniques, respectively. Furthermore, we revealed that, under selectively epitaxial growth of diamond through a SiO2 mask, a carbon-rich film was formed on SiO2 and C–Si bonding was realized at the SiO2/(111) diamond interface. The fabricated device with a source and drain distance (${L}_{SD}$) of $3 \,\mu \text{m}$ exhibits a distinct threshold voltage (${V}_{TH}$) of −5.6 V and a maximum drain current density (${I}_{D\_{}{MAX}}$) up to −311 mA/mm, which is a record value among normally-off single-crystalline diamond MOSFETs to date. In the case of having ALD-Al2O3 as the main gate insulator, normally-off operation of the C–Si–O diamond MOSFETs has a stark contrast with the typically normally-on performance of the hydrogen-terminated (C–H) diamond MOSFETs, which is mainly due to the smaller negative electron affinity of C–Si–O diamond compared with that of C–H diamond. These results indicate that the proposed C–Si–O (111) diamond MOSFETs with excellent normally-off operation and large drain current density are promising to fulfill the requirements of fail-safe and current drive capabilities in power device applications. [ABSTRACT FROM AUTHOR]

A small subthreshold swing (SS) hydrogen-terminated diamond field-effect transistor is realized by using a wide bandgap material (SnO2). Results showed an SS of 106.4 mV/dec, which should be ascribed to the low interface state density (1.05 $\times10$ 12 cm $^{-2}\cdot $ eV−1) between SnO2 and diamond. The fixed charge density and trapped charge density are $1.1\times10$ 12 cm−2 and $8.6\times10$ 11 cm−2, respectively. Leakage current between source and gate is less than $2.1\times10$ −8 A at gate voltages from −5.0 to 1.0 V and the breakdown voltage is measured to be −180 V. In addition, the devices exhibit normally- OFF characteristics, whose threshold voltage and maximum drain current density are −0.12 V and −21.6 mA/mm with 4- $\mu \text{m}$ gate at ${V}_{GS} = -3$ V. The ON/OFF ratio is around 107 and the maximum effective mobility is extracted to be 165 cm2/(Vs). This work indicates that SnO2 dielectric could form low interface state density with hydrogen-terminated diamond surface and it also provides a simple method to realize normally- OFF devices. [ABSTRACT FROM AUTHOR]

A normally-off β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed using a technology computer-aided design (TCAD) device simulation, which employs an epitaxial drift layer grown on an n-type low-doped body layer. The low-doped body layer under the MOS gate enabled normally-off operation, whereas the epitaxial drift layer determined the on-resistance and breakdown characteristics. The effects of the doping concentration of each layer and thickness of the drift channel layer on the device characteristics were investigated to design a device with a breakdown voltage of 1 kV. A threshold voltage of 1.5 V and a breakdown voltage of 1 kV were achieved by an n-type body layer with a doping concentration of 1 × 1015 cm−3 and an n-type drift layer with a doping concentration of 3 × 1017 cm−3, a thickness of 150 nm, and a gate-to-drain distance of 9.5 μm; resulting in an on-resistance of 25 mΩ·cm2. [ABSTRACT FROM AUTHOR]

SnOx films were deposited on a hydrogen-terminated diamond by thermal oxidation of Sn. The X-ray photoelectron spectroscopy result implies partial oxidation of Sn film on the diamond surface. The leakage current and capacitance–voltage properties of Al/SnOx/H-diamond metal-oxide-semiconductor diodes were investigated. The maximum leakage current density value at −8.0 V is 1.6 × 10−4 A/cm2, and the maximum capacitance value is measured to be 0.207 μF/cm2. According to the C–V results, trapped charge density and fixed charge density are determined to be 2.39 × 1012 and 4.5 × 1011 cm−2, respectively. Finally, an enhancement-mode H-diamond field effect transistor was obtained with a VTH of −0.5 V. Its IDMAX is −21.9 mA/mm when VGS is −5, VDS is −10 V. The effective mobility and transconductance are 92.5 cm2V−1 s−1 and 5.6 mS/mm, respectively. We suspect that the normally-off characteristic is caused by unoxidized Sn, whose outermost electron could deplete the hole in the channel. [ABSTRACT FROM AUTHOR]

[Display omitted] • The preparation of AlN films by magnetron sputtering at low temperature of 400 °C is proposed and the effect of 11-nm AlN cap layer on the performance of the p-GaN HEMT is investigated. • Low-temperature preparation of AlN enhances the threshold voltage and drain breakdown characteristics of p-GaN HEMTs and has good potential for preparing p-GaN HEMT power devices. • The conduction band offset of p-GaN and AlN was analyzed by XPS test, and the gate leakage current suppression mechanism was clarified. • The improved gate reliability of the AlN/p-GaN HEMT due to the preparation of AlN is analyzed and the gate leakage current mechanism is clarified. In this paper, a low temperature sputtered AlN cap-layer p-GaN HEMT with high gate breakdown and improved reliability is realized. XPS test shows that the valence band offset of p-GaN and low-temperature magnetron sputtered AlN is 1.2 eV, which successfully suppresses the gate leakage current and greatly improves the gate reliability. Low capacitance–voltage hysteresis and small pulsed threshold voltage shift predict good AlN/p-GaN interface quality. The threshold voltage of the AlN/p-GaN HEMT is improved from 0.61 V to 0.82 V compared to the conventional p-GaN HEMT with tungsten Schottky gate (W/p-GaN HEMT), the DIBL decrease from 34.4 mV/V in W/p-GaN HEMT to 1.1 mV/V in AlN/p-GaN HEMT. The gate forward and reverse leakage is significantly suppressed, and the gate forward breakdown voltage is improved to 17 V. The gate operating range is improved from 7 V to 12 V, and the I D / I G under saturation state is improved from 104 to 107. In addition, a smaller on-resistance of 67.5 Ω·mm was obtained, which is 15.3 % lower than that of the W/p-GaN HEMT, minimizing on-state loss. The gate leakage mechanism of the AlN/p-GaN HEMT is mainly dominated by the PF emission in the medium gate voltage range. Based on this leakage mechanism, the maximum forward V G for a ten-year lifetime was extracted as 6.8 V at room temperature at a failure level of 63.2 % for the AlN/p-GaN HEMT, while this value for W/p-GaN HEMT is 5.4 V. In addition, the AlN cap layer attenuates the depletion region of metal/p-GaN by the gate Schottky metal, which keeps the GaN channel better depleted, thus keeping a higher off-state breakdown voltage. These results demonstrate the good potential of magnetron sputtering AlN as a low-cost, methodologically simple growth method for the commercial use of p-GaN HEMTs. [ABSTRACT FROM AUTHOR]

Apart from providing high-quality ohmic contacts to III-N devices, n++ GaN cap layers can eliminate surface-related current collapse effects in high-electron-mobility transistors (HEMTs). Various metal-organic chemical vapor deposition conditions and n-type doping are tested in GaN growth on sapphire by using triethylgallium as a Ga precursor, replacing more conventional trimethylgallium. Consequently, despite relatively low temperature of the growth at 800 °C to facilitate InAlN barrier capping, optimized growth conditions and SiH 4 flow provided free electron concentration of 7.2 × 1019 cm−3 and mobility of 103 cm2/Vs. Moreover, electron concentration in the range of 1020 cm−3 is demonstrated by using flow modulation epitaxy. On the other hand, as calibration growths indicated, excessive SiH 4 flow alone can lead to high density of edge dislocations and surface undulations without enhancing free electron concentration. 6 nm (Si: 4.2 × 1019 cm−3) and 8 nm thick (Si: 7.2 × 1019 cm−3) n++ GaN cap is implemented in normally-off n++ GaN/InAlN/AlN/GaN HEMTs grown on Si, with a collapse-free performance for the latter case. By calculating energy band and free carrier concentration profiles of the heterostructures it is shown, that free electrons of a sufficiently thick and doped n++ GaN cap can shield the channel from the unstable surface potential. [ABSTRACT FROM AUTHOR]

In this article, the normally- OFF oxidized Si-terminated (C–Si) diamond metal–oxide–semiconductor field-effect transistors (MOSFETs) with as-deposited 0.5-nm silicon on diamond annealed at high temperature as the subsurface p-channel were presented for the first time. A novel method utilizing both a metal mask to realize the regrown heavily boron-doped (001) diamond layer first (p+-diamond-first) and a molecular beam deposition (MBD) method to procure atomic-scale silicon deposition was achieved. Scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy (EDS) element mapping results suggest that the C–Si diamond/Al2O3 interface is quite continuous and atomically flat. A remarkably high threshold voltage (${V}_{\text{TH}}$) of −10 V and a maximum drain current density (${I}_{D\_{}{\text{MAX}}}$) of −156 mA/mm are simultaneously achieved in the fabricated devices. The devices with different source and drain (S/D) distances ($L_{\text{SD}}$) deliver robust ${V}_{\text{TH}}$ results and feature low OFF-state S/D leakage current $\vert {I}_{\text{leakage}}\vert $ of ~ $6\times10$ −6 mA/mm at ${V}_{\text{GS}}$ = 0 V. The extracted field-effect mobility is as high as 127 cm2 $\cdot \text{V}$ −1 $\cdot \text{s}$ −1 and the interface state density is as low as $4.35\times10$ 12 eV−1 $\cdot $ cm−2. These competitive results reveal that this first attempt of employing the combination of p+-diamond-first and MBD approaches promotes the integration of the advanced silicon manufacturing process with wide bandgap diamond material for power applications. [ABSTRACT FROM AUTHOR]

This letter reports a high drain current density and normally-off operation metal-oxide-semiconductor field-effect transistors (MOSFETs) with a gate insulator of 100 nm-Al2O3. A heavily boron-doped layer as the source/drain region was deposited on a (110) polycrystalline diamond substrate to achieve a low ohmic contact resistance. The MOSFETs demonstrate a maximum current density of −400 mA mm $^{-{1}}$ normalized by gate width and a maximum current density of $- 2000\,\,\mu \text{m}$ mA mm−1 normalized by gate length and gate width, which are the highest values for normally-off diamond FETs. The Grain boundaries (GBs) and the nitrogen impurities ($\sim {3}\,\,\times \,\,{10}^{{17}}$ cm $^{-{3}}$) as ionized donors in the channel region caused the threshold voltage (${V}_{\text {th}}$) to shift in the negative direction, exhibiting normally-off characteristics. This technique provides a promising method to achieve high-performance diamond devices, and help improve safety and save energy in switching systems. [ABSTRACT FROM AUTHOR]

A p-GaN HEMT with an AlGaN cap layer was grown on a low resistance SiC substrate. The AlGaN cap layer had a wide band gap which can effectively suppress hole injection and improve gate reliability. In addition, we selected a 0° angle and low resistance SiC substrate which not only substantially reduced the number of lattice dislocation defects caused by the heterogeneous junction but also greatly reduced the overall cost. The device exhibited a favorable gate voltage swing of 18.5 V (@IGS = 1 mA/mm) and an off-state breakdown voltage of 763 V. The device dynamic characteristics and hole injection behavior were analyzed using a pulse measurement system, and Ron was found to increase and VTH to shift under the gate lag effect. [ABSTRACT FROM AUTHOR]

High performance normally-OFF hydrogenated diamond (C-H diamond) metal–insulator–semiconductor (MIS) field-effect transistors (FETs) have been achieved with Al/BaF2 gate materials. The 15-nm BaF2 film was formed by electron beam evaporation at room temperature. The flat-band voltage and hysteresis voltage extracted from the capacitance–voltage characteristics of the Al/BaF2/ C-H diamond MIS diode indicate low positive fixed charges and trapped charges in the BaF2 film. The 4- $\mu \text{m}$ FET device with a threshold voltage (${V}_{\text {TH}}$) of −0.90 V exhibits distinct pinch-off characteristics. The enhancement mode could be due to primarily the Schottky barrier depletion effect of the gate metal on the channel, and secondarily the positive fixed charges present in the BaF2 layer. The maximum transconductance and maximum saturated drain current are 30 mS/mm and −96.5 mA/mm, respectively. The device performance benefits from the decent conductivity at the BaF2/C-H diamond interface with an almost constant effective hole mobility of about 225.0 cm2/ $\text{V}\cdot \text{s}$ for −2.1 V $\le {V}_{\text {GS}}$ – ${V}_{\text {TH}} \le -4.1$ V. [ABSTRACT FROM AUTHOR]

Hole concentration of 2-D hole gas (2DHG) on (110) diamond is higher than that on other faces, making it the best choice for power device application. Detailed analysis of atomic layer deposition (ALD) Al2O3/(110) C–H diamond interface structure is of vital importance. MOSFETs with thin (10 nm) and thick (100 nm) ALD Al2O3 layer were made in this study. The microstructure of Al2O3 on (110) C–H diamond was analyzed. Abrupt interface of ALD Al2O3/C–H diamond was observed through high resolution transmission electron microscope (HRTEM). Cascode structure using diamond MOSFETs and enhancement mode silicon MOSFET is fabricated and its high performance is confirmed. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrated a normally-off AlGaN/GaN HEMT using p-NiO as a gate stack combined with a recess structure. The fabricated HEMT exhibits a positive threshold voltage of 1.73 V, a saturation output current of 524 mA/mm, a small subthreshold swing of 79.7 mV/dec and a maximum transconductance as high as 143 mS/mm. This is the first time to demonstrate the breakdown characteristics of a p-NiO gate HEMT with a high breakdown voltage of 1205 V and a low specific ON-resistance of 2.22 $\text{m}\Omega \cdot $ cm2, yielding a competitive Baliga’s figure-of-merit of 0.65 GW/cm2. The instability evaluation of ${V}_{\text {TH}}$ by step stress and pulse transfer curves shows that the p-NiO gate HEMT has a negligible ${V}_{\text {TH}}$ shift in the entire measured gate bias range, which can be attributed to the counteraction between the electron trapping-induced positive $\text{V}_{\text {TH}}$ shift and hole accumulation induced-negative ${V}_{\text {TH}}$ shift. It is well understood in terms of the carrier transport model based on the large band discontinuity at the interface of the p-NiO/AlGaN type-II heterojunction, which is further verified by transient gate current spectra. [ABSTRACT FROM AUTHOR]

In this study, a normally-off AlGaN/GaN metalâ€"insulatorâ€"semiconductor field-effect transistor (MIS-FET) based on the combination of tri-gate and recessed MIS gate is fabricated and characterized. The recessed tri-gate MIS-FET is manufactured by micro-level trenches, defining the fin-shaped channel and improving the gate control capability. The recessed surface is cleaned by a diluted buffered oxide etch, HCl solution, and tetramethylammonium hydroxide treatment before a 20 nm Al2O3 deposition by atomic layer deposition. After deposition, post-deposition annealing was carried out. Recessed tri-gate MIS-FET demonstrates a high threshold voltage of 3.1 V, a high drain current of 1121 mA mmâˆ'1, and an on/off current ratio of 2 Ă— 108. A smaller on-resistance of 5.4 Ω mm compared with recessed planar MIS-FET of 12.7 Ω mm is achieved. Besides, the devices show a low I â€" V hysteresis. All experimental results confirm micro-level trenches realize the advantages of the recessed tri-gate structures, which supports a promising technique to pursue the normally-off operation of GaN high electron mobility transistors. [ABSTRACT FROM AUTHOR]

Normally-off p-GaN gated AlGaN/GaN high electron mobility transistors (HEMTs) were developed. Oxygen plasma treatment converted a low-resistive p-GaN layer in the access region to a high-resistive GaN (HR-GaN); that oxygen plasma treatment used an AlN layer as an oxygen diffusion barrier layer to prevent further oxidizing of the underlying AlGaN barrier layer, and to ensure that the low-resistive p-GaN layer in the access region was fully oxidized. Relative to conventional p-GaN gated AlGaN/GaN HEMTs, these AlGaN/GaN HEMTs with HR-GaN layers achieved a lower drain leakage current of 4.4 $\times 10^{-7}$ mA/mm, a higher drain current on/off ratio of 3.9 $\times 10^{9}$ , a lower on-state resistance of 17.1 ${\Omega }\cdot $ mm, and less current collapse.

In this article, the normally- OFF etching-free p-GaN stripe array gate AlGaN/GaN high-electron-mobility-transistors (PSAG-HEMTs) are designed and experimentally demonstrated through hydrogen plasma treatment. The unique threshold voltage (${V}_{TH}$) modulation technique based on the PSAG structure is proposed and simulated. Using this method, the ${V}_{TH}$ can be continuously shifted from −0.14 to +1.03 V by just tuning the widths of p-GaN (${W}_{p}$) and hydrogenated p-GaN (HR-GaN) stripes. To improve breakdown voltage (BV), the PSAG is extended to the drain side based on the 3-D simulation results so that a new electric-field peak is introduced at the edge of the PSAG in the drain side and then the surface electric field is optimized. Besides this, an enhanced conductivity effect is observed and results in a low ON-resistance. The fabricated PSAG-HEMT with $0.75~\mu \text{m}~{W}_{p}$ and 4- $\mu \text{m}$ extension length (${L}_{E}$) exhibits a positive ${V}_{TH}$ of +0.8 V, a low specific ON-resistance (${R}_{\text {ON,sp}}$) of 2.73 $\text{m}\Omega \cdot cm^{2}$ , a high BV of 852 V (1449 V) at ${I}_{D} = 1 ~\mu \text{A}$ /mm, and BFOM of 266 MW/cm2 (769 MW/cm2) with substrate grounded (floating), which demonstrate significant improvements over Reference single-gate E-mode and D-mode devices. This work provides a promising architecture for future high voltage normally- OFF p-GaN HEMT devices. [ABSTRACT FROM AUTHOR]

In this work, the dual junction-high-electron-mobility-transistor (DJ-HEMT) was investigated. The thin AlGaN was grown between the p-GaN gate and gate metal. In the TCAD simulations, the band gap and electric field were shown in this letter, proving the dual junction forming. Moreover, DJ-HEMT shows the high gate voltage swing due to the dual junction at the gate region of device, which enhance gate performance. By contrast with standard p-GaN HEMT (ST-HEMT), DJ-HEMT shows higher $\text{V}_{\text {TH}}$ of 2V, saturation current of 187mA/mm, $\text{I}_{\text {ON}}/\text{I}_{\text {OFF}}$ ratio of $5.1\times 10^{{8}}$ and gate swing voltage which is higher than 20V. In addition, DJ-HEMT also shows the lower device leakage current and superior life time measurement due to the thicker and higher barrier of AlGaN cap layer. [ABSTRACT FROM AUTHOR]

Novel normally-OFF AlGaN/GaN MIS-high electron mobility transistors (HEMTs) with a ZrOx charge trapping layer are proposed. The deposition of the ZrOx charge trapping layer on the partially recessed AlGaN in conjunction with the Al2O3 gate dielectric has been accomplished. The developed MIS-HEMTs exhibit a threshold voltage of 1.55 ± 0.4 V and a maximum drain current of 730 ± 6 mA/mm, while associated low ON-resistance of $7.1~\pm ~0.2~\Omega \cdot $ mm, for a gate to drain separation of 3 $\mu \text{m}$. The TCAD simulation results are presented to explore the charge trapping and de-trapping behaviors. Moreover, the devices exhibit a high breakdown voltage. The results indicate the merits of employing ZrOx charge trapping layer to realize the normally-OFF GaN devices with low ON-state resistance. [ABSTRACT FROM AUTHOR]

High performance normally-off hydrogen-terminated diamond (H-diamond) MOSFETs were fabricated on single crystalline diamond grown in our lab. The device with 2-μm gate length shows threshold voltage of -1.0 V, and a drain current of 51.6 mA/mm at VGS = VDS = -4.5 V and an on-resistance of 65.39 Ω·mm. The transconductance keeps increasing when VGS shifts from VTH toward more negative direction, and reaches the record high value of 20 mS/mm at VGS of -4.5 V, which benefitted from the almost constant mobility of the holes in the gate voltage range of -4 V GS

A normally-off β-Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) is proposed using a technology computer-aided design (TCAD) device simulation, which employs an epitaxial drift layer grown on an n-type low-doped body layer. The low-doped body layer under the MOS gate enabled normally-off operation, whereas the epitaxial drift layer determined the on-resistance and breakdown characteristics. The effects of the doping concentration of each layer and thickness of the drift channel layer on the device characteristics were investigated to design a device with a breakdown voltage of 1 kV. A threshold voltage of 1.5 V and a breakdown voltage of 1 kV were achieved by an n-type body layer with a doping concentration of 1 × 1015 cm−3 and an n-type drift layer with a doping concentration of 3 × 1017 cm−3, a thickness of 150 nm, and a gate-to-drain distance of 9.5 μm; resulting in an on-resistance of 25 mΩ·cm2.

In this work, normally-off p-channel and n-channel heterojunction field-effect transistors (HFETs) were fabricated based on a p-GaN gate Al0.2Ga0.8N/Al0.05Ga0.95N HFET platform. For p-channel HFETs, normally-off operation and low gate leakage were obtained by using a recessed-gate structure and a 20 nm Al2O3 thin film grown by thermal atomic layer deposition as the gate insulator. The normally-off p-channel HFETs exhibited a threshold voltage of 105. By introducing an Al0.05Ga0.95N channel instead of a conventional GaN channel layer, the threshold voltage increased from 1.1 V to 1.5 V and the breakdown voltage almost doubled from 270 to 580 V for n-channel HFETs. These results indicate that n-channel and p-channel HFETs based on p-GaN/Al0.2Ga0.8N/Al0.05Ga0.95N heterostructures have a great potential for monolithic integration.

The normally-off Yttrium (Y) gate hydrogen-terminated (H-terminated) diamond field effect transistor (FET) with 5 nm Al 2 O 3 dielectric layer has been successfully fabricated and evaluated in this work. The threshold voltage is extracted to be - 0.21 V at drain source voltage of −10 V, and the normally-off mode should be caused by the low work function of Y. The saturated drain current (I DSsat) is - 16.14 mA/mm obtained at gate voltage (V GS) of - 2.5 V with 4 μm gate length and 100 μm gate width. The value of I DSsat I DSmax is relatively high compared with other normally-off H-terminated diamond FETs at the same gate voltage, and this is ascribed to the well-preserved two-dimensional hole gas channel. The maximum transconductance of the fabricated device is 7.97 mS/mm. The current on/off ratio is about 7 orders of magnitude with a subthreshold swing of 150 mV/dec. The maximum effective mobility is 233.08 cm2/V. The results contribute to the development of normally-off H-terminated diamond FETs significantly. [ABSTRACT FROM AUTHOR]

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The normally-off hydrogen-terminated diamond metal–semiconductor field effect transistors (MESFETs) with a MoO3 passivation layer were fabricated on the CVD grown polycrystalline diamond substrate. The characteristics of the device at room temperature and 100 °C, 150 °C and 200 °C were investigated. The device with a 2-μm gate shows a threshold voltage of −0.38 V, the maximum output current of 35 mA/mm and the transconductance of 17.4 mS/mm. The device can still work normally until 150 °C, which shows great potential to be used in high temperature in the future.

A p-GaN HEMT with an AlGaN cap layer was grown on a low resistance SiC substrate. The AlGaN cap layer had a wide band gap which can effectively suppress hole injection and improve gate reliability. In addition, we selected a 0° angle and low resistance SiC substrate which not only substantially reduced the number of lattice dislocation defects caused by the heterogeneous junction but also greatly reduced the overall cost. The device exhibited a favorable gate voltage swing of 18.5 V (@IGS = 1 mA/mm) and an off-state breakdown voltage of 763 V. The device dynamic characteristics and hole injection behavior were analyzed using a pulse measurement system, and Ron was found to increase and VTH to shift under the gate lag effect.

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (i.e., 1200 V) SiC junction field effect transistor (JFET) and a low-voltage GaN high electron mobility transistor (HEMT). This cascode device exhibits superior thermal stability and switching performance compared to the SiC MOSFETs, but also inevitably presents challenge in dv/dt-control as the input gate does not directly control the high-voltage JFET. Since dv/dt-control is of great importance to the management and suppression of electromagnetic interference in power electronics systems, methods of controlling the dv/dt rates of SiC/GaN cascode devices need to be developed. In this article, we conduct systematic investigation on different dv/dt control schemes with theoretical analysis and experimental evaluation. A dv/dt-control method based on diode-clamped external JFET gate resistor is proposed and evaluated by comparing it with other more conventional methods. The proposed dv/dt-control method is verified to provide a balanced dv/dt-control on the device turn-on and turn-off. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate normally-OFF p-GaN gate high electron mobility transistors (HEMTs) on Si with an ultrahigh breakdown voltage (VBR) and excellent saturation drain current. Benefiting from the optimized material growth of high-resistivity buffer, effective Al2O3 surface passivation with suppressed OFF-state leakage current, and proper management of the electric field on the p-GaN gate edge, the device with a gate–drain distance of 18.5 μm exhibits a VBR of 1344 V at ID of 1 μA/mm with grounded substrates, the highest among all the reported normally-OFF GaN-on-Si transistors. Well-restored high-density 2-D electron gas and efficient gate modulation enable the device with a high IDS,max of 450 mA/mm and a low specific ON-resistance of 3.92 mΩ·cm2. Moreover, a large threshold voltage of 1.6 V (at ID of 10 μA/mm) and a steep subthreshold slope of 66 mV/dec have been achieved, with negligible threshold voltage shift upon long-term forward gate stress at 150 °C. These results illustrate the great potential of p-GaN gate HEMTs on Si for beyond 600-V applications. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) performances are investigated in a normally-off GaN metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated by utilizing the tetramethylammonium hydroxide (TMAH) wet etching. The normalized power spectral densities ($\text{S}_{Id}/\text{I}_{d}^{2})$ are measured and perfectly matched with both the correlated mobility fluctuations (CMF) and Hooge mobility fluctuations (HMF) noise models. From the curves of ($\text{S}_{Id}/\text{I}_{d}^{2})$ dependent on the gate overdrive voltage (Vg – $\text{V}_{th})^{-1}$ , it is also confirmed that the mobility fluctuations prevail in the fabricated GaN device. The calculated Hooge constants ($\alpha _{H}$) according to the (Vg – $\text{V}_{th}$) are obtained to be 10−2 ~ 10−3. The reason for the dominance of the mobility fluctuations and the relatively low $\alpha _{H}$ is attributed that the TMAH wet etching effectively removes the plasma etching damage and fully recovers the crystal quality of GaN channel. [ABSTRACT FROM AUTHOR]

In this paper, a novel normally off p-gallium nitride (GaN) gate high electron-mobility transistor (HEMT) with composite AlN/Al0.17Ga0.83N/Al0.3Ga0.7N barrier layers is proposed. Compared to the standard (STD) p-GaN/AlGaN/GaN HEMT structure, the composite barriers (CB) with AlN etchstop layer can effectively improve the uniformity of the device threshold voltage (VTH) and reduce the leakage current. The CB p-GaN gate HEMT achieved a VTH of 1.7 ± 0.06 V; this value was 2.1 ± 0.2 V for STD HEMT. In addition, the off-state drain leakage current was suppressed one order of magnitude by adopting a composite barrier design.

In order to realize ultralow power Internet-of-Things (IoT) edge devices, standby leakage current must be suppressed because activity of IoT device is very small in an intermittent mode. One of the approaches for ultralow power consumption is normally off computing by utilizing nonvolatile memory. After the discovery of ferroelectricity in HfO2 which is compatible to CMOS integration, ferroelectric nonvolatile memory has been revisited. In this paper, toward normally off computing, we have proposed, designed, and fabricated nonvolatile SRAM integrated with ferroelectric HfO2 capacitor in a simple architecture with two capacitors. Fundamental store and recall operation have been demonstrated. This device technology will open a new path for ultralow power IoT application.

A normally-OFF GaN metal-insulator-gate high electron mobility transistors with fluorine doped gate insulator has been fabricated using standard ion implantation technique. Fluorine ions with negative charges were doped lightly into both the gate insulator and the partially recessed barrier layer, resulting in high positive threshold voltage ( ${V} _{\mathrm{ th}}$ ) for the device, meanwhile preserving low ON-resistance. Compared to the fluorine-free and recess-free device, only about 16% increase of ON-resistance was observed for the F− doped devices. The fabricated F− doped device exhibits a threshold voltage of +0.68 V at ${I} _{\mathrm{ DS}}= 5~\mu \text{A}$ /mm, a current density of 620 mA/mm, an OFF-state breakdown voltage of 800 V, and high ON/OFF current ratio of 1010. For thermal stability consideration of fluorine dopant, the ${V} _{\mathrm{ th}}$ -thermal stability test and positive bias temperature instability test were also discussed.

We demonstrate a high-performance normally-OFF AlGaN/GaN fin metal–insulator–semiconductor high electron mobility transistor (fin-MISHEMT) on silicon with a low work function metal-source contact ledge (LWFM-SCL). In order to realize the normally-OFF operation, an optimized gate-recessed fin structure is used. The fin structure inherently containing a gate-connected field plate (FP) design improves the breakdown voltage (VBD). Moreover, the LWFM-SCL can improve the device overall ON-resistance (RON) by lowering the gate–source access resistance (Ra). The proposed device with a gate–drain length (LGD) of 7 μm exhibits superior characteristics such as a threshold voltage (VTH) of +1.2 V, maximum drain current (ID, max) of 825 mA/mm, ON-state/OFF-state current (ION/IOFF) ratio of 109–1010, subthreshold swing (SS) of 76 mV/decade, VBD of 810 V, and specific RON (Ron, sp) of 0.63 mΩ ⋅ cm2. It also possesses excellent VTH hysteresis, temperature stability, and dynamic RON characteristics. These results suggest that the proposed device is very suitable for high power switching applications. [ABSTRACT FROM AUTHOR]

Hydrogen-terminated (C-H) diamond has a high current density owing to the 2-D hole gas (2DHG) on its C-H diamond surface. The C-H diamond metal-oxide-semiconductor field-effect transistor (MOSFET) has high-breakdown-voltage characteristics but exhibits normally-ON operation. For security and energy-saving purposes, we fabricated the diamond cascode using the C-H diamond p-channel field-effect transistor (p-FET) combination with the normally- OFF silicon p-FET. The diamond cascode exhibits normally- OFF characteristics and a high breakdown voltage of more than 1.7-kV. [ABSTRACT FROM AUTHOR]