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This article introduces an innovative non‐volatile associative memory (AM) that leverages spintronic synapses, employing magnetic tunnel junctions (MTJ) in conjunction with neurons constructed using carbon nanotube field‐effect transistors (CNTFETs). Our proposed design represents a significant advancement in area optimization and outperforms prior designs. We adopt MTJ‐based spintronic devices due to their remarkable attributes, including dependable reconfigurability and nonvolatility. Simultaneously, CNTFETs effectively address the longstanding limitations traditionally associated with MOSFETs. In this work, our proposed design undergoes rigorous simulations that account for process variations. The results demonstrate that our AM system closely approximates its ideal mathematical model, even with significant process variations. Furthermore, we investigate the impact of Tunnel Magnetoresistance (TMR) on the performance of our proposed AM system. Our investigations reveal that, even with a TMR as low as 100%, our design matches and often surpasses the performance of its counterparts operating with a TMR of 300%. This achievement holds profound significance from a fabrication standpoint, as fabricating MTJs with high TMR values can be intricate and costly. Overall, our novel AM system represents a significant breakthrough in emerging technologies, harnessing the unique strengths of spintronic synapses and advanced carbon nanotube transistors while robustly addressing challenges in performance and variability. [ABSTRACT FROM AUTHOR]

In‐memory computing and sensing can break through the limit of the traditional Von Neumann architecture where information storing and computing units are separated. Recently the topographic creation of a ferroelectric domain wall in separation of two antiparallel domains in LiNbO3 single‐crystal films integrated with the Si substrate has been the focus of such research. Here, the additional freedom of the light stimulus is reported to modulate the domain wall current significantly, enabling applications in nonvolatile domain wall memory, photodetector, and image recognition processor. These measurements shows the fantastic photosensitivity of 2D domain walls where the photocurrent varies nonlinearly against the accumulative pulse number. With this observation, an associated learning model is constructed to stimulate neuromorphic computing (with a recognition accuracy of 90%) using an artificial neuromorphic network of domain walls. The research promotes the multifold development of artificial intelligence using domain‐wall nanodevices sensitive to both optical and electrical stimulus. [ABSTRACT FROM AUTHOR]

Organic electrochemical transistors (OECTs) are promising candidates for artificial synapses to achieve high‐performance synaptic characteristics. While most research has focused on modifying the properties of organic semiconductors for efficient ion doping, there is a lack of systematic investigation into the relationship between ion‐mediated mechanisms and synaptic performance. In this study, an effective strategy for enhancing electrochemical doping and de‐doping by utilizing different coulombic anions is proposed. The findings reveal that doped ions in the channel layer affect inter‐ion interactions, influencing the non‐volatile effects by improving the doping performance of the synaptic device. Moreover, electrochemical analysis indicates that ions in the channel layer are sequentially de‐doped, enabling high linearity and symmetry. The fabricated devices demonstrate high‐performance synaptic properties including a retention time of ≈102 s with ≈50% retention over peak current and near‐ideal long‐term potentiation/long‐term depression (LTP/LTD) through effective electrochemical doping and de‐doping. These results show that controlling both the properties of organic semiconductors and ion interactions in the electrolyte is crucial for OECTs, opening up various applications for neuromorphic computing. [ABSTRACT FROM AUTHOR]

A nonlinear system, exhibiting a unique asymptotic behaviour, while being continuously subject to a stimulus from a certain class, is said to suffer from fading memory. This interesting phenomenon was first uncovered in a non-volatile tantalum oxide-based memristor from Hewlett Packard Labs back in 2016 out of a deep numerical investigation of a predictive mathematical description, known as the Strachan model, later corroborated by experimental validation. It was then found out that fading memory is ubiquitous in non-volatile resistance switching memories. A nonlinear system may however also exhibit a local form of fading memory, in case, under an excitation from a given family, it may approach one of a number of distinct attractors, depending upon the initial condition. A recent bifurcation study of the Strachan model revealed how, under specific train stimuli, composed of two square pulses of opposite polarity per cycle, the simplest form of local fading memory affects the transient dynamics of the aforementioned Resistive Random Access Memory cell, which, would asymptotically act as a bistable oscillator. In this manuscript we propose an analytical methodology, based on the application of analysis tools from Nonlinear System Theory to the Strachan model, to craft the properties of a generalised pulse train stimulus in such a way to induce the emergence of complex local fading memory effects in the nano-device, which would consequently display an interesting tuneable multistable oscillatory response, around desired resistance states. The last part of the manuscript discusses a case study, shedding light on a potential application of the local history erase effects, induced in the device via pulse train stimulation, for compensating the unwanted yet unavoidable drifts in its resistance state under power off conditions. [ABSTRACT FROM AUTHOR]

Abstract This article introduces an innovative non‐volatile associative memory (AM) that leverages spintronic synapses, employing magnetic tunnel junctions (MTJ) in conjunction with neurons constructed using carbon nanotube field‐effect transistors (CNTFETs). Our proposed design represents a significant advancement in area optimization and outperforms prior designs. We adopt MTJ‐based spintronic devices due to their remarkable attributes, including dependable reconfigurability and nonvolatility. Simultaneously, CNTFETs effectively address the longstanding limitations traditionally associated with MOSFETs. In this work, our proposed design undergoes rigorous simulations that account for process variations. The results demonstrate that our AM system closely approximates its ideal mathematical model, even with significant process variations. Furthermore, we investigate the impact of Tunnel Magnetoresistance (TMR) on the performance of our proposed AM system. Our investigations reveal that, even with a TMR as low as 100%, our design matches and often surpasses the performance of its counterparts operating with a TMR of 300%. This achievement holds profound significance from a fabrication standpoint, as fabricating MTJs with high TMR values can be intricate and costly. Overall, our novel AM system represents a significant breakthrough in emerging technologies, harnessing the unique strengths of spintronic synapses and advanced carbon nanotube transistors while robustly addressing challenges in performance and variability.

The emerging multi-value logic technology in memory systems has increased data storage capacity and power efficiency. In this paper, to address the power consumption challenge of ternary memory, a ternary precharge sense amplifier (TPCSA)-based magnetic random-access memory (MRAM) is designed and simulated for the first time. The proposed TPCSA-MRAM leverages both low power consumption and high performance of TPCSA-based memory and nonvolatility of the magnetic tunnel junction (MTJ). The proposed TPCSA-MRAM also offers high resilience against process variation, which is critical in the ternary circuits. This process variation resilience is validated through Monte Carlo and process corners simulations. A ternary memory array architecture is also designed and simulated based on the proposed design to show the scalability of the proposed TPCSA-MRAM. Detailed post-layout simulations using the 7nm FinFET technology as an industrially available technology for digital circuit fabrication indicate that the proposed design’s read and write energy is up to 80% and 37% lower than the existing nonvolatile ternary memories.

Emerging 2D nonvolatile Schottky‐barrier‐field‐effect transistors (NSBFETs) are envisaged to build a promising reconfigurable in‐memory architecture to mimic the brain. Herein, a vertically stacked multilayered graphene (MGr)‐molybdenum disufide (MoS2)‐tungsten ditelluride (WTe2) NSBFET is reported. The semimetal WTe2 with the charge‐trapping effect enables the simultaneous integration of the electrode and the self‐gating function. The effective Schottky barrier height offset ΔΦB is programed from ΔΦB‐p = 132.6 meV to ΔΦB‐n = 109.4 meV, inducing the reversed built‐in electric field to make the NSBFET, so as to provide one with a multifunctional platform to integrate the nonvolatility and the reconfigurable self‐powered photo response. The reversible open‐circuit voltages of NSBFET synapse are programmed from −0.1 to 0.25 V and the self‐powered responsivity with reversed signs is tuned from 290 to −50 mA W−1, which enables the representation of a signed weight in a single device to enrich multiple optical sensing and computing capabilities. [ABSTRACT FROM AUTHOR]

Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and in-memory computing (IMC), but there is a rising interest in using memristive technologies for security applications in the era of internet of things (IoT). In this review article, for achieving secure hardware systems in IoT, low-power design techniques based on emerging memristive technology for hardware security primitives/systems are presented. By reviewing the state-of-the-art in three highlighted memristive application areas, i.e. memristive non-volatile memory, memristive reconfigurable logic computing and memristive artificial intelligent computing, their application-level impacts on the novel implementations of secret key generation, crypto functions and machine learning attacks are explored, respectively. For the low-power security applications in IoT, it is essential to understand how to best realize cryptographic circuitry using memristive circuitries, and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security. This review article aims to help researchers to explore security solutions, to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.

In this article, we report high-performance one-transistor-one-resistor (1T1R) FETs for nonvolatile memory application based on nanometer-thick indium oxide (In2O3) as channel material deposited by atomic layer deposition (ALD). ALD grown hafnium oxide (HfO2) and aluminum oxide (Al2O3) are used as gate dielectrics as well as insulator in resistive part. Two nonvolatile states with different threshold voltages are realized. High ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}} > 10^{10}$ at ${V}_{\mathrm {GS}} =0$ V, large memory window (MW) exceeding 10 V, and deep sub-60-mV/dec subthreshold slope (SS) are achieved on ALD In2O3 1T1R FETs. Channel length (${L}_{\mathrm {ch}}$) and channel thickness (${T}_{\mathrm {ch}}$) dependence of device properties are systematically investigated. Optimized In2O3 thickness is determined to 1.2 nm, balancing ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , MW, device variation, and stability. The fabrication process has a low thermal budget below 225 °C. Thus, these 1T1R FETs are back-end-of-line (BEOL) compatible and promising for monolithic 3-D integration to realize near-/in-memory computing. [ABSTRACT FROM AUTHOR]

• A strategy to realize nonvolatile magnetization reversal is proposed based on electric field control of interlayer coupling. • The dependence of interlayer coupling energy on electric field strength follows a continuous odd function in mathematics, guaranteeing the nonvolatility. • The feasibility of this strategy is demonstrated by a MnBi 2 Te 4 / h -BN/Fe 3 GaTe 2 / h -BN/MnBi 2 Te 4 junction. Achieving electric field control of nonvolatile magnetization reversal in van der Waals magnetic tunnel junctions (vdW MTJs) is of paramount importance for nanoscale spintronic devices with ultralow-power consumption and high-density storage. Here, a new and universal design strategy is proposed to realize nonvolatile magnetization reversal, which is based on electric field control of interlayer coupling. The nonvolatility benefits from the proposed special principle of vdW MTJ, in which the dependence of interlayer coupling energy on electric field strength follows a continuous odd function in mathematics. The feasibility of proposed strategy is proved by the MnBi 2 Te 4 / h -BN/Fe 3 GaTe 2 / h -BN/MnBi 2 Te 4 junction. The magnetization state of Fe 3 GaTe 2 can be reversed 180° by changing electric field directions. Moreover, the magnetization states can be preserved after removing electric field, demonstrating the nonvolatile magnetization reversal. Therefore, the present strategy provides an alternative approach to realize electric control of nonvolatile magnetization reversal in vdW MTJs for next-generation spintronic devices. [ABSTRACT FROM AUTHOR]

Approximate computing aims to reduce the power consumption and design complexity of digital systems with the cost of a tolerable error. In this article, two ultra-efficient magnetic approximate full adders are presented for computing-in-memory applications. The proposed ultra-efficient full adder blocks are coupled with a memory cell based on magnetic tunnel junction (MTJ) to allow for nonvolatility. Therefore, they can be power-gated when required. Both the proposed full adders have simple designs and are energy-efficient. Instead of introducing dedicated write-driver and read circuits, the restorer latch inverters are utilized to contribute to the read and write operations, which results in a lower complexity. The peripheral circuitries are designed based on the gate-all-around carbon nanotube field-effect transistor (GAA-CNTFET). The hardware simulation results show a 5.2 times improvement (78% reduction) in power-delay product (PDP), on average, compared with the previous fully nonvolatile approximate full adders. Utilizing the approximate adders in Gaussian filters to denoise a noisy image revealed that our proposed adders result in almost the same image quality as an accurate adder. Both our adders have an accurate carry output and two erroneous sum outputs. Nevertheless, these two erroneous outputs have a low-value gap, which results in higher quality in image processing applications. The results indicate that the proposed designs make an effective tradeoff between energy and accuracy, which is the main goal of approximate computing. [ABSTRACT FROM AUTHOR]

This article presents a majority-logic device, called sttMAJ, based on spin-transfer torque magnetic tunnel junctions (STT-MTJs). sttMAJ devices make it possible to build Boolean and non-Boolean circuits without any transistors. We leverage a physics-based model of sttMAJ device to the design of different highly scalable current-mode logic circuits and neuromorphic-computing/image-processing applications. The functionality of sttMAJ-based circuits is verified using the SPICE circuit simulator. The simulation results reveal that the gate device not only provides a simple and powerful structure (in terms of implementing digital functions and image-processing applications with a small number of devices) but also offers high performance due to its better electrical properties. [ABSTRACT FROM AUTHOR]

As the technology node shrinks to the nanoscale, several challenges such as high power density have become more critical. One of the most effective methods for addressing these problems is utilizing spintronic devices based on magnetic tunnel junction (MTJ). Furthermore, approximate computing is an emerging paradigm for reducing the power consumption and design complexity in some applications, where the computational error is tolerable. In this paper, a novel non-volatile hybrid MTJ/FinFET-based approximate full adder is presented. The proposed design uses the spin Hall effect (SHE) assisted method for writing data on MTJs, which significantly reduces the power consumption and write energy of the MTJ switching as compared to the conventional STT writing method. The proposed design leads to an effective trade-off between efficiency and quality, as it has a simple and energy-efficient structure, while it provides an acceptable quality in applications like approximate image processing. The circuits are simulated using HSPICE with 14 nm FinFET and SHE perpendicular-anisotropy MTJ models. According to the extensive HSPICE and MATLAB simulations, the proposed approach improves power consumption, delay, power-delay product, and energy-delay product on average by 47%, 53%, 75%, and 86%, while achieving relatively better quality metrics as compared to its state-of-the-art counterparts. [ABSTRACT FROM AUTHOR]

This paper presents a new floating memristor emulator (FME) consisting of only a single current backward transconductance amplifier (CBTA) as the active element and two grounded capacitors. The proposed FME-based on CBTA enjoys some advantages that include minimum active and passive elements without using an analog multiplier circuit and grounded passive elements which are attractive for the integrated circuit. In addition, excluding the DC power supply voltage, it does not use bias voltage and/or bias current. The designed memristor circuit provides incremental and decremental characteristics without changing circuit topology or using a switching mechanism and it is implemented with a minimum of circuit elements. All simulation results for the memristor emulator were obtained as expected when compared with fabricated memristors. [ABSTRACT FROM AUTHOR]

Complementary metal oxide semiconductor (CMOS) downscaling leads to various challenges, such as high leakage current and increase in radiation sensitivity. To solve such challenges, hybrid MTJ/CMOS technology-based design has been considered as a very promising approach thanks to the high speed, low power, good scalability, and full compatibility of magnetic tunnel junction (MTJ) devices with CMOS technology. One important application of MTJs is the efficient utilization in building nonvolatile look-up tables (NV-LUTs) used in reconfigurable logic. However, NVLUTs face severe reliability issues in nanotechnology due to the increasing process variations, reduced supply voltage, and high energetic particle strike at sensitive nodes of CMOS circuits. This paper proposes a nonvolatile radiationhardened look-up table (NVRH-LUT) for advanced reconfigurable logic. Compared with previous works, the proposed NVRH-LUT is fully robust against single-event upsets and also single-event double-node upsets that are among the main reliability-challenging issues for NV-LUTs. Results have shown that NVRH-LUT not only provides increasing reliability and reduced bit error rate but also offers low delay and low energy consumption. [ABSTRACT FROM AUTHOR]

In this paper, we present a memristor emulator based on voltage difference transconductance amplifier (VDTA). The proposed memristor emulator circuit contains only one VDTA as an active element and single grounded capacitor which benefits from the integrated circuit. Furthermore, it can be utilized MOS-capacitance instead of the external capacitor in the circuit. The complete memristor emulator is laid by using Cadence Environment using TSMC $0.18\ {\boldsymbol \mu }\text{m}$ process parameters. It occupies an area of $35.7\ {\boldsymbol \mu }\text{m}\,\,\times 29\ {\boldsymbol \mu }\text{m}$. Its simulation results are given to demonstrate the performance of the presented memristor emulator in different operating frequencies, process corner, and radical temperature changes. Moreover, prototype circuit is implemented to confirm the theoretical analysis by employing the single LM13700 commercial device as an active element. Experimental results of the designed memristor emulator are given to investigate its ability for different operating frequencies, the capacitance value and resistor value and DC supply voltage. The experimental results are in accordance with theoretical analyses and simulation results. [ABSTRACT FROM AUTHOR]

Very large-scale integrated circuit (VLSI) design faces many challenges with today’s nanometer CMOS technology, including leakage current and reliability issues. Magnetic tunnel junction (MTJ) hybrid with CMOS transistors can offer many advantages for future VLSI design such as high performance, low power consumption, easy integration with CMOS and also nonvolatility. However, MTJ-based logic circuits suffer from a reliability challenge that is the read disturbance issue. This paper proposes a new nonvolatile magnetic flip-flop (MFF) that offers a disturbance-free sensing and a low power write operation over the previous MFFs. This magnetic-based logic circuit is based on the previous two-in-one (TIO) MTJ cell that presents the aforementioned attributes. Radiation-induced single event upset, as another reliability challenge, is also taken into consideration for the MFFs and another MFF robust against radiation effects is suggested and evaluated. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of many matrix and array operations. We describe in detail the circuit design techniques enabling the proposed architectures, as well as the viability of emerging memory technologies based on ferroelectric transistors (FEFETs) for our design. Compared to FEFET memory with standard 1-D access, we achieve 5% energy savings for the proposed memory featuring 2-D read and 93% energy savings for memory with 2-D read and write, for 32 bit column read and write. In addition, we get around 11% and 95% delay savings for 2-D read-enabled memory and 2-D read-write memory, respectively. The application analysis shows that 2-D read-enabled memory achieves around 86% average decrease in row-buffer transactions in $256\times 256$ size matrix operations without any array area increase. The 2-D read write memory offers 87% decrease in row-buffer transactions with 28.5% increase in array area compared to the 1-D FEFET memory. [ABSTRACT FROM AUTHOR]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

The MTJ-based circuits have been considered as a candidate for next generation digital integrated circuits thanks to their attractive features such as nonvolatility, low leakage current, high endurance, and CMOS integration compatibility. However, incurred energy and delay by reconfiguration of their employed conventional MTJs limit their application. Besides, the issue of read-disturbance is another challenge in such MTJ-based circuit designs. In this article, a new magnetic-based full-adder (MFA) circuit based on a new three-terminal two-in-one magnetic tunnel junction (TIO-MTJ) cell is proposed. Comparing with the previous MFA circuits, the proposed circuit offers a lower energy for the write operation and also a disturbance-free reading. Two improved structures based on the proposed MFA are also suggested to obtain the advantages of nonvolatility for the power-gating architectures and also radiation hardening for the radiation harsh environments. [ABSTRACT FROM AUTHOR]

Spin-transfer torque random access memory (STT-RAM) is an emerging storage technology that is considered widely thanks to its attractive features such as low power consumption, nonvolatility, scalability and high density. STT-RAMs are comprised of a hybrid design of CMOS and spintronic units. Magnetic tunnel junction (MTJ) as the basic element of such hybrid technology is inherently robust against radiation induced faults. However, the peripheral CMOS component for sensing the resistance of the MTJs are prone to be affected by energetic particles. This paper proposes low power, nonvolatile and radiation hardened latch and lookup table circuits based on hybrid CMOS/MTJ technology for the next generation integrated circuit devices. Simulation results revealed that, the proposed circuits are fully robust against single event upsets (SEU) and also single event double node upsets (SEDU) that are of the main reliability challenging issues in current sub-nanometer CMOS technologies. [ABSTRACT FROM AUTHOR]

In this paper, we show that parasitic elements have a significant effect on the dynamics of memristor circuits. We first show that certain -terminal elements such as memristors, memcapacitors, and meminductors can be used as nonvolatile memories, if the principle of conservation of state variables hold by open-circuiting, or short-circuiting, their terminals. We also show that a passive memristor with a strictly-increasing constitutive relation will eventually lose its stored flux when we switch off the power if there is a parasitic capacitance across the memristor. Similarly, a memcapacitor (resp., meminductor) with a positive memcapacitance (resp., meminductance) will eventually lose their stored physical states when we switch off the power, if it is connected to a parasitic resistance. We then show that the discontinuous jump that circuit engineers assumed to occur at impasse points of memristor circuits contradicts the principles of conservation of charge and flux at the time of the discontinuous jump. A parasitic element can be used to break an impasse point, resulting in the emergence of a continuous oscillation in the circuit. We also define a distance, a diameter, and a dimension, for each circuit element in order to measure the complexity order of the parasitic elements. They can be used to find higher-order parasitic elements which can break impasse points. Furthermore, we derived a memristor-based Chua's circuit from a three-element circuit containing a memristor by connecting two parasitic memcapacitances to break the impasse points. We finally show that a higher-order parasitic element can be used for breaking the impasse points on two-dimensional and three-dimensional constrained spaces. [ABSTRACT FROM AUTHOR]

Given the synergy of optogenetics and bioimaging in neuroscience, it is possible for light to simultaneously modulate and visualize synaptic events of optoelectronic synaptic devices, which are building blocks of a neuromorphic computing system with optoelectronic integration. Here we demonstrate the realization of the simultaneous modulation and visualization of synaptic events by using optically stimulated synaptic devices based on the heterostructure of fluorescent silicon quantum dots (Si QDs) and monolayer molybdenum disulfide (MoS 2 ). The charge-transfer-enabled photogating effect of the Si QDs/MoS 2 heterostructure leads to the nonvolatility of the synaptic devices, which exhibit important synaptic functionalities and synchronous fluorescence upon optical stimulation. An array of the Si QDs/MoS 2 optoelectronic synaptic devices is well-employed to mimic robust neural population coding. Defective devices in this array may be pinpointed by the absence of their fluorescence. This work has an important implication for the development of synaptic devices facilitating the system-level diagnosis and device-level positioning of a neuromorphic computing system.

The energy consumption during the operation of organic nonvolatile memory devices fabricated on a flexible polyethylene naphthalate (PEN) substrate is investigated. For bistable resistive memory devices, the applied external voltage and time are essential factors for switching the memory cell from the OFF to ON state because the amounts of voltage and time determine the applied energy needed to set the memory cell. Using the composite material polyimide (PI) and [6,6]‐phenyl‐C61 butyric acid methyl ester (PCBM) as the active layer of the bistable resistive memory devices on a flexible PEN substrate, nonvolatile unipolar switching behavior and good electrical reliability of PI:PCBM memory devices are observed, and the relationship between the applied energy and the switching characteristics for various applied voltages and times is characterized. The results of the performed experiments show that higher ON state currents are reached as greater set voltages or times are applied, and reliable switching behavior is observed at over ≈10−6 J of applied energy with at least 4 V of applied voltage and 10 ms of pulse time. [ABSTRACT FROM AUTHOR]

Magnetoresistance (MR) is highly exploitable to future spintronics devices, such as random-access memory, magnetic sensors, and spin-based neuromorphic electronics. Conventionally the enhanced MR in manganite always companies a sacrifice of Curie temperature, which limits its widespread application potential. Here we report a high-temperature survived MR in a La 0.67 Sr 0.33 MnO 3 (LSMO) film grown on a piezoelectric substrate. The lattice mismatch between the film and substrate creates a self-assembled nano-matrix with two types of nanoscale matrices, namely [001]- and [101]-orientated LSMO magnetic domains. In this structure, the MR can reach -67% at even 350 K. Furthermore, the resistance of LSMO is electric-field-tunable to multiple resistance states by electrically modulating the biaxial strain imposed by the underlying piezoelectric substrate, an additional ∼14.2% electroresistance (ER) can be obtained. The achievements of high-temperature substantial MR and its electrical tunability in the nano-matrix manganite are of use to future multi-state memory devices in both spintronics and straintronics. [Display omitted] [ABSTRACT FROM AUTHOR]

Large switching current and long switching time have significantly limited the adoption of spin-transfer torque random access memory (STT-RAM). Technology scaling, moreover, makes it very challenging to reduce the switching current while maintaining the reliability of magnetic tunneling junction (MTJ) to be similar to that of the earlier generations. In this work, we shall exploit a key insight that in the most on-chip caches where STT-RAM is most likely to be deployed, the lifespan of the data stored in the memory cells is much shorter than the data retention time requirement assumed in STT-RAM development, namely, 4 \sim 10 years. We also quantitatively investigated the possibility of trading off MTJ nonvolatility for improved switching performance, e.g., the switching time and/or current, under architectural level guidance. We further proposed and evaluated a hybrid memory design technique that partitions the on-chip STT-RAM cache into two parts with different nonvolatility performances so as to better fit the diverse retention time requirements of different data sets. [ABSTRACT FROM AUTHOR]

Atomic switches are nanoionic devices that control the diffusion of metal cations and their reduction/oxidation processes in the switching operation to form/annihilate a metal atomic bridge, which is a conductive path between two electrodes in the on-state. In contrast to conventional semiconductor devices, atomic switches can provide a highly conductive channel even if their size is of nanometer order. In addition to their small size and low on-resistance, their nonvolatility has enabled the development of new types of programmable devices, which may achieve all the required functions on a single chip. Three-terminal atomic switches have also been developed, in which the formation and annihilation of a metal atomic bridge between a source electrode and a drain electrode are controlled by a third (gate) electrode. Three-terminal atomic switches are expected to enhance the development of new types of logic circuits, such as nonvolatile logic. The recent development of atomic switches that use a metal oxide as the ionic conductive material has enabled the integration of atomic switches with complementary metal-oxide-semiconductor (CMOS) devices, which will facilitate the commercialization of atomic switches. The novel characteristics of atomic switches, such as their learning and photosensing abilities, are also introduced in the latter part of this review. [ABSTRACT FROM AUTHOR]

[Display omitted] • Ionogel fiber (IGF)-based sensor is fabricated via exceedingly simple mold method. • The IGF exhibits distinctive self-adhesiveness and improved anti-freezing property. • The sensor showed high sensitivity (GF = 6.8) and low detection threshold (<0.5%). • The sensor works well in a wide temperature range(-80 ∼ 150 °C) or vacuum environment. Stretchable conductive sensors based on iontronics are key components for next generation sensing systems in wearable devices or soft robots. Considering the narrow working temperature range of hydrogels-based ionic conductors, ionogel with inherent non-volatility and survivability over a wide temperature range, is proposed to prepare gel fiber-based sensor, via exceedingly simple mold method. Zwitterionic monomer [2-(Methacryloyloxy) ethyl] dimethyl-(3-sulfopropyl) (SBMA) and acrylamide (AM) were selected to construct the crosslinked ionogel networks. The ion–dipole, dipole–dipole interactions and interchain hydrogen bonds introduced in the ionogel fiber (IGF) system, simultaneously improve the gel strength and endow the IGF with distinctive properties. The resultant IGF exhibits unique self-adhesiveness, excellent transparency, tunable mechanical properties and ultrahigh stability in various extreme environments. Moreover, as a strain sensor, the as-fabricated IGF is characteristic by outstanding sensitivity with a gauge factor (GF) of 6.20, low detection threshold (0.5% strain) and high durability (1000 cycles at 100% strain). The sensor works well in harsh environments, exhibiting an enlarged working temperature range (–80 ∼ 150 °C) and high tolerance under vacuum (1.325 kPa). We anticipate this IGF-based sensor to make up for the vacancy of flexible sensors in extreme circumstances, thus expanding more application scenarios. [ABSTRACT FROM AUTHOR]

With the rising demand for information security, there has been a surge of interest in harnessing the intrinsic physical properties of device for designing a secure logic circuit. Here we provide an innovative approach to realize the secure optoelectronic logic circuit based on nonvolatile van der Waals (vdW) heterostructure phototransistors. The phototransistors comprising WSe 2 and h-BN flakes exhibit electrical tunability of nonvolatile conductance under cooperative operations of electrical and light stimulus. This intriguing feature allows the phototransistor to work as a building block for the design of secure optoelectronic logic circuit in which the information encryption can be directly achieved with a designed secret key. On the basis of this approach, we assemble two phototransistors into an optoelectronic hybrid circuit and implement a functionally complete set of logic gates (i.e., NOR, XOR, and NAND) in a reconfigurable manner. Our findings highlight the potential of nonvolatile phototransistors for the development of reconfigurable secure optoelectronic circuits.

Reversible and nonvolatile modulation of magnetization switching characteristic in ferromagnetic materials is crucial in developing spintronic devices with low power consumption. It is recently discovered that strain engineering can be an active and effective approach in tuning the magnetic/transport properties of thin films. The primary method in strain modulation is via the converse piezoelectric effect of ferroelectrics, which is usually volatile due to the reliance of the required electric field. Also the maximum amount of deformation in ferroelectrics is usually limited to be less than 1%, and the corresponding magnetoelastic strain energy introduced to ferromagnetic films is on the order of 10(4) J/m(3), not enough to overcome magnetocrystalline anisotropy energy (Ku) in many materials. Different from using conventional strain inducing substrates, this paper reports on the significantly large, reversible, and nonvolatile lattice strain in the L10-FePt films (up to 2.18%) using nonelectrically controlled shape memory alloy substrates. Introduced lattice strain can be large enough to effectively affect domain structure and magnetic reversal in FePt. A noticeable decrease of coercivity field by 80% is observed. Moreover, the coercivity field tunability using such substrates is nonvolatile at room temperature and is also reversible due to the characteristics of the shape memory effect. This finding provides an efficient avenue for developing strain assisted spintronic devices such as logic memory device, magnetoresistive random-access memory, and memristor.