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A transimpedance amplifier (TIA)—with gamma-irradiation resistance of over 1 MGy—based on a novel 4H-SiC complementary MOS (CMOS) technology was fabricated. This TIA is robust enough to be applied in measuring instruments installed in nuclear power plants or other harshly irradiated environments. The SiC CMOS transistors comprising the TIA feature a thin (8-nm-thick) gate oxide to reduce the threshold-voltage shift ( ${V}_{{\text {th}}}$ ) due to irradiation by more than 90% compared with that of the conventional transistors. Oxynitride protection formed at the SiC–SiO2 interface in the thin gate-oxide region suppresses the deterioration of mobility by interface traps generated by the gamma radiation. The TIA consisting of these SiC-CMOS transistors operated properly up to at least 1.2 MGy without an increase in the offset voltage, although its open-loop gain was degraded due to deteriorated mobility of the p-channel metal–oxide–semiconductor field-effect transistor (MOSFET). On the other hand, increasing the drain leakage current in the nonactive region impeded further improvement of the SiC TIA under a high integral dose. To decrease the drain leakage current, a structure with a high doping concentration layer between the source and the drain in the nonactive region was fabricated. The structure stops the parasitic transistor turning on and the trap-assisted current increasing. The leakage current of the improved structure is about 42% lower than that of a conventional structure.

We report the physical and electrical characterization of the inversion layer carrier and the shallow interface trap sites with n-and p-channel SiC-MOSFET in terms of high temperature electronics. This work proposes a physical model that explains the difference between Id-Vg measurement result and calculation result supposing the ideal condition with Pao and Sah double ideal in room temperature. The measurement at 500°C confirmed our model so that inversion carrier were thermally excided, they could not be easily trapped by shallow trap sites, and Id-Vg measurement result approached the ideal condition.

For a variety of applications from mobile to high-performance computing, the power consumption of very-large-scale-integrated (VLSI) circuits is a serious issue. The scaling rule has been a paradigm for miniaturizing complementary metal-oxide-semiconductor (CMOS) field-effect-transistors (FETs) in VLSI circuits for a long period. In the ideal scaling rule, the supply voltage Vdd should decrease in proportion to the miniaturization of the transistor. This Vdd reduction has roughly been successful so far. In extremely scaled transistors such as those in the 45-nm logic node and beyond, however, it is very difficult to further decrease Vdd. Unless Vdd is reduced with the scaling rule, the power consumption of the LSI will increase significantly due to an increase in both operational and standby-leakage power (Sakurai, 2004; Chen, 2006). The primary cause of this difficulty is widely recognized as the increase in threshold voltage (Vth) variation of CMOSFETs, because Vdd should be set higher considering the margin to the increased Vth variation (Takeuchi et al., 1997). Variation of transistor characteristics, primarily Vth variation, is increasing substantially in sub-100-nm technologies. This makes the Vdd reduction, required by the scaling rule, difficult, and significantly increases the power consumption of an LSI chip. Here, power consumption P of an inverter, which is the representative LSI unit circuit, is defined as

Ultra-low power technology has drawn much attention recently as the number of connecting (Internet-of-Things) devices rapidly increases. The silicon-on-thin-buried oxide (SOTB) technology is a CMOS device technology that uses fully depleted silicon-on-insulator (FDSOI) transistors with a thin buried oxide layer enabling enhanced back-bias controllability and that can be monolithically integrated with the conventional bulk CMOS circuits. It can significantly reduce both the operation and the standby powers by taking advantage of low-voltage operation and back-biasing, respectively. In this chapter, advantages of the SOTB technology in terms of ultra-low power, circuits design and chip implementation examples including ultra-low power micro-controllers operating with harvested power, reconfigurable logic circuits, analog circuits, are reviewed, and a future perspective is shown.

This special section of the IEEE JOURNAL OF ELECTRON DEVICES SOCIETY is dedicated to select papers presented at the 2019 IEEE S3S Conference, which was held Oct. 14– 17, 2019 in San Jose, CA, USA. The papers were selected based on their technical merits and relevance to the Journal and with the feedback from the Technical Committee of the conference and session chairs.

Four write stability metrics for the characterization of six-transistor SRAM cells were experimentally evaluated and compared at low supply voltage ( $V_{\mathrm {DD}})$ . A silicon-on-thin-BOX technology with reduced body doping was used to achieve low voltage operation. It was confirmed that both bitline and wordline methods are preferable in that they yield metrics that follow normal distributions, which is practically beneficial for the yield estimation. On the contrary, different from at high $V_{\mathrm {DD}}$ , both write static noise margin from write butterfly curve and write ${N}$ -curve current ( $I_{W})$ exhibit non-normal probability distributions. The origins of the non-normality are analyzed in detail.

The paper presents a receiver design operating at 312–315 MHz frequency band for wireless sensor networks. The proposed architecture uses synchronized on–off-keying (S-OOK) modulation scheme, which includes clock information together with data, providing self-synchronization ability for the receiver without a separate clock and data recovery circuit. In addition, a new technique is also proposed to reduce active time of the RF font-end for better energy efficiency. The receiver architecture is verified by using discrete RF modules and FPGAs, then VLSI design is carried out on 65 nm Silicon-On-Thin-Buried-Oxide (SOTB) CMOS technology and simulated using SPICE models to illustrate effectiveness of the proposed architecture. Post-layout simulation shows −58.5 dBm sensitivity with 1.36 μW and 8.39 μW power consumption corresponding to 10 kbps and 100 kbps data rate, respectively.

This paper reports a novel method that reduces fabrication period of customized MEMS sensors. A 3D printing method with a high-current plasma focused ion beam (FIB) system was developed and applied to MEMS sensor fabrication for the first time. Capacitive MEMS vibration sensors fabricated using the conventional lithography process and the 3D printing process were compared. The difference in the resonance frequency was as small as 4%. Compared to the conventional process, the 3D printing process reduced the fabrication period by ∼80%.

This special section of the IEEE Journal of Electron Devices Society is dedicated to select papers presented at the 2018 IEEE S3S Conference, which was held Oct. 15–18, 2018 in Burlingame, CA, USA. The papers were selected based their technical merits and relevance to the Journal and with the feedback from the Technical Committee of the conference and session chairs.

The authors demonstrate an ultra-low-power microcontroller unit (MCU) with an embedded atom-switch ROM, which performs 0.39-V operation voltage and 18.26-pJ/cycle minimum active energy (or 18.26-µW/MHz minimum active power) at 14.3 MHz. The MCU is fabricated using an embedded atom-switch process with a hybrid silicon-on-thin-buried-oxide (SOTB) core and bulk I/O transistors. The atom switch is suitable for an ultra-low-voltage operation because of its high on/off conductance ratio. The SOTB CMOS with a body-bias voltage control realizes a high operation frequency of 40 MHz at 0.54 V and an ultra-low sleep power of 0.628 a#x00B5;W, simultaneously.

Highly energy efficient CMOS circuits are required in theinternet-of-things (IoT) era since a great number of smallelectronic apparatuses process and communicate data. Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy (Emin) point (MEP) is effective, most of the scaled circuits operate with far higher energy than Emin. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control.[1,2] These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. The MEP operation is generally very slow, e.g. less than 1MHz. The variable Vth approach with adaptive back-bias control can mitigate the situation of decreasing energy as low as possible down to MEP while satisfying the required frequency. Another obstacle is the variability of transistors, which degrades operation margin especially at low Vdd. To solve these problems, we are developing silicon on thin buried oxide (SOTB) [3-4]. In this paper, we demonstrate SOTB’s small variability, back-bias control, and ULV circuit operation. SOTB Device Results A cross-section of the SOTB/bulk hybrid CMOS and a TEMphoto are shown in Figs. 1 and 2. The back-bias voltages, Vbn and Vbp, are applied to the well regions below BOX. The local interconnect by the silicide at the well contact region contributes to improving the back-bias voltage stability. Details of the SOTB process and electrical characteristics are described in [3]. Very small Vth and Ion variability was demonstrated [3] for one million transistors The Pelgrom coefficient was ~1.3 mVμm, the smallest level taking the gate-oxidethickness (Tinv = 2.4 nm) into account. With this improvement, we confirmed 6-T SRAM operation (2 Mbit) at less than 0.4 V (Fig.3 (a)) with a 5.5-ps access time and demonstrated that the minimum operating voltage can be controlled at SOTB Circuit Design and ULV Operation We developed a standard cell library for the SOTB technology. The SOTB design flow is basically the same as that for the bulk technology. Using our SOTB flow, various logic circuits were designed and ULP operations were confirmed, such as an accelerator [5] and flex-power FPGA with back biasing [6]. We designed a micro-controller chip dedicated to the sensor-node application [7]. This chip operated at Vdd = 0.35 V and consumed only E = 13.4 pJ. The sleep current was only 0.14 μA. We demonstrated sensor-node operation. The CPU was operated with a single PV cell at Acknowledgment This work was performed as “Ultra-Low Voltage Device Project" funded and supported by METI and NEDO. References [1] R. Tsuchiya et al., IEDM, p. 631 (2004). [2] Y. Morita et al., VLSI Tech., p. 166, (2008). [3] Y. Yamamoto et al., VLSI Tech., p.212 (2013). [4] H. Makiyama et al., IEDM, p.812 (2013). [5] H. Su et al., IEICE, 113, RECONF 2013-52, 71.[6] H. Koike et al., S3S Conf., 5a.5 (2013). [7] K. Ishibashi et al.,COOL Chips XVII (April 2014). Figure 1

Although a large amount of research on Li ion transportation has been carried out with the aim of improving the properties of lithium ion batteries, there has been little detailed research on electron conduction. Hence, we have been focusing on improving the charge/discharge performance of lithium ion batteries by increasing the electron conductivity of the electrodes. The electron conductivity of crystalline tungsten trioxide (WO 3 ) was found to be increased by N 2 annealing owing to the generation of oxygen vacancies. It was clarified that increasing the conductivity of the electrodes can improve the performance of lithium ion batteries, particularly their charge/discharge speed and reversibility. Additionally, the best performance was observed in a sample subjected to high-temperature annealing at 700 °C in N 2 ambient, which decreased the resistivity of the WO 3 electrode by five orders of magnitude and simultaneously changed the monoclinic crystalline structure into a cubiclike structure into which Li ions are more easily intercalated. Therefore, to enhance the charge/discharge performance of lithium ion batteries, electron conduction should be a focus of research. Crystalline WO 3 was also demonstrated to be a promising material for electrodes since oxygen vacancy generation can be induced by a simple annealing treatment, improving the electron conduction and Li ion transportation.

Progress in FDSOI research and development is reviewed.Process technology and electrical characteristics of FDSOI CMOS transistors are described.Low-voltage CMOS circuits utilizing the FDSOI technology are described. Scaling the CMOS device has continuously improved its functionality and performance while lowering its power consumption and price. However, the current "scaled CMOS" technology faces several problems regarding power consumption, and a migration to new transistor structures is proceeding. "Fully depleted silicon on insulator" (FDSOI) technology can lower power consumption and improve performance of CMOS circuits with a capability of low-voltage operation. This article reviews advances in FDSOI technology: device structure, back-bias control function, fabrication process, demonstration of small variability of transistors, reliability including soft error, low voltage circuit design and silicon verification, and improvement in the energy efficiency of CMOS logic circuits. The strong requirement of further improvement in energy in the near future is finally pointed out.

We report a new approach for improving the recharging and discharging speed of lithium ion batteries based on understanding of the electron conduction mechanism of tungsten trioxide (WO 3 ) powder thin films fabricated from nanoparticles and used in lithium ion battery electrodes. Resistivity measurements are carried out after annealing in N 2 or 5% O 2 + 95% N 2 ambient. Annealing in N 2 ambient decreases the resistivity owing to the increased number of oxygen vacancies in the WO 3 thin film. Fitting results obtained from the resistivity are used to propose the simultaneous existence of two types of electron conduction mechanism, band conduction and nearest-neighbor hopping (NNH) conduction, contributing to electron conduction in WO 3 thin films.

This paper reports a novel method that reduces time for design customization of MEMS sensors. In this method, a design database (DB) that contains a variety of structural and characteristic parameter sets is built beforehand. Once required specifications are given, the DB is analyzed to select a candidate structure and obtain a guideline for a structural refinement. The number of time-consuming calculations by finite element method (FEM) is dramatically reduced by this method. In the case of a seesaw-type vibration sensor, it reduced the design customization time by 83%.

A 910nW 46fJ/conv 0.036mm2 delta sigma modulator is demonstrated. The chip was fabricated using 65nm SOTB (Silicon on Thin Buried oxide) technology, in which 13.4pJ/cycle 0.14uA Sleep Current CPU with 15nA VBB generator was obtained, resulting in achieving ultra-low power mixed signal IC for IoT applications.

A new type of silicon-based Tunneling FET (TFET) using semiconducting silicide Mg2Si/Si hetero-junction as source-channel structure is proposed and the device simulation has been presented. With narrow bandgap of silicide and the conduction and valence band discontinuous at the hetero-junction, larger drain current and smaller subthreshold swing than those of Si homo-junction TFET can be obtained. Structural optimization study reveals that low Si channel impurity concentration and the alignment of the gate electrode edge to the hetero-junction lead to better performance of the TFET. Scaling of the gate length increases the off-state leakage current, however, the drain voltage (Vd) reduction in accordance with the gate scaling suppresses the phenomenon, keeping its high drivability.

Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era.

Iron disilicide films (FeSi2) has been formed using stacked sputtered process using Fe and Si stacked structures. Owing to high reaction of thin films, FeSi2 phase has been confirmed at an annealing temperature as low as 600℃ (commonly fomed at over 800℃). The atomic ratio could be also controlled by this process. In addition, the films which are formed by this method are confirmed to have four kinds of activation energy.

Contributions of gate metal to electrical characteristics in AlGaN/GaN Schottky HEMT are reported. The focus is on the collapse of drain current associated with Schottky metals. Ni and W gate introduce electrically active defects under the gate metal in AlGaN layer. These electrically active defects induce the current collapse, higher gate leakage current, and frequency dispersion in C-V characteristics. Contrarily, TiN metal seems to mitigate the appearance of such electrically active defects. The observed current collapse is not the permanent but the recoverable degradation by means of light exposure irrespectively of the gate metals, suggesting the involvement of electron trapping on defects, particularly at the gate edge on the drain side where the electric field is the highest. The nitrogen vacancies in the AlGaN layer underneath the Schottky gate are plausible origin that is responsible for the electrically active defects based on the dependence of nitrogen concentration in TiN metal on the current collapse, which can be explained in terms of nitrogen diffusion from the AlGaN layer to the gate metal.

A semiconductor diamond draws an attention as a future semiconductor material for power devices. The main issue of the diamond is high resistance of the metal/n-diamond contact. It was reported that this is caused by the Fermi level pinning which forms a Schottky barrier of ~4.3 eV at the contact. In this research, J-V characteristics of four types of contacts using metal electrodes, Ti, Ni, NiSi2, and Ni3P and n-diamond with phosphorus concentration of 5 x 1019 cm-3 were investigated. It was observed that the contact with the Ni3P electrode flowed larger current than others at low bias voltages. This improvement might be caused by the phosphorus diffusion into the diamond substrate. It was shown that a metal electrode containing impurities has a possibility to decrease the contact resistance with n-diamond.

The reported compact SOI-MOSFET model hiroshima university starc igfet model-silicon on thin buried oxide (HiSIM-SOTB) has been developed for devices with ultrathin silicon on insulator (SOI) and buried oxide (BOX) layers. The potential distribution determined by the Poisson equation is accurately solved with the Newton iteration method across the SOI layer and in the substrate on the backside of the BOX for source and drain side of the device. All charges including accumulation and inversion charges on both side of the BOX are explicitly considered in the Poisson equation. It is found that different from the double-gate MOSFET, the influence of the impurity concentration of the bulk substrate below the BOX must be also explicitly considered to capture all measured properties of the silicon on thin buried oxide (SOTB) MOSFET. A further modeling challenge of the thin SOI and BOX layers, which had to be overcome, is that charge neutrality is not independently preserved at the front-gate oxide or at BOX side, but only totally within the whole device. Additionally it is found that, due to the consistent potential- and charge-based model formulation, the developed HiSIM-SOTB model can reproduce not only TCAD and measured SOTB device data but is even capable to predict the effects of structural variations, including the limiting case of the double-gate MOSFET structure.

The dependency of Ti atom composition in Ti-C mixed electrodes on Ohmic characteristics for AlGaN/GaN structure is examined by elucidating the role of both Ti and C atoms. Owing to AlGaN surface reduction by reaction with C atoms with thermal treatment, an enhanced reaction of Ti atoms and AlGaN layer has been confirmed. The border of reactive layer and the remaining AlGaN layer has shown rather uniform interface, which is contrast to conventional metallic spike formation. Higher Ti atom composition has revealed lower Ohmic contact resistance, especially 2.6 mm with Ti:C of 5:1. The proposed reaction mechanism gives a new guideline to achieve uniform electron conduction for lower

This special section of the IEEE Journal of Electron Devices Society is dedicated to select papers presented at the 2017 IEEE S3S Conference, which was held Oct. 16 – 19, 2017 in Burlingame, CA, USA. The papers were selected based on their technical merits and relevance to the Journal and with the feedback from the Technical Committee of the conference and session chairs.

Reliability of La-silicate gate dielectrics with tungsten carbide gate electrode have been investigated by Constant Voltage Stress (CVS) measurement. During constant voltage stress of the MOS capacitors, La-silicate MOS capacitors with tungsten carbide gate electrodes show better reliability due to the nice interface properties.

Demands for low-power CMOS devices are still increasing. Ultralow-voltage operation of CMOS with maximum power efficiency can extend the opportunity of using the electron devices to power-conscious applications such as ubiquitous sensor network, etc. The main issues for low-power (highly efficient) operation of the modern scaled CMOS are reducing variability and enabling adaptive control of circuit performance and power consumption under the operation at voltages as low as possible. In order to solve these issues, we are developing the silicon-on-thin-buried-oxide (SOTB) transistors. We show features of the SOTB, transistor technology dedicated for ultralow-voltage (down to 0.4 V) operation, circuit design applicable for SOTB and we discuss on the performance projection and ULV application with SOTB.

This study reports on the electrical characteristics of (1 1 0)-oriented nMOSFETs with a direct contact La-silicate/Si interface structure and the detailed comparison with (1 0 0)-oriented nMOSFETs. Precise control of oxygen partial pressure can provide the scaled EOT down to 0.73 nm on (1 1 0) orientation in common with (1 0 0) orientation. No frequency dispersion in Cgc–V characteristic for (1 1 0)-oriented nMOSFETs is successfully demonstrated at scaled EOT region, while higher amount of available bonds on (1 1 0) surface results in a larger interface state density, leading to the degradation of sub-threshold slope. High breakdown voltages of 2.85 V and 2.9 V for (1 0 0)- and (1 1 0)-oriented nMOSFETs are considered to be due to superior interfacial property. The electron mobility on (1 1 0) orientation is lower than that on (1 0 0) orientation because of the smaller energy split between fourfold valleys and twofold valleys as well as the larger density of states for lower-energy valleys in the (1 1 0) surface. Moreover, electron mobility is reduced with decreasing EOT in both (1 0 0)- and (1 1 0)-oriented nMOSFETs. It is found that threshold voltage instability by positive bias stress is mainly responsible for bulk trapping of electron even with a larger interface state density in (1 1 0) orientation and influence of surface orientation on threshold voltage instability is negligibly small.

Effect of W and TiN/W gate metal on the interface quality of La 2 O 3 /InGaAs metal–oxide-semiconductor (MOS) interface is investigated. Hard X-ray photoelectron spectroscopy revealed that gate metal greatly affects the oxidation states at La 2 O 3 /InGaAs interface after post-metallization annealing (PMA). Results demonstrate that TiN/W gate metal can effectively control the reaction at La 2 O 3 /InGaAs interface and also suppress the formation of As, Ga, and In oxides. As a result, superior capacitance–voltage (C–V) characteristics with low interface state density ( D it ) of 4.6 × 10 11 cm −2 /eV (∼0.1 eV from midgap) and leakage current below 10 −5 A/cm 2 was obtained for TiN/W/La 2 O 3 (10 nm)/InGaAs MOS capacitors. The MOS structure integrity was preserved for annealing temperature up to 620 °C.

InGaAs surface nitridation effect on La2O3/InGaAs interface has been investigated. It was found that by controlling nitridation conditions such as temperature interface quality can be improved. Also a new covalent structure based on nitridated Si and La2O3 is proposed to reduce dielectric and substrate intermixing, thus improving the high-k/InGaAs interface. High electron mobility of III-V material, in particular InGaAs, has made them a promising candidate to replace channel in Si-based metal-oxide-semiconductor field effect transistors (MOSFETs) [1]. In order to realize high performance III-V devices, the interface at high-k gate oxide and substrate surface must be improved [2]. Various interface control methods such as sulfur treatment and nitridation have been proposed in order to improve interface quality [3]. The most promising results have been reported on Al2O3-based capacitors which is a dielectric with covalent nature. However the low dielectric constant value of Al2O3 (k~9) makes it unsuitable for device scaling. In this study we have investigated the formation of a covalent interface by means of insertion and nitridation of a thin Si layer at La2O3/InGaAs interface. La2O3 (k~30) is recognized as a next-generation high-k material. A Si-doped n-In0.53Ga0.47As epiaxially grown on InP substrate was used. After oxide removal by HF, nitridation was performed by radical gun prior to La2O3 deposition for 5min. Amount of nitrogen dose was estimated at ~1.5x10 atoms/cm by SIMS. La2O3 layer was deposited by e-beam evaporation and W gate electrode was in situ deposited by RF magnetron sputtering. Post-metallization anneals (PMA) were carried out in forming gas (N2:H2= 97:3%) ambient. Fig. 1 shows capacitance-voltage (C-V) characteristic of W/La2O3/In0.53Ga0.47As annealed in F.G at 370 C with (a) and without (b) surface nitridation at 200 C. Low frequency capacitance response in negative gate bias is suppressed for nitridated sample which is an indicator of improved interface. Optimum surface passivation was obtained for nitridation at a substrate temperature of 200 C (fig. 2). Performing Nitridation after a thin Si layer insertion (fig. 3 (a)) further improved the C-V characteristics of the device, evident from smaller frequency dispersion in accumulation condition (fig. 3 (b)). In conclusion, nitridation was shown to be an effective interface passivation method. Forming a LaO-Si-N structure with covalent nature further improved C-V characteristics of the capacitors.

TiC films have been formed by stacking multiple thin Ti and C layers with subsequent annealing on diamond substrates. Thermally stable contact characteristics have been obtained with TiC electrodes, owing to the suppression of reaction between TiC and diamond. Workfunction of TiC film has been 4.3 eV. Contact resistivity of one order of magnitude lower than the Ti/n-diamond has been obtained.

This study focuses on studying the effective electron mobility in direct contact La-silicate/Si structure based nMOSFETs and searching for the difference of the mobility characteristics compared with the SiO 2 MOSFETs. In this study, three types of gate electrode structure were prepared to investigate the mobility characteristics over a wide EOT range; W for EOT of 1.63 nm, TiN/W for EOT of 1.02 nm and metal-inserted poly-Si (MIPS) for EOT of 0.71 nm. Since the silicate formation is basically caused by the presence of oxygen, Si layer in MIPS can suppress the oxygen in-diffusion from atmosphere, resulting in scaled EOT. It is found that the E eff dependence of mobility with La-silicate is observed to differ from the mobility of SiO 2 MOSFETs. The electron mobility with La-silicate shows the weaker E eff dependence than the mobility of SiO 2 nMOSFETs in middle and high E eff region. This suggests an existence of additional mobility component related to the direct contact La-silicate/Si structure. The effective electron mobility is degraded with decreasing EOT in entire E eff region. This means that the scattering sources including Coulomb scattering, phonon scattering and surface roughness scattering are located not at La-silicate/Si interface but the inside of gate stacks and approach the Si inversion channel. Coulomb scattering and phonon scattering are thought to be strengthened by increasing k -value because of the enhancement of Coulomb scattering potential and higher ionicity in La-silicate gate dielectrics. The influence of metal/high- k interface is also considered to affect on the mobility with decreasing the EOT.

A novel interpretation for conductance spectra obtained by conductance method of La2O3 gated MOS capacitors has been proposed. Two distinct peaks, one with broad spectrum ranging from 10 k to 200 kHz and the other near 1 kHz with a single time constant spectrum, have been observed at depletion condition. The former spectrum can be assigned as the interface traps (Dit) located at the interface between La-silicate and the Si substrate by statistical surface potential fluctuation model. On the other hand, as the latter slow trap signal shows strong influence with the thickness of La-silicate layer, it can be assigned as the trappings (Dslow) at the interface between La2O3 and La-silicate. Finally, the Dit and Dslow trends on annealing temperature are summarized.

We propose a novel resistive switching device with a W/CeO 2 /Si/TiN structure by incorporating a very thin Si buffer layer in the interface, the memory performance of this device such as forming voltage, operation power, and window and endurance characteristics were found to be remarkably improved compared with the performance of the device without the Si layer. This improvement was attributed to the formation of Ce-silicate and thus proper introduction of oxygen vacancies at the interface. The gradual reset process of the W/CeO 2 /Si/TiN device under sweeping voltage was quantitatively analyzed by parallel conductive filaments model. Our results provide a guideline for the operation voltage control for further optimizing device performance and give new insights into the gradual reset process.

Resistance changing of ion binding insulator hardly obtain large on and off resistance ratio. Resistance switching properties using Ni, W and Ti as a bottom electrode ware caused of changing resistance of Ce oxide. The influence of metal electrode on resistive switching behavior of CeOx film has been investigated. Resistance switching characteristics using NiSi2 electrode shows a large on and off window as large as 105. The main differences of the switching properties among the electrode materials are thought to be the reaction between the Ce oxide layer and electrodes. The set voltage dependence on the thickness of Ce oxide layers has indicated that the switching behavior is based on electric field.

The metal/InGaAs Schottky devices with Ni, TiN and stacked Ni/Si were fabricated. J-V and C-V characteristics were measured and Schottky barrier height was calculated.

Thickness dependence of La2O3 gate dielectrics on electrical characteristics for AlGaN/GaN MOSHFET has been investigated. Positive shift in threshold voltage has been observed with thicker La2O3 film thickness. Reduction in leakage current has obtained with thicker film.

Interface properties of La-silicate gate dielectrics with tungsten carbide gate electrode have been investigated. Utilizing multi-stacking of tungsten and carbon thin films, W2C has been realized with annealing at 750 oC for 20 minutes in N2 ambient. Improvements in interface properties have been observed with W2C gate electrode.