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In this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology computer-aided design-based statistical modeling. Compared with planar SOI high- $k$ metal gate CMOS technologies, 14-nm SOI FinFET technology shows better n-to-p tracking mainly due to the strong influence of correlated Fin geometrical variation, as well as reduced uncorrelated variation from an innovative work function process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/fast and fast/slow corners in certain conditions and, therefore should be considered in guard time design.

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

A highly optimized silicon-on-insulator FinFET technology is utilized for the IBM processor designs in the 14-nm node. This process technology has a number of unique elements that enable these prod...

In this paper we show that devices in scaled technologies could undergo self-heating (SH) even in the off-state when subjected to stress conditions that would in turn adversely impact product life-time. We present a detailed methodology in analyzing the impact of off-state SH, thus preventing unintentional overstressing during product stress-screening. We propose an analytical model for modeling this effect, verifying it against detailed TCAD simulations and actual hardware (HW) data from 14nm SOI FinFET technology. We show that the amount of off-state SH depends on the actual device size and the circuit layout. Additional temperature rise (deltaT) can increase ∼2.7x for 2-finger vs. 40-finger FETs. We demonstrate the SH impact on off-state hot-carrier-injection (HCI) induced degradation based on HW data. Finally, we analyze its impact on backend electromigration (EM) showing that median-time-to-fail (MTTF) can be reduced as much as 80% in large multi-finger (MF) FETs when off-state SH is taken into account.

Matched circuit components are widely used in logic circuits including resistors, capacitors and transistors. Any variations in those components could cause mismatch in circuit performance. In advanced technology nodes, double patterning (litho/etch/litho/etch) process has been introduced to pattern BEOL metal and via levels. Two patterning steps (litho/etch/litho/etch) with two sets of masks for litho printing and with two independent etch processes, could result in pattern dimension difference which leads to resistance and capacitance (RC) mismatch. In wire or via heavily dominated logic circuits, this RC mismatch may be sensitive to design-matched circuit components.

The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performance-enhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond

A 90-nm silicon-on-insulator (SOI) CMOS system on-chip integrates high-performance FETs with 243-GHz F/sub t/, 208-GHz F/sub max/, 1.45-mS//spl mu/m gm, and sub 1.1-dB NFmin up to 26 GHz. Inductor Q of 20, VNCAP of 1.8-fF//spl mu/m/sup 2/, varactor with a tuning range as high as 25:1, and a low-loss microstrip. Transmission lines were successfully integrated without extra masks and processing steps. SOI and its low parasitic junction capacitance enables this high level of performance and will expand the use of CMOS for millimeter-wave applications.

This paper presents five-stage and seven-stage traveling-wave amplifiers (TWA) in a 0.12-/spl mu/m SOI CMOS technology. The five-stage TWA has a 4-91-GHz bandpass frequency with a gain of 5 dB. The seven-stage TWA has a 5-86-GHz bandpass frequency with a gain of 9 dB. The seven-stage TWA has a measured 18-GHz noise figure, output 1-dB compression point, and output third-order intercept point of 5.5 dB, 10 dBm, and 15.5 dBm, respectively. The power consumption is 90 and 130 mW for the five-stage and seven-stage TWA, respectively, at a voltage power supply of 2.6 V. The chips occupy an area of less than 0.82 and 1 mm for the five-stage and seven-stage TWA, respectively.

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).

In this paper, a general design methodology of low-voltage wide-band voltage-controlled oscillator (VCO) suitable for wireless LAN (WLAN) application is described. The applications of high-quality passives for the resonator are introduced: 1) a single-loop horseshoe inductor with Q > 20 between 2 and 5 GHz for good phase noise performance; and 2) accumulation MOS (AMOS) varactors with C/sub max//C/sub min/ ratio of 6 to provide wide-band tuning capability at low-voltage supply. The adverse effect of AMOS varactors due to high sensitivity is examined. Amendment using bandswitching topology is suggested, and a phase noise improvement of 7 dB is measured to prove the concept. The measured VCO operates on a 1-V supply with a wide tuning range of 58.7% between 3.0 and 5.6 GHz when tuned between /spl plusmn/0.7 V. The phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz, with the nominal power dissipation between 2 and 3 mW across the whole tuning range. The best phase noise at 1-MHz offset is -124 dBc/Hz at the frequency of 3 GHz, a supply voltage of 1.4 V, and power dissipation of 8.4 mW. When the supply is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz. Using this design methodology, the feasibility of generating two local oscillator frequencies (2.4-GHz ISM and 5-GHz U-NII) for WLAN transceiver using a single VCO with only one monolithic inductor is demonstrated. The VCO is fabricated in a 0.13-/spl mu/m partially depleted silicon-on-insulator CMOS process.

In this paper, a 1-V 3.8 - 5.7-GHz wide-band voltage-controlled oscillator (VCO) in a 0.13-/spl mu/m silicon-on-insulator (SOI) CMOS process is presented. This VCO features differentially tuned accumulation MOS varactors that: 1) provide 40% frequency tuning when biased between 0 - 1 V and 2) diminish the adverse effect of high varactor sensitivity through rejection of common-mode noise. This paper shows that, for differential LC VCOs, all low-frequency noise such as flicker noise can be considered to be common-mode noise, and differentially tuned varactors can be used to suppress common-mode noise from being upconverted to the carrier frequency. The noise rejection mechanism is explained, and the technological advantages of SOI over bulk CMOS in this regard is discussed. At 1-MHz offset, the measured phase noise is -121.67 dBc/Hz at 3.8 GHz, and -111.67 dBc/Hz at 5.7 GHz. The power dissipation is between 2.3 - 2.7-mW, depending on the center frequency, and the buffered output power is -9 dBm. Due to the noise rejection, the VCO is able to operate at very low voltage and low power. At a supply voltage of 0.75 V, the VCO only dissipates 0.8 mW at 5.5 GHz.

A wide-band physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout. The 2-/spl Pi/ model accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. Using frequency-independent RLC elements, this new model is fully compatible with both ac and transient analysis. Verification with measurement data from a SiGe process demonstrates accurate performance prediction and excellent scalability for a wide range of inductor configurations.

Silicon-based devices, including the increasingly available SiGe-based devices, are now demonstrating fT and fMAX values over 200 GHz. These recent advances open the door to a wide range of silicon-based very high frequency, low power and highly integrated solutions. Trends in silicon MOS, SiGe HBT, SiGe MODFET and SiGe strained silicon FETs are reported. Silicon inroads to device functions viewed as the sole realm of III-V technologies are also being demonstrated. Capability and trends of the integrated silicon photodiode are reported here as an example. Integration of these high-speed devices into a complex circuit requires on-chip passive device functionality at such high frequency. Key devices to enable integration are the inductor, varactor, and transmission line, and operation of these devices at high frequency is reported. Further, we discuss noise isolation issues and techniques, which may be used when minimizing cross-talk within a conductive silicon substrate.

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading ‘scale-out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.

We report a strong direct correlation (above 0.9) between conventional transistor-level parametrics typically used in the industry to monitor and control intra-die variability (IDV) and a novel, non-contact performance-based metrology (PBM), technology that was integrated into an active die on a 32nm SOI advanced logic product platform. We demonstrate a PBM test structure measurement repeatability of less than 0.4%. In this work, we also demonstrate the compatibility of integrating the PBM technology into an advanced CMOS process flow with no added processing or steps, as well as its footprint scalability. The data suggests that the non-contact PBM technology meets all prerequisites for its deployment as a standard, within-product IDV monitor.

We report a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance. We propose a metric to capture impact of ACV on chip-level leakage quantitatively. Product power-performance can be optimized by minimizing systematic ACV. Thermally-driven ACV was identified as a major mechanism in 32nm SOI technology. An optimized thermal anneal process was used to suppress ACV significantly, leading to a dramatic benefit in leakage power-performance trade-off.

Over the past three technology generations we have made systematic observations on device-design strategies leading to optimal circuit-limited yield. These strategies now impose additional considerations that need to be directly coupled into the technology-development paradigm. At the core of the present discussion is the balance between traditional FET (Field Effect Transistor) and small-circuit optimization and the concurrent impact seen at product level. Certain device-design tradeoffs need to be understood in order to maximize performance for a diverse range of products.

It is known that significant intra-die thermal absorption variation is caused by non-optimized rapid thermal anneal (RTA) conditions and the variation depends on the local pattern density of various types of exposed stacks of the wafer. This variation can create errors in the electrical measurement MOSFET gate length itself. Two electrical methods for measuring gate length will be discussed, namely, the resistive technique, where a long-wide poly-silicon resistor is used as a normalizing resistor; and the capacitive technique, where a long-wide plate gate capacitor is used as a normalizing capacitor. It is shown, that the capacitive technique is more immune to errors introduced by RTA driven intra-die thermal absorption variation. Methods of minimizing these measurement errors are briefly discussed.

New effective drive current IEFF + methodologies are demonstrated in this paper to address predictability of circuit performance across wide Vt range and accuracy of effective resistance REFF prediction-to-hardware correlation. Two separate IEFF definitions are adopted for delay performance prediction (IEFF = [IH + IL]/2), and ring AC/DC prediction-tohardware correlation analysis (IEFF + = [1.15IH + IL + GDS,LIN* VDD/80]/2). IEFF + results in perfect matching in ring AC and DC effective resistance across SOI and bulk technologies. IEFF combined with Vt-dependent effective switching capacitance (CEFF_Delay) also leads to good match between predicted performance and spice simulation across wide Vt range using simple CMOS device parameters.

We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fT's are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.

We present record-performance RF devices and circuits for an SOI CMOS technology, at 35 nm Lpoly. Critical RF/analog figure of merits in FET such as current gain cut-off frequency (fT), 1/f noise, and high-frequency noise figure at various bias and temperature conditions are measured and modeled to enable high-performance circuit design. Measurement results show peak fT's of 340 GHz and 240 GHz for 35 nm Lpoly NFET and PFET, respectively. At sub-35 nm Lpoly, 360 GHz fT NFET and 260 GHz fT PFET are demonstrated. High-Q, high-density vertical native capacitors (VNCAPs) and on-chip inductors are integrated. RF-operable ring oscillator (RFRO) demonstrates a 3.58 psec delay and a SSB phase noise of -107 dBc/Hz at 1 MHz offset. LC-tank VCO operates at 70 GHz with 9.5% tuning range. The maximum operating frequency of a static CML divider is 93 GHz while dissipating 52.4 mW.

Recently, 65 nm technology-based microprocessors have been introduced into high-end products such as games processors and high- performance servers [1]. As technology development in the modern-day relies more and more on non-traditional performance- leverage elements, there is an enhanced need to tighten the coupling between development, modeling, and design. We discuss the key challenges in the inter-related tasks of CMOS-technology development, early product engineering, and transition to full-volume manufacturing. In order to meet timely introduction to market, several key objectives must be pursued in a parallel fashion and must adhere to stringent timelines. The essence of this is the simultaneous development of (1) 65 nm process-technology (including continual process development geared towards minimization of variability) (2) highly accurate compact models and (3) product- design.

We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in VT and REXT accounts for most of the IDV in delay and leakage and is modulated by lamp RTA ramp rate. We show a good correlation of inverter delay to mm-scale variation in the predicted reflectivity of the device pattern densities

A differentially tuned VCO is fully integrated in a standard microprocessor 0.12 /spl mu/m SOI CMOS. A phase noise of -101.8dBc/Hz at 1MHz offset is measured with 7.5mW at 1.5V. The VCO tuning range is 9.8% from 40GHz to 44GHz. The output power is up to -6dBm after a single-stage buffer amplifier with 6mW at 1.5V.

This paper presents the design and manufacturability of SOI RF integrated circuits, from an SOI technology understanding, to the integration of high-performance passive devices for a wireless system-on-chip (SoC) application. In the technology section, we show the ability of SOI NMOS transistors to function as high-bandwidth amplifiers. A 9-stage distributed amplifier exhibited a gain of 11 dB with a 90 GHz 3 dB cut-off frequency. We also present four features of an aggressively scaled 120 nm partially-depleted SOI CMOS technology that shows its suitability for HF circuit applications. In the integrated-passive section, high-Q inductors and high value capacitors are both presented. In the RF circuit design section, four 5 GHz LC-tank VCOs are detailed Finally, a 2:1 static frequency divider, exhibiting a maximum operating frequency of 33 GHz, is described.

This paper presents a three-stage CML (current mode logic) ring VCO fabricated in a 0.12 /spl mu/m SOI CMOS technology with a minimum stage delay of 5.4 ps at a differential voltage swing of 400 mV. The maximum oscillation frequency measured is 31 GHz. A tuning range as high as 10% is measured. The phase noise is -95.6 dBc at an offset frequency of 10 MHz. The energy per stage is as low as 26.8 fJ at a power supply voltage of 1.5V and a delay per stage of 5.95 ps.

This paper presents the design optimization and experimental results of 40-50 GHz VCOs for embedded RF integrated circuits that are widely tunable and therefore highly manufacturable. We achieved up to 15% frequency tuning range from 43.5 to 50.5 GHz and -90.2 dBc/Hz phase noise performance at 1 MHz offset from 50.1 GHz operating frequency. The total power dissipation is 15 mW at 1.8 V. The VCOs are fabricated in a 120 nm SOI technology.

This paper presents high-Q and high-density 3-dimensional VPP (vertical parallel plate) capacitors fabricated in a 0.12 /spl mu/m SOI CMOS technology. An effective capacitance density of 1.76 fF//spl mu/m/sup 2/ is obtained. A quality-factor of 22 at 1 GHz is obtained for a 20 pF VPP capacitor. Also, a VPP capacitor model is proposed for the first time to design the VPP capacitor.

SOI CMOS technology offers low parasitic junction capacitance, and therefore provides speed and power enhancements to digital applications compared to bulk CMOS. It is also emerging as a good candidate for high-performance SoC, with integratable RF circuits that operate beyond 30-GHz already demonstrated at the 130-nm technology node. The digital aspects of the base 90-nm SOI technology were previously reported. This paper presents the RF performance of this technology, and shows that the capabilities of CMOS technology are expanding into the millimeter-wave regime.

This paper describes the design and technology optimization of power-efficient monolithic VCOs with wide tuning range. Four 5-GHz LC-tank VCOs were fabricated in a 0.12-/spl mu/m SOI CMOS technology that was not enhanced for RF applications. High and regular resistivity substrates were used, as were single-layer and multiple-layer copper inductors. Using a new figure-of-merit (FOM/sub T/) that encompasses power dissipation, phase noise and tuning range, our best VCO has an FOM/sub T/ of -189 dBc/Hz. The measured frequency tuning range is 22 % and the phase noise is 126 dBc/Hz at 1 MHz offset for 4.5-GHz. Oscillation was achieved at 5.4-GHz at a minimum power consumption of 500 /spl mu/W.

A 2:1 static frequency divider was fabricated in a 0.12-/spl mu/m SOI CMOS technology. The divider exhibits a maximum operating frequency of 33 GHz. When the power consumption is scaled down to 2.7 mW, a maximum operating frequency of 25 GHz is measured.

A solenoid layout technique is used to increase the magnetic coupling between the coils in multi-level spiral transformers. Using this technique, transformers with the following performance are measured: (a) magnetic coupling with coupling factor k>0.95 and insertion loss s/sub 21/ better than 0.8 dB at 5 GHz; (b) self-resonant frequency f/sub res/>15 GHz with peak Q>10. The effect of high and low resistive substrates is discussed with measured results. Using this structure, the size of the transformer can be reduced from 50 to 400%.

This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 /spl mu/m SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH//spl mu/m/sup 2/ is obtained for a 42 nH MTS (Multi-turn, multiple metal layers in Series) inductor.

A 1 V 3.8-5.7 GHz VCO was designed and fabricated in a 0.13 /spl mu/m SOI CMOS process. This VCO features differentially-tuned accumulation MOS varactors that (a) provides 40% frequency tuning when biased between 0 to 1 V, and (b) rejects common-mode noise such as flicker noise. At 1 MHz offset, the phase noise is -121.67 dBc/Hz at 3.8 GHz, and -111.67 dBc/Hz at 5.7 GHz. The power dissipation is between 2.3 to 2.7 mW depending on the centre frequency. When V/sub DD/ is reduced to 0.75 V, the VCO only dissipates 0.8 mW at 5.5 GHz.

A low-voltage 3.0-5.6 GHz VCO was designed and fabricated in an 0.13 /spl mu/m SOI CMOS process. This VCO features a single-loop horseshoe-shaped inductor and an array of band-switching accumulation MOS (AMOS) varactors. This results in good phase noise and a wide tuning range of 58.7% when tuned between 0 to 1.4 V. At a 1 V Supply (V/sub DD/) and 1 MHz offset, the phase noise is -120 dBc/Hz at 3.0 GHz, and -114.5 dBc/Hz at 5.6 GHz. The power dissipation is between 2 and 3 mW across the whole tuning range. The buffered output power is -7 dBm. When VDD is reduced to 0.83 V, the VCO dissipates less than 1 mW at 5.6 GHz.

A 40 GHz fully-monolithic complementary VCO fabricated in IBM 0.13 /spl mu/m partially-depleted SOI CMOS technology is reported. The VCO operates at 1.5 V supply and draws 11.25 mW of power. The measured phase noise at 40 GHz is -109 dBc/Hz at 4 MHz offset from the carrier. At 1.5 V and 2 V V/sub DD/, the tuning range is 9% and 15% respectively, and the output power is -8 dBm and -5 dBm respectively. The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m.