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Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing. [ABSTRACT FROM AUTHOR]

Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architectures are used extensively to accelerate inferencing/training with convolutional neural networks (CNNs). Three-dimensional (3D) integration is an enabling technology to integrate many PIM cores on a single chip. In this work, we propose the design of a thermally efficient dataflow-aware monolithic 3D (M3D) NoC architecture referred to as TEFLON to accelerate CNN inferencing without creating any thermal bottlenecks. TEFLON reduces the Energy-Delay-Product (EDP) by 42%, 46%, and 45% on an average compared to a conventional 3D mesh NoC for systems with 36-, 64-, and 100-PIM cores, respectively. TEFLON reduces the peak chip temperature by 25K and improves the inference accuracy by up to 11% compared to sole performance-optimized SFC-based counterpart for inferencing with diverse deep CNN models using CIFAR-10/100 datasets on a 3D system with 100-PIM cores. [ABSTRACT FROM AUTHOR]

The streaming multiprocessor (SM) count in GPUs continues to increase to provide high computing power. To construct a scalable crossbar network that connects the SMs to the LLC slices and memory controllers, a cluster structure is exploited in GPUs where a group of SMs shares a network port. Unfortunately, current GPU spatial multitasking is unaware of this underlying network-on-chip infrastructure which poses the challenges and also the opportunities for the performance. In this paper, we observe that compared to the cluster-unaware multitasking, considering the cluster structure, the SM partition within a cluster and also the injecting policy of sharing the network port can bring significant performance improvement. Next, we propose a low-cost online profiling and scheduling policy that consists of two steps. The cluster-aware scheduling first determines the best SM partition within a cluster and then finds the proper injecting policy between the two co-executing applications. Both steps are achieved in online profiling which only incurs limited runtime overhead. The evaluation results show that for all workloads, our cluster-aware multitasking increases the system throughput by 12.9% on average (and up to 76.5%). [ABSTRACT FROM AUTHOR]

Organizations managing high-performance computing systems face a multitude of challenges, including overarching concerns such as overall energy consumption, microprocessor clock frequency limitations, and the escalating costs associated with chip production. Evidently, processor speeds have plateaued over the last decade, persisting within the range of 2 GHz to 5 GHz. Scholars assert that brain-inspired computing holds substantial promise for mitigating these challenges. The spiking neural network (SNN) particularly stands out for its commendable power efficiency when juxtaposed with conventional design paradigms. Nevertheless, our scrutiny has brought to light several pivotal challenges impeding the seamless implementation of large-scale neural networks (NNs) on silicon. These challenges encompass the absence of automated tools, the need for multifaceted domain expertise, and the inadequacy of existing algorithms to efficiently partition and place extensive SNN computations onto hardware infrastructure. In this paper, we posit the development of an automated tool flow capable of transmuting any NN into an SNN. This undertaking involves the creation of a novel graph-partitioning algorithm designed to strategically place SNNs on a network-on-chip (NoC), thereby paving the way for future energy-efficient and high-performance computing paradigms. The presented methodology showcases its effectiveness by successfully transforming ANN architectures into SNNs with a marginal average error penalty of merely 2.65%. The proposed graph-partitioning algorithm enables a 14.22% decrease in inter-synaptic communication and an 87.58% reduction in intra-synaptic communication, on average, underscoring the effectiveness of the proposed algorithm in optimizing NN communication pathways. Compared to a baseline graph-partitioning algorithm, the proposed approach exhibits an average decrease of 79.74% in latency and a 14.67% reduction in energy consumption. Using existing NoC tools, the energy-latency product of SNN architectures is, on average, 82.71% lower than that of the baseline architectures. [ABSTRACT FROM AUTHOR]

Rajnish Nagarkar,1 Mamillapalli Gopichand,2 Suparna Kanti Pal,3 Ankur Gupta,4,5 Najmuddin Mohd Saquib,4,5 Ganga Sagar,4 Kanury VS Rao,4,5 Zaved Siddiqui,4,5 Imliwati Longkumer6 1Surgical Oncology, HCG Manavta Cancer Centre, Nashik, Maharashtra, India; 2Surgical Oncology, HealthCare Global Enterprises Limited, Vijayawada, India; 3Radiotherapy, Indoriv Clinical, Kolkata, India; 4Research and Development Section, PredOmix Technologies Private Limited, Gurugram, India; 5Research and Development Section, PredOmix Health Sciences Private Limited, Singapore; 6Biochemistry, North East Cancer Hospital and Research Institute, Guwahati, Assam, IndiaCorrespondence: Imliwati Longkumer; Zaved Siddiqui, Email ilongkumer@yahoo.co.in; zaved@predomix.comAbstract: We evaluated the potential relevance of our multi-cancer detection test, OncoVeryx-F, for ovarian cancer screening. For this, we compared its accuracy with that of CA125-based screening. We demonstrate here that, in contrast to CA125-based detection, OncoVeryx-F detected ovarian cancer with very high sensitivity and specificity. Importantly here, Stage I cancers too could be detected with an accuracy of > 98%. Furthermore, again unlike CA 125, the detection accuracy of OncoVeryx-F remained comparable in both Caucasian and South Asian/Indian women. Thus, the robustness and accuracy of OncoVeryx-F, particularly for early-stage detection, underscores its potential utility for ovarian cancer screening.Keywords: CA 125, Oncoveryx-F, OvC, NoC, LC-MS/MS

Voltage stacking is a technique in which multiple integrated circuits are stacked in series between the supply voltage instead of in parallel, thus improving the energy efficiency of the power distribution network. Unfortunately, voltage stacking presents stability challenges for integrated circuits within the stack. A first-order model to quantify variability, stability, and power metrics for an array of voltage-stacked asynchronous integrated circuits is presented. Voltage variability and power consumption are accounted for and discussed. Limitations of the model are identified outside of the nominal behavior. The number of columns in the architecture, chip leakage, and supply voltage are shown to be the key contributors to the stability, performance, and energy efficiency of a system of voltage-stacked asynchronous processors. A higher leakage to active power ratio, though usually avoided by chip designers, is shown to improve stability and be key in designing stacks without external balancing. Outputs of the model enable system and chip designers to evaluate first-order trade-offs in energy efficiency, performance, and system cost. These fundamental data allow designers to make informed design and optimization trade-offs between asynchronous voltage-stacked architectures and the integrated circuits used therein. Analysis of this model shows that various voltage-stacked configurations, such as one with a 48 V supply using 100 rows and 11 columns, can be designed with less than 10% voltage variation per chip, mitigating the need for external voltage balancing.

Applications running in a large and complex manycore system can significantly benefit from adopting the dataflow model of computation. In a dataflow execution environment, a thread can run only if all its required inputs are available. While the potential benefits are large, it is not trivial to improve resource utilization and energy efficiency by focusing on dataflow thread execution models (i.e., the ways specifying how the threads adhering to a dataflow model of computation execute on a given compute/communication architecture). This paper proposes and implements a hardware-software co-design-based dataflow threads management framework. It works at the Network-on-Chip (NoC) level and consists of three stages. The first stage focuses on a fast and effective thread distribution policy. The next stage proposes an approach that adds reconfigurability to a 2D mesh NoC via customized instructions to manage the dataflow thread distribution. Finally, a 2D mesh and ring-based hybrid NoC is proposed for better scalability and higher performance. This work can be considered a primary reference framework from which extensions can be carried out. [ABSTRACT FROM AUTHOR]

Providing 80% of healthcare worldwide, nurses focus on physiologic and psychosocial aspects of health, which incorporate social determinants of health (SDOH). Recognizing their important role in SDOH, nurse informatics scholars included standardized measurable terms that identify and treat issues with SDOH in their classification systems, which have been readily available for over 5 decades. In this Perspective, we assert these currently underutilized nursing classifications would add value to health outcomes and healthcare, and to the goal of decreasing disparities. To illustrate this, we mapped 3 rigorously developed and linked classifications: NANDA International (NANDA-I), Nursing Interventions Classification (NIC), and Nursing Outcomes Classification (NOC) called NNN (NANDA-I, NIC, NOC), to 5 Healthy People 2030 SDOH domains/objectives, revealing the comprehensiveness, usefulness, and value of these classifications. We found that all domains/objectives were addressed and NNN terms often mapped to multiple domains/objectives. Since SDOH, corresponding interventions and measurable outcomes are easily found in standardized nursing classifications (SNCs), more incorporation of SNCs into electronic health records should be occurring, and projects addressing SDOHs should integrate SNCs like NNN into their ongoing work. [ABSTRACT FROM AUTHOR]

Purpose: This research aims to focus on the strategic management by National Olympic Committees (NOCs) during the COVID-19 crisis. The authors investigate "How are strategies being developed within European NOCs to tackle the impact of the corona crisis?" and "which measures have proven to be particularly helpful?" Design/methodology/approach: The research uses a sequential exploratory mixed-methods approach. Five high-level representatives of European NOCs were interviewed using expert interviews to gain insights into their strategy development process. The interviews were analyzed using qualitative content analysis, and a questionnaire was developed based on the results. Nineteen other European NOCs were surveyed using this questionnaire to verify the strategy development process steps on a larger sample. Findings: The research resulted in a six-step NOC strategy development process framework, with helpful measures for each step. It can help the organizations to better cope with current or upcoming crises. Originality/value: This framework can serve as a guide for NOCs to find the right steps and measures to better perform in crisis situations. [ABSTRACT FROM AUTHOR]

Network-on-Chip (NoC) initiates the design procedure of interconnection network into SoC - System-on-Chip. The current technique overcomes the drawbacks of traditional bus-based SoC, for instance, poor scalability, small-link bandwidth, and large delay. The network-on-Chip systems required minimum buffering space and low-latency requirements. Here, the FIFO buffer is utilized as a virtual channel to evade deadlock issues and thus enhances throughput. The current research focused on an enhanced toward improving Embedding-Memory-management- Units performance into Network-on-Chip. Here, the 3D NoC was considered in the study for Noc improvement and has achieved high performance. Further, A first-in-first-out (FIFO) buffer was used in NoC routers to store the data packets temporarily. Eventually, the RAM -random access memory was proposed that serves as a link between the crossbar switch and the input ports. The simulation result of the current research results in only 0 to 16 memory for data storage in a stack out of 64, with the almost empty signal being high.

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In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to <8% in multi/many-core systems. [ABSTRACT FROM AUTHOR]

Multi-threaded design of the applications has given a new dimension to the execution concurrency. The Network-on-Chip (NoC) infrastructure has evolved as the communication backbone in multiprocessor System-on-Chips (MPSoCs) to exploit Thread-Level Parallelism (TLP). Mapping the threads of various applications on the processing cores is crucial in utilizing the resources of a many-core system. An application's performance depends primarily on the mapping strategy. However, the performance of an application gets influenced significantly by the underlying network architecture of the NoC. The present work proposes a run-time application mapping technique based on the Cube-Tree-Hybrid (CTH) topology focusing on the traffic load balancing across the network. The mapping overhead decreased significantly by exploiting the low network diameter of CTH with its high scalability and path diversity, projecting a 31% reduction in normalized execution time over the prevalent algorithms on the existing mapping platforms. Rigorous experimentation with varying application and network sizes is carried out across mesh, ZMesh, torus, and Mest-of-Tree (MoT) networks. The experimental observations project that the proposed algorithm results in sustainable application performance with 15%-21% gain in the overall energy consumption over the existing state-of-the-art techniques across various benchmark workloads. [ABSTRACT FROM AUTHOR]

A new technology is much more required in this fast-growing communication world due to inability to bear the segments by the conventional wiring-based transmitting strategies and the coordinated dimensions of System on Chip (SoC). The new technology could manage the increasing enduring failures due to diminishing technology parameters. To solve the above problem, an advanced technical paradigm Network-on-Chip (NoC) was created to keep pace with the correspondence requests on this high demanding network frame. In this paper, we have dealt with Fault Tolerance Topology Design (FTTD) along with Corvus Seek Algorithm (CoSA) and Look Advanced Propinquity Enlightened Routing (LA-PER) that can tolerate the single continuous failures in joiners of NoC for specific applications. The proposed work generates fault-tolerant topology with two substitute paths between the transmitting Processing Elements (PEs) using proposed Routing Element architecture for the applications. The FTTD carefully selects the shortest substitute path with CoSA and LA-PER that led to energy reduction and minimal latency utilization. The aim of the method is to optimize the communication with less energy utilization and latency, tested with different multimedia applications against different topologies. The proposed method's outcomes exhibited the reduction in energy and latency an extent of 19.15% and 35.29%. • The proposed work generates fault-tolerant topology with two substitute paths between the transmitting Processing Elements (PEs) using proposed Routing Element architecture for the applications. • The Routing Element(RE) architecture using Look advanced Propinquity Enlightened Routing (LA-PER) for shortest path generation. • The proposed design of Fault Tolerance topology for ASNoC uses Corvus seek algorithm (CoSA) that is based on crow search algorithm. • The proposed algorithms run in Vivado 15.1 HLS and implemented in Zynq7000 series xc7z020clg484-1chip. [ABSTRACT FROM AUTHOR]

This paper introduces a novel 3D NoC router that combines buffered and bufferless routing with approximate priority comparison when deflecting flits. Our proposal is a modification of an asymmetrical router that is buffered in the z dimension ports and bufferless in the x and y dimension ports. Flits that request output ports in the x and y dimensions are granted or deflected based on approximate, instead of accurate, priority comparison. Experimental results show that the proposed router, in addition to effectively combining the advantages of both buffered and bufferless routers, achieves additional performance and area gains due to the reduced logic required for approximate priority comparison in flit deflections. Experimental results using synthetic and realistic traffic show that the proposed router begins to saturate at a significantly higher injection rate than a bufferless router, but at a slightly lower injection rate than when using accurate priority comparison. Furthermore, the proposed router achieves higher clock frequencies and a reduced area compared to bufferles routers due to the simpler permutation network. The increased routing efficiency is shown to also translate to energy gains. [ABSTRACT FROM AUTHOR]

This paper summarizes recent research on network-on-multi-chip (NoMC) at Poznań University of Technology. The proposed network architecture supports hierarchical addressing and multicast transition mode. Such an approach provides new debugging functionality hardly attainable in classical hardware testing methodology. A multicast transmission also enables real-time packet monitoring. The introduced features of NoC network allow to elaborate a model of hardware video codec that utilizes distributed processing on many FPGAs. Final performance of the designed network was assessed using a model of AVC coder and multi-FPGA platforms. In such a system, the introduced multicast transmission mode yields overall gain of bandwidth up to 30%. Moreover, synthesis results show that the basic network components designed in Verilog language are suitable and easily synthesizable for FPGA devices.

Background and Objectives: Wireless Network on Chip (WNoC) is one of the promising interconnection architectures for future many-core processors. Besides the architectures and topologies of these WNoCs, designing an efficient routing algorithm that uses the provided frequency band to achieve better network latency is one of the challenges.Methods: Using wireless connections reduces the number of hops for sending data in a network, which can lead to lower latency for data delivery and higher throughput in WNoCs. On the other hand, since using wireless links reduces the number of hops for data transfer; this can result in congestion around the wireless nodes. The congestion may result in more delay in data transfer which reduces the network throughput of WNoCs. Although there are some good routing algorithms that balance traffic using wired and wireless connections for synthetic traffic patterns, they cannot deal with dynamic traffic patterns that existed in real-world applications. In this paper, we propose a new routing algorithm that uses the wireless connections as much as possible, and in the case of congestion, it uses the wired connection instead.Results: We investigated the proposed method using eight applications from the Parsec benchmark suite. Simulation results show that the proposed method can achieve up to 13.9% higher network throughput with a power consumption reduction up to 1.4%.Conclusion: In this paper, we proposed an adaptive routing algorithm that uses wireless links to deliver data over the network on chip. We investigated the proposed method on real-work applications. Simulation results show that the proposed method can achieve higher network throughput and lower power consumption.

Network on chip (NoC) is an integrated communication system on chip (SoC), efficiently connecting various intellectual property (IP) modules on a single die. NoC has been suggested as an enormously scalable solution to overcome the communication problems in SoC. The performance of NoC depends on several aspects in terms of area, latency, throughput, and power. In this paper, the 2D and 3D mesh NoC performance on Virtex-5 field-programmable gate array (FPGA) is studied. The design is carried in Xilinx ISE 14.7 and the behavior model is followed based on XY and XYZ routing for 2D and 3D mesh NoC respectively. The functional simulation is performed on Modelsim 10.0 software. The on-chip communicationis verified for 2D and 3D mesh NoC with different cluster sizes that pre-estimates the hardware resources utilization on FPGA. The algorithm provides a substantial platform to NoC designers to overcome the issues of substantial configuration in NoC synthesis on FPGA in case of multiple processing elements, routers, cache controllers are integrated with SoC. The suggested NoC is helpful for the embedded system design of smart wireless communication. [ABSTRACT FROM AUTHOR]

Abstract The Code‐division multiple access (CDMA) method is commonly used as the network infrastructure in multi‐core chips. One of its advantages is the simultaneous connection of all network components. Another advantage is the constant delay of this method. On the other hand, one drawback is that the number of transmitters is limited to the number of encoding bits. In this study, the authors used the combination of Walsh codes and their inverses, as well as the simultaneous application of the time‐division multiple access (TDMA) method, to increase the transmission capacity of this protocol more than four times the standard mode. In the proposed design, although the circuit area does not increase significantly, a fourfold increase in the throughput of the CDMA network is seen. Using the method proposed in this study, it will be possible to increase the capacity further.

In modern computing, which relies on the interconnection of networks used in many/multi-core systems, any system can be critically subverted if the interconnection is compromised. This can be done in a multitude of ways, but the threat of a hardware Trojan (HT) being injected into a system is particularly prevalent due to the increase in third-party manufacturers for system-on-chip (SoC) designs. With a local injection of an HT in an SoC, an adversary can gain access to information about applications running on the system by revealing specific communications of the SoC, and the network-on-chip (NoC) as a whole. This heavily compromises the system and gives information to the attacker, which can lead to more tailored, compromising attacks. In this paper, we demonstrate an HT that exploits communication patterns inside an SoC to reveal applications that are running on an NoC with multi/many-core processors. This is performed by leaking packet counts, after which the attacker then uses machine learning techniques to identify applications running on processors, and the SoC as a whole. We also propose a LUT-based obfuscation technique to limit the information available to the hardware Trojan. Our results indicate that this obfuscation method can reduce the accuracy of this attack from 99% to