Search

A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 μm2 cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cell signal distribution in low voltage scaled FeRAMs are discussed. Next, the shield-bitline-overdrive technique is presented. This technique applies a 0.24 V higher bias to the ferroelectric capacitor through bitline-to-bitline coupling during the read operation without increasing device stress, and eliminates bitline-to-bitline coupling noise. The measured tail-to-tail cell signal is improved by 100 mV and effectively doubles for 1.3 V array operation. The area penalty of the proposed scheme is 0.9% of the 576 Kb cell array, and the access time penalty is 5 ns. The effect of this technique will be enhanced by cell shrink as the bitline-to-bitline coupling ratio increases. A tail-to-tail cell signal window of more than 200 mV is expected in 1.3 V 256 Mb and 1.2 V 512 Mb chain FeRAMs, whereas the tail-to-tail cell signal window without overdrive would degrade to 95 mV for 256 Mb and 60 mV for 512 Mb.

A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated bitlines, resulting in the reduction of die size by 6.5% and cell array power consumption by 28%. Fast read/write of 60-ns cycle time as well as reliability improvement are realized by two high-speed error checking and correcting (ECC) techniques: 1) fast pre-parity calculation ECC sequence and 2) all-“0”-write-before-data-write scheme. Moreover, among nonvolatile memories reported so far, the 64 Mb chain FeRAM has achieved the highest read/write bandwidth of 200 MB/s with ECC. The chip size is 87.5 mm2 with average cell size of 0.7191 μm2.

The cell-to-cell leakage caused by bipolar disturb of the floating-body cell (FBC) has been investigated. In the case of FBC without silicide at the source and drain regions, the change of data “0” to data “1” has been observed in the writing operation to the adjacent cell. However, this leakage can be reduced when the silicide is formed on the thin silicon film at the source and drain regions. It has been clarified that the diffusion of holes inside the n+ region is restricted by the capture of holes at the silicide/silicon interface when silicon thickness reduces. Based on these experimental results, 6F2 layout of FBC can be realized with the conventional logic device process platform.

An 87.7 mm2 1.6 GB/s 128 Mb chain FeRAM with 130 nm 4-metal CMOS process is demonstrated. In addition to small bitline capacitance inherent to chain FeRAM architecture, three new FeRAM scaling techniques - octal bitline architecture, small parasitic capacitance sensing scheme, and dual metal plateline scheme - reduce bitline capacitance from 100 fF to 60 fF. As a result, a cell signal of ±220 mV is achieved even with the small cell size of 0.252 ?m2. An 800 Mb/s/pin read/write bandwidth at 400 MHz clock is realized by installing SDRAM compatible DDR2 interface, and performance is verified by simulation. The internal power-line bounce noise due to 400 MHz clock operation is suppressed to less than 50 mV by an event-driven current driver, which supplies several hundreds of mA of current within 2 ns response. The precise timing and voltage controls are achieved by using the data stored in a compact FeRAM-fuse, which consists of extra FeRAM memory cells placed in edge of normal array instead of conventional laser fuse links. This configuration minimizes area penalty to 0.2% without cell signal degradation.

Physics of autonomous refresh is presented, which explains the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC). Input current to the floating body and output current from the body balance to generate an unstable stationary state that is accompanied by two stable stationary ones. The current anomaly of impact ionization is essential for the instability that brings about the bistability and is realized by positive feedback where impact ionization current input increases as the body voltage increases. Experiments with charge pumping current as output show that the autonomous refresh is possible on a single-cell basis. Necessary conditions for a high-density memory to be autonomously refreshed are derived and assessed for state-of-the-art FBCs. FBC is shown in simulation to become an SRAM cell when the autonomous refresh is applied, which uses gate direct tunneling current as output. This is an SRAM cell that is theoretically expected to have the simplest structure ever reported.

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage

A damage-robust SrRuO 3 /IrO 2 top electrode FeRAM with Cu BEOL process is demonstrated for the first time as a promising device for 130 nm CMOS embedded non-volatile memory. The ferroelectric capacitor with SrRuO 3 /IrO 2 top electrode has no degradation during Cu metallization to suppress oxygen and lead vacancies at a top electrode interface. Switching charge ( Q sw ) of 40 μC/cm 2 is achieved for 0.45 × 0.45 μm 2 top electrode (TE) size capacitor. Ninety percent saturation of Q sw is obtained at 1.1 V that is low enough to drive ferroelectric capacitors at 1.8 V for 130 nm CMOS. Opposite state polarization margin more than 90% is retained against imprint after the high temperature storage at 150 °C for 70 h. The combination of this high reliable capacitor with large Q sw and Chain FeRAM™ architecture with a small bit line capacitance [Ozaki T, Iba J, Yamada Y, Kanaya H, Morimoto T, Hidaka O, et al. In: Symposium on VLSI technologies technical digest; 2001. p. 113] drastically increases signal window for 1T1 C operation. A sharp signal distribution and a large peak-to-peak signal window of 730 mV at 1.8 V on the test device with 0.20 μm 2 area capacitors using three-level Cu metallization on 32 Mb Chain FeRAM™ are obtained. This technology realizes reliable embedded FeRAM of 130 nm generation and beyond.

A one-transistor memory cell on silicon-on-insulator, called floating-body cell (FBC), has been developed and demonstrated. Threshold voltage difference between the "0"-state and the "1"-state, which is a key parameter for realizing a large-scale memory by FBCs, is measured and analyzed using a 96 kb array diagnostic monitor (ADM). A function test of the ADM yielded a fail-bit probability of 0.002%. A new metric relating to the fail-bit probability, that is, the ratio of the threshold voltage difference over the total threshold voltage variation, is introduced and applied to the measurement results. Read current distributions are also evaluated for various operation voltages. This paper also investigates substrate bias dependence of the threshold voltage unique to fully-depleted devices. Channel impurity and substrate impurity concentration dependence of the threshold voltage are analyzed based on experimental data and device simulation.

We proposed Bit Cost Scalable (BiCS) technology in 2007 as a three-dimensional memory for the future ultra high density storage devices, which extremely reduce the bit costs by vertically stacking memory arrays with punch and plug process. We've applied it to just NAND flash, which is BiCS Flash memory, and established the mass production technology. Moreover, we can apply the BiCS technology to various memories. The critical issues and the comparison among various 3D NAND Flash-type memories are to be discussed, as well.

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGT's) For ultra high density DRAM's. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGT's connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >

We've developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We've advanced it to Pipe-shaped BiCS flash memory with U-shaped NAND string, improving the operation window and the reliability and realizing the Multi-Level-Cell (MLC) operation. The functionality has been successfully demonstrated using the 32 Gbit test chip with the 16 stacked layers and the MLC operation by 60nm P-BiCS flash technology.

The double lightly doped drain concave (DLC) MOSFET has been developed for sub-half-micrometer MOSFETs which can operate at a 5-V supply voltage. This structure has an impurity profile of n/sup +/-n/sup -/-p/sup -/-p along the sidewall of the groove. It is found that the DLC MOSFET has excellent characteristics, such as high drain sustaining voltage, less short-channel effect, high current drivability, and high reliability, due to the double LDD concave structure. The DLC MOSFET is one of the most promising device structures for sub-half-micrometer MOSFETs. >

An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.

The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the sidewalls of the pillars are used effectively as the transistor channel, the M-SGT has a high-shrinkage feature. The area occupied by the M-SGT can be shrunk to less than 30% of that occupied by the planar transistor. The small occupied area and the mesh-structured gate electrode lead to the small junction capacitance and the small gate electrode RC delay, resulting in high-speed operation. The fabrication of the M-SGT CMOS inverter chain is discussed. The propagation delay reduces to 40%, compared with the planar transistor inverter chain. >

A transistor with compact structures for future MOS devices is discussed. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. By using this transistor, the occupied area of the CMOS inverter can be shrunk to 50% of that using planar transistors. Other advantages, such as steep cutoff characteristics, very small substrate bias effects, and high reliability, are discussed. Its structure, which allows for the enlargement of gate-controllability to the channel and electric field relaxation at the drain edge, is described. The advantages of this SGT for large-scale integration (LSI) devices is discussed. >

A 64-Mb CMOS dynamic RAM (DRAM) measuring 176.4 mm/sup 2/ has been fabricated using a 0.4- mu m N-substrate triple-well CMOS, double-poly, double-polycide, double-metal process technology. The asymmetrical stacked-trench capacitor (AST) cells, 0.9 mu m*1.7 mu m each, are laid out in a PMOS centered interdigitated twisted bit-line (PCITBL) scheme that achieves both low noise and high packing density. Three circuit techniques were developed to meet high-speed requirements. Using the preboosted word-line drive-line technique, a bypassed sense-amplifier drive-line scheme, and a quasi-static data transfer technique, a typical RAS access time of 33 ns and a typical column address access time of 15 ns have been achieved. >

A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs. >

Program and erase operation on NAND-string of Bit-Cost Scalable (BiCS) flash memory has been successfully achieved. High boost efficiency of floating pillars and ONON (block oxide/charge SiN/tunnel oxide/tunnel SiN) structure as a memory film stack improve disturbance characteristics enough to realize tera-bit density of three dimensional flash memory. BiCS flash memory has become a more promising candidate for ultra high density memory.

Physics of autonomous refresh of FBC is presented. Current input to the floating body by impact ionization and output by charge pumping can balance to make FBC refresh by itself without sense amplifier operation. Thanks to this feature, multiple cells on a BL can be refreshed simultaneously, leading to a drastic reduction of BL charging current compared to the conventional refresh. 600 muA refresh current for 1 G-bit memory is achieved in 32 nm technology node with 4 ms retention time. If gate direct tunneling current is used as output, FBC can realize static RAM without periodical refresh when retaining data.

A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 1016cm-3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.

The most appropriate method to evaluate the process damage is proposed. FeRAM process is used as a damage source. The degradation of the drain current of long-channel MOSFET is larger than that of short-channel MOSFET, although long-channel MOSFET has been believed to be more robust. In the case of short-channel MOSFET, the drain current is limited by saturation velocity, and thus the mobility degradation caused by the process damage has a smaller influence. On the contrary, in the case of long-channel MOSFET, the drain current is not limited by saturation velocity, which leads to the degradation of the drain current owing to the mobility reduction caused by the process damage of the FeRAM capacitor process. These results suggest that the most accurate method for evaluating the process damage is to monitor the degradation of the drain current of long-channel MOSFET.

Magnetoresistive Random Access Memory (MRAM) is a promising device for high-density (over Gbits scale), high-speed (equal to DRAM or better) non-volatile RAM, and much research has been done over several years with a view to overcoming the problems regarding practical use. Spin Torque Transfer switching MRAM (STT-MRAM) is considered to be the most promising candidate and there already are some papers on this new device. MgO is expected to be the best material for magnetic tunnel junction (MTJ) of STT-MRAM, because MgO-MTJ is known to show large Magnetoresistance (MR) and enhance spin polarization by the coherent tunneling effect, resulting in decrease of writing current of MTJ. MgO-MTJ has been shown to be an excellent barrier with little resistance drift compared with MTJ using alumina. Notwithstanding its excellent potential, the degradation mechanism of MgO-MTJ has not been well understood. In this paper, we will demonstrate for the first time the degradation of coherent tunneling and trapping phenomena of MgO-MTJ and discuss its mechanism.

A 6F2 single cell (one-cell-per-bit) operation of the floating body RAM (FBRAM) is successfully demonstrated for the first time with more than 60% yield of 16Mbit area in a wafer. The signal sense margin (SSM) at actual read conditions is found to well back up the functional results. The parasitic resistance in the source and drain formed under the FBC's spacers can be optimized for making the SSM as large as 8muA at plusmn 4.5sigma without sacrificing the retention time.

We propose Bit-Cost Scalable (BiCS) technology which realizes a multi-stacked memory array with a few constant critical lithography steps regardless of number of stacked layer to keep a continuous reduction of bit cost. In this technology, whole stack of electrode plate is punched through and plugged by another electrode material. SONOS type flash technology is successfully applied to achieve BiCS flash memory. Its cell array concept, fabrication process and characteristics of key features are presented.

Study of the reliability of ultra-thin MgO tunneling barriers for spin transfer switching magnetoresistive random access memory (MRAM) revealed MgO to be an excellent film with little resistance drift. Precise control of CoFeB/MgO/CoFeB interface was found to be important for making highly reliable tunneling barriers.

Optimal process integration for array devices of bit-cost scalable (BiCS) flash memory is successfully developed. We adopt SiN-based gate dielectrics for the consistency with the 'gate-first' process which is unique to BiCS flash technology, and 'macaroni' body FETs for better controllability over the sub-threshold characteristics of depletion-mode poly-silicon transistors. With these technologies and newly devised 4F2 cell array, BiCS flash becomes a promising candidate for future ultra-high density memory.

An excellent 64Mb chain FeRAMtrade using a highly reliable capacitor with damage-robust MOCVD-PZT and SrRuO3/IrO2 top electrode (TE) is successfully demonstrated for the first time. A very large signal margin of 540mV at 1.8V is achieved for the capacitor as small as 0.19mum2. Large sensing margin is well maintained after 85degC storage, and 10 years lifetime is successfully guaranteed. The combination of damage-robust MOCVD-PZT and optimized SrRuO3/IrO2 TE as well as a sophisticated `chain' structure that has a small bit line capacitance (Cb) nature shows excellent reliability and scalability. This work demonstrates that high density 256Mb chain FeRAM with 0.1 mum2 planar capacitor can be realized

Floating Body Cell (FBC) is a one-transistor memory cell on SOI substrate, which aims high density embedded memory on SOC. In order to verify this memory cell technology, a 128Mb SOI DRAM with FBC has been designed and successfully developed. The memory cell design, and the experimental results, such as the signal and the retention characteristics, are reviewed. The results of the fabricated SOI DRAM and the prospect as embedded memory are also discussed.

A one-transistor memory cell on silicon-on-insulator, called Floating Body Cell (FBC), has been developed for high density embedded DRAM applications. The functionality of a 128Mb FBC DRAM using fully compatible 90nm CMOS technology has been successfully demonstrated. The memory cell design, such as fully-depleted (FD) operation with substrate-bias, and the process integration, such as well and Cu wiring, are reviewed. The scalability and future challenge of FBC technology are discussed as well.

A 64Mb chain FeRAM implemented in 0.13mum 3M CMOS technology is described. A quad-BL architecture reduces the die area by 6.5% and realizes 87.5mm2 die with an effective cell-size of 0.7191mum2 while eliminating BL-BL coupling noise. A high-speed ECC circuit and cell data write-back scheme achieves read/write cycle time of 60ns and 200MB/S burst