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Purpose: This paper aims to study the relationship between the ball grid array (BGA) flip-chip underfilling process parameter and its void formation region. Design/methodology/approach: A set of top-down scanning acoustic microscope images of BGA underfill is collected and void labelled. The labelled images are trained with a convolutional neural network model, and the performance is evaluated. The model is tested with new images, and the void area with its region is analysed with its dispensing parameter. Findings: All findings were well-validated with reference to the past experimental results regarding dispensing parameters and their quantitative regional formation. As the BGA is non-uniform, 85% of the test samples have void(s) formed in the emptier region. Furthermore, the highest rating factor, valve dispensing pressure with a Gini index of 0.219 and U-type dispensing pattern set of parameters generally form a lower void percentage within the underfilling, although its consistency is difficult to maintain. Practical implications: This study enabled manufacturers to forecast the void regional formation from its filling parameters and array pattern. The filling pressure, dispensing pattern and BGA relations could provide qualitative insights to understand the void formation region in a flip-chip, enabling the prompt to formulate countermeasures to optimise voiding in a specific area in the underfill. Originality/value: The void regional formation in a flip-chip underfilling process can be explained quantitatively with indicative parameters such as valve pressure, dispensing pattern and BGA arrangement. [ABSTRACT FROM AUTHOR]

Purpose: This paper aims to study the interfacial delamination found in the boundary of the copper/copper-epoxy layers of a multi-layer ceramic capacitor. Design/methodology/approach: The thermal reflow process of the capacitor assembly and the crack propagation from the initial micro voids presented in the boundary, and later manifested into delamination, were numerically simulated. Besides, the cross section of the capacitor assembly was inspected for delamination cracks and voids using a scanning electronic microscope. Findings: Interfacial delamination in the boundary of copper/copper-epoxy layers was caused by the thermal mismatch and growth of micro voids during the thermal reflow process. The maximum deformation on the capacitor during reflow was 2.370 µm. It was found that a larger void would induce higher vicinity stress, mode I stress intensity factor, and crack elongation rate. Moreover, the crack extension increased with the exerted deformation until 0.3 µm, before saturating at the peak crack extension of around 0.078 µm. Practical implications: The root cause of interfacial delamination issues in capacitors due to thermal reflow has been identified, and viable solutions proposed. These can eliminate the additional manufacturing cost and lead time incurred in identifying and tackling the issues; as well as benefit end-users, by promoting the electronic device reliability and performance. Originality/value: To the best of the authors' knowledge, the mechanism of delamination occurrence in a capacitor during has not been reported to date. The parametric variation analysis of the void size and deformation on the crack growth has never been conducted. [ABSTRACT FROM AUTHOR]