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This paper presents a single-ended 12-transistor SRAM cell capable of operating at near-threshold voltage in FinFET technology. This cell employs Schmitt trigger-based inverters and feedback cut write assist technique to improve performance properties. The simulations have been done through HSPICE using 10 nm FinFET technology at a supply voltage of 0.45 V and a temperature of 25°C under 5000 Monte Carlo tests. The proposed cell improves the read static noise margin by at least 1.01 times. The write static noise margin is also increased by at least 1.07. The proposed single-ended cell leads to a reduction of $ {\alpha _{BL}} $ αBL by 50% and offers low dynamic write power. The leakage power is also reduced by 1.03 times due to the use of single bitline in the cell structure, stack transistors in the write path and elimination of leakage in the read path. [ABSTRACT FROM AUTHOR]

A high-efficiency synchronous boost converter with near-threshold self-starting is proposed. It adopts a novel phased start-up method to achieve self-start when the input voltage is below the threshold voltage of the MOS device and without external auxiliary measures. This boost converter is fabricated in a 0.18 um COMS process with a 1.24 × 0.78 um 2 chip area, and can achieve a reliable self-start when the input voltage is below the threshold voltage of 40 mV. It has an input voltage range of 0.7–5 V, a load current range of 0–300 mA, a stable output voltage of 5 V, and a maximum peak efficiency of 95.01%. [ABSTRACT FROM AUTHOR]

Standard-cell-based memory (SCM) circuits with fully digital signals are attractive for power-/energy-constrained edge devices due to the strong voltage scaling capability, fast design iteration, and flexibility in integration. In this article, a 13-transistor (13T) static-random access memory (SRAM) circuit with ultra-wide range voltage scaling capability is proposed for ultra-low-power applications. By adopting the concept of SCM, the 13T SRAM cell is custom-designed, while providing fully digital inputs and outputs. Without any analog circuitry, the 13T memory array is fully synthesizable and compatible with the commercial semi-custom design flow. A specialized circuitry is employed in the 13T SRAM cell to enable cell-level bit-interleaving. An 8-kb 13T SRAM bank is fabricated in the UMC 55-nm low power CMOS technology, achieving an area density of $5 \mu \text{m}$ 2/bit. The minimum operational voltage for the 13T SRAM circuit is 324 mV, while the data retention voltage is down to 279 mV. The 13T SRAM circuit achieves the minimum energy point at 0.4 V for both the read (32.8 fJ/bit) and write (54.1 fJ/bit) operations, providing a good opportunity to perform voltage scaling together with logic blocks when embedded in the same power domain. [ABSTRACT FROM AUTHOR]

In the design of nonvolatile memory (NVM), the sense amplifier (SA) contributes a major part of the power consumption due to high-frequency read operations. This brief proposes a leakage-current-canceling current-sampling sense amplifier (LCCS-SA) for the suppression of the read power consumption by operating in near-threshold region. The proposed LCCS-SA adopts the technology of offset cancellation and single-ended differential circuit structure to compensate the effect of the leakage current. The bit-line (BL) leakage-induced read failure is effectively suppressed in near-threshold region. Monte Carlo simulation demonstrates that the proposed LCCS-SA can operate at a supply voltage of 0.4 V and achieves 4.4 times lower read energy per bit compared to the conventional current-sampling-based SA. [ABSTRACT FROM AUTHOR]

In this brief, a standard cell library targeting ultra-low voltages (ULVs) is designed in a 65-nm low-power CMOS technology to enable digital integrated circuits (ICs) to achieve good tradeoff among speed, power consumption, area, and reliability in the near/subthreshold region. The transistor sizes in the standard cells are optimized by threshold voltage tuning and technology feature exploration to enhance the switching and area efficiency of transistors. To balance the pull-up and pull-down networks, a Monte Carlo (MC) simulation-based balancing method is proposed. An AES-128 test circuit is fabricated by using the proposed library, achieving a minimum voltage of 0.338 V. Compared to the state of the art, our test circuit reduces the minimum energy delay product (EDP) by at least $3.55\times $. [ABSTRACT FROM AUTHOR]

This paper presents the sampling and comparator speed-enhancement techniques for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. Delayed cross-coupling comparator is introduced in this work, which enhances the comparator regeneration while keeping the noise comparable. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove the proposed techniques. The post-layout simulated SAR ADC consumes only $6.71~\mu \text{W}$ and achieves SNDR of 48.8dB at Nyquist input, resulting in a figure-of-merit (FoM) of 2.47 fJ/convertion-step. Simulation results show the proposed speed-enhancement techniques improve the sampling rate of SAR ADC significantly under near-threshold supply voltages.

Conscious perception of a near‐threshold (NT) stimulus is characterized by the pre‐ and post‐stimulus brain state. However, the power of pre‐stimulus neural oscillations and strength of post‐stimulus cortical activity that lead to conscious perception have rarely been examined in individual cortical areas. This is because most previous electro‐ and magnetoencephalography (EEG and MEG, respectively) studies involved scalp‐ and sensor‐level analyses. Therefore, we recorded MEG during a continuous NT somatosensory stimulus detection task and applied the reconstructed source data in order to identify cortical areas where the post‐stimulus cortical activity and pre‐stimulus alpha oscillation predict the conscious perception of NT somatosensory stimuli. We found that the somatosensory hierarchical processing areas, prefrontal areas and cortical areas belonging to the default mode network showed stronger cortical activity for consciously perceived trials in the post‐stimulus period, but the cortical activity in primary somatosensory area (SI) is independent of conscious perception during the early stage of NT stimulus processing. In addition, we revealed that the pre‐stimulus alpha oscillation only in SI is predictive of conscious perception. These findings suggest that the bottom‐up stream of somatosensory information flow following SI and pre‐stimulus alpha activity fluctuation in SI as a top‐down modulation are crucial constituents of conscious perception. [ABSTRACT FROM AUTHOR]

A novel dual mode logic (DML) model has a superior energy-performance compare to CMOS logic. The DML model has unique feature that allows switching between both modes of operation as per the real-time system requirements. The DML functions in two dissimilar modes (static and dynamic) of operation with its specific features, to selectively obtain either low-energy or high-performance. The sub-threshold region DML achieves minimum-energy. However, sub-threshold region consequence in performance is enormous. In this paper, the working of DML model in the moderate inversion region has been explored. The near-threshold region holds much of the energy saving of subthreshold designs, along with improved performance. Furthermore, robustness to supply voltage and sensitivity to the process temperature variations are presented. Monte carol analysis shows that the projected near-threshold region has minimum energy along with the moderate performance.

Near-threshold computing brings several times of magnitude improvement in energy efficiency of digital circuits. However, it also introduces several times of deteriorated delay variations caused by process, voltage, and temperature (PVT) variations. In situ timing monitoring-based adaptive techniques can mitigate excessive timing margins caused by PVT variations, but current frequency and/or voltage tuning methods cause large performance loss. In this paper, we propose a low overhead timing error prediction monitor and a super-fast clock stretching circuit to solve this problem. They are both optimized for near threshold voltage of 0.5 V. When there are timing margins, the frequency will be increased. Until when the timing is intense due to variations, timing monitors will generate a predicted alarm signal. Accordingly, the system clock will be stretched immediately to avoid real timing errors. Applied on a 40-nm CMOS Bitcoin Miner chip, simulation results show that the whole system operating at near-threshold voltage can increase the frequency to up to 2.1× compared with the original non-monitored circuit. Our method can increase the energy efficiency to mitigate near-threshold variations effectively.

Graphical abstract Highlights • Ti-containing welds possessed smaller size of prior austenite grains. • Ti-free welds performed better crack growth resistance at near-threshold regime. • Deflections in Ti-free welds enhanced the roughness induced crack closure. Abstract The resistance to fatigue crack growth and its correlation with microstructure for weld metals with different trace Ti element addition was systematically investigated in this paper. It is found that there were some obvious differences in grain size, block ferrite and precipitations for Ti-free and Ti-containing weld metal. Fatigue crack growth tests were conducted in weld center under different stress ratios, the results indicate that weld metal without Ti addition performed better on fatigue resistance in near-threshold regime at each stress ratio. Transgranular growth with crack deflections and intergranular growth with bifurcations are the typical crack growth behavior in Ti-free and Ti-containing weld centers respectively. It is revealed that large size of prior austenite grains in Ti-free weld center lead to more crack deflection via analysis on the fatigue crack growth path. Moreover, the carbides scattered on ferrite boundaries also lead to crack deflection and reduce the possibility of intergranular fracture at near-threshold for Ti-free weld center. Compared to crack bifurcations, the crack deflections contributed more to crack closure inducted by contact surface roughness, and the fatigue growth resistance is enhanced for Ti-free weld center. The correlation between fatigue resistance performance and misorientation of ferrite boundaries in weld centers was further clarified by electron back-scattered diffraction (EBSD) characterization. [ABSTRACT FROM AUTHOR]

Aircraft grade 7010 aluminum alloy was heat treated to two different conditions: (1) standard peak aging (T6) and (2) retrogression and re‐aging (RRA). The microstructures of these alloys were characterized by using transmission electron microscope. Fatigue crack growth rate (FCGR) tests were conducted using standard compact tension specimens, following ASTM standards. Tests were conducted at various stress ratios, R ranging from 0.1 to 0.7. The RRA‐treated alloy was observed to contain coarsened η′ (MgZn2) precipitates with higher inter‐particle spacing when compared with T6‐treated alloy. The grain boundary precipitates (GBPs) were also coarsened and discontinuous in RRA‐treated alloy as compared with continuous GBPs in T6 condition. The FCGR was lower and ΔKth was higher in RRA‐treated alloy compared with T6‐treated alloy at all the stress ratios investigated. Improved fatigue crack growth resistance in RRA‐treated alloy was correlated to the modified microstructure and enhanced crack closure levels. [ABSTRACT FROM AUTHOR]

• Fatigue strength decreases with increasing microstructure size. • Crack closure in coarse-microstructures inhibits near-threshold crack growth. • Fatigue crack propagates along the {110}<111> slip system (SS) with high SF. • Crack initiation at the interface of grains with high SF and low TF on {110}<111> SS. In this study, high-cycle S-N characteristics and fatigue cracking behaviors under near-yield mean stress of 42CrMo steel with two different fine/coarse-grain tempered sorbite/bainite microstructures (FGM/CGM) were investigated. The results show that fatigue strength is greater for FGM than for CGM as expected, but fatigue crack growth (FCG) threshold is higher for the latter. Compared to FGM with a single crack source, CGM has multiple fatigue sources together with higher-degree ratchetting-fatigue damage, i.e., plastic-strain, dislocation cells and sub-grains, thus accelerating fatigue crack initiation. In the near-threshold regime, roughness-induced crack closure in coarse-microstructures of CGM leads to FCG retardation behavior, which increases FCG threshold. In the Paris regime, CGM presents a similar FCG rate to FGM. Microstructure barriers (i.e., crystal interfaces, carbides and interfaces with different orientations), secondary cracks, crack-path fluctuations, ratchetting and plastic strain jointly result in severer crack-tip stress shielding effects in CGM than in FGM. However, fatigue crack tends to propagate through the high Schmid factor region with {110}<111> slip system with lower slip resistance in FGM but not in CGM, which facilitates fatigue cracking of the former. Under the combined effects of the above factors, similar FCG rates are thus exhibited in both steels with different tensile strengths. [ABSTRACT FROM AUTHOR]

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing.

Abstract Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ended read memory cell that consists of a total of 6 transistors. The innovative idea is to bring the loadless 4-transistor latch into the realm of low voltage memory cells by exploiting features of the 28 nm FDSOI Process and by adding a 2-transistor readbuffer with a footer line. Stand-alone and on a system level, the cell is stable during read, write and hold operations and it has great write-ability due to its differential write and loadless nature. The single NWELL option in 28 nm FD-SOI allows the loadless core to have minimal device widths while greatly improving the time it takes to evaluate the read bit-line. The cell has, in this paper, been used in a 128 kb (217) SRAM in a 16 block configuration exploring 3 different types of logic libraries for the peripheral logic of the system. Depending on the application, the IO-peripheral logic may be implemented using either high threshold voltage transistors or low threshold voltage transistors in where the power consumption of the 128 kb system was found to range from 1.31 µW to 71.09 µW, the maximum operational frequency lies within 1.87 MHz and 14.97 MHz while the read energy varies from 13.08 to 75.21 fJ/operation/bit for a supply voltage of 350 mV. The minimum retention voltage of the loadless SRAM cell is found to be 230 mV covering 5 σ of variation with Monte Carlo simulations. [ABSTRACT FROM AUTHOR]

This paper presents a near-threshold operating voltage timing error detecting 32-bit microcontroller system. The lightweight in situ error detection and correction technique uses a soft-edge flip-flop combined with in-latch transition detection and a set-dominant error latch to detect data path transitions after the clock edge. Inherent error correction is achieved through time borrowing in soft-edge flip-flops. The technique is implemented in an ARM Cortex M0 microcontroller system in 40-nm CMOS, rendering the microcontroller “timing error aware.” Automatic critical path analysis results in an optimized timing error detection window and sparse flip-flop replacement. An autonomous dynamic voltage scaling (DVS) loop facilitates automatic operation at the point of first failure. The M0 system operates down to 290 mV and achieves 11–18 pJ/cycle core energy consumption in a 5–30 MHz frequency ranges. The architecture profits optimally from ULV operation at frequencies <10 MHz, where intra-die variations are significant. [ABSTRACT FROM AUTHOR]

A 400W near-threshold supply class-C voltage controlled oscillator (VCO) with amplitude feedback loop and auto amplitude control (AAC) is proposed in this paper. The amplitude feedback loop and AAC ensure the robust startup of the proposed VCO and automatically adapts it to the class-C mode in steady state. Consequently, ultra-low power can be achieved in AAC mode and low phase noise, high swing can be achieved in AAC off mode. The proposed VCO with AAC gets ultra-low power consumption by limiting the oscillating amplitude and driving the proposed VCO into the deep Class-C mode. Additionally, the peak value detector is employed in this work to boost the controlling voltage of capacitors bank. Thus, a low on resistance of switch transistors is obtained, which increases the Q value of capacitors bank. The simulated phase noise is 124.5dBc/Hz at 1MHz offset with the 1.16GHz oscillation frequency. In this case, the figure-of-merit including tuning range (FOMT) of proposed VCO is 195dBc/Hz. The proposed VCO is fabricated in SMIC 40nm CMOS process and consumes 0.62mA from 0.65V supply. The measured phase noise is 109dBc/Hz and FOMT is 179dBc/Hz. [ABSTRACT FROM AUTHOR]

Shrinking of technology node in advanced VLSI devices and scaling of supply voltage degrade the performance characteristics and reduce the soft error resilience of modern downscaled digital circuits. In this paper, we propose a reliable near-threshold 7T SRAM cell with single ended read and differential write operations based on a previous proposed 5T cell. Our new cell improves read speed without degrading of write speed compared to the recently reported 7T cell. Furthermore, our proposed cell provides high soft error reliability amongst all the SRAM cells mentioned in this paper. We compared the performance and reliability characteristics of 5T, 6T, 8T and previous 7T cells with our new 7T SRAM cell to show its efficacy. The simulations are performed using HSPICE in 20 nm FinFET technology at V = 0.5 V. The results show that the new 7T cell has high write speed, read and write margins with improved read speed and low leakage power in the hold '0' state compared to 5T cell. In addition, the study of performance parameters under process and environmental variations considering ageing effect in near-threshold region shows the robustness of the proposed 7T SRAM cell against these variations. [ABSTRACT FROM AUTHOR]

In this paper, a closed-form expression for estimating the minimum operating voltage ( V\mathrm{ DDmin} ) of D flip-flops (FFs) is proposed. V\mathrm{ DDmin} is defined as the minimum supply voltage at which the FFs are functional without errors. The proposed expression indicates that V\mathrm{ DDmin} of FFs is a linear function of the square root of logarithm of the number of FFs, and its slope depends on the within-die variation of the threshold voltage ( V\mathrm{ TH} ) and its intercept depends on the balance between nMOS and pMOS, which is mainly due to the die-to-die V\mathrm{ TH} variation. The proposed expression of V\mathrm{ DDmin} is validated by the simulation results as well as the silicon measurements. Finally, we discuss the dependence of V\mathrm{ DDmin} on the device parameters. [ABSTRACT FROM AUTHOR]

We evaluate full-V DD and near-threshold operation of nine novel eight-transistor (8T) FinFET SRAM cell schemes using shorted gate (SG) and low power FinFET configurations for 32-bit by 1024-word SRAMs. 8T SRAM schemes outperform six-transistor schemes since SG-configured read FinFETs minimize delay and reverse-biased inverter FinFETs’ back gates reduce leakage current by up to 97%. At near-threshold, 8T FinFET cell delay increases by 56%, but leakage current and energy-delay product (EDP) decrease by up to 16% and 77%, respectively. 8T Low-Power Inverters scheme uses these configurations and reduces EDP by 60% (79% at near-threshold) versus the conventional SG 8T FinFET SRAM. [ABSTRACT FROM AUTHOR]

A conditional-boosting flip-flop is proposed for ultralow-voltage application where the supply voltage is scaled down to the near-threshold region. The proposed flip-flop adopts voltage boosting to provide low latency with reduced performance variability in the near-threshold voltage region. It also adopts conditional capture to minimize the switching power consumption by eliminating redundant boosting operations. Experimental results in a 65-nm CMOS process indicated that the proposed flip-flop provided up to 72% lower latency with 75% less performance variability due to process variation, and up to 67% improved energy-delay product at 25% switching activity compared with conventional precharged differential flip-flops. [ABSTRACT FROM AUTHOR]

The increasing popularity of DVFS (dynamic voltage frequency scaling) schemes for portable low power applications demands highly efficient on-chip DC-DC converters. The primary aim of this work is to enable increased efficiency of on-chip DC-DC conversion for near-threshold operation of multicore chips. The idea is to supply nominal (high) off-chip voltage to the cores which are then “voltage-stacked” to generate the near-threshold (low) voltages based on Kirchhoff’s voltage law through charge recycling. However, the effectiveness of this implicit down-conversion is affected by the current imbalance among the cores. The paper presents a design methodology and optimization strategy for highly efficient charge recycling on-chip regulation using a push-pull switched capacitor (SC) circuit. A dual-boundary hysteretic feedback control circuit has been designed for stacked loads. A stacked-voltage domain with its self-regulation capability combined with a SC converter has shown average efficiency of 78%–93% for 2:1 down-conversion with ILoad (max) of 200 mA and workload imbalance varying from 0–100%.

• Effects of microstructures on the FCP behavior of 42CrMo steel are investigated. • In the later stage of near-threshold and early stage of Paris-regime, FCP rate depends on the single coarse-microstructure. • Roughness-induced crack closure caused by coarse microstructures retards FCP under low ΔK conditions. • FCP behavior in the later stage of Paris-region depends on the microstructure group effects, or overall strength and fracture toughness of materials. Microstructural differences through the thickness have always been an attention focus for large-scale steel structures, since they could significantly influence fatigue crack propagation (FCP) characteristics. Here, the effects of microstructure in FCP behaviors of 42CrMo steel were analyzed with emphasis on two different tempered sorbite/bainite (TS/B) microstructures: (i) fine TS/B structures (M42); (ii) coarse TS/B structures (M52). The results show that the FCP rate is relatively slower for M52 than for M42 in the regime through the later stage of near-threshold (I-L) to the early stage of Paris-regime (Ⅱ-E) with low ΔK, but is fairly similar for the two cases in the other ΔK regimes. Under relatively low ΔK, the FCP path of M52 is more tortuous with numerous micro-cracks in B and larger-sized crack deflections at the carbides and boundaries compared to M42, especially in the I-L where fatigue micro-cracks can deflect at the single coarse carbide, thereby resulting in roughness-induced crack closure and crack retardation behavior. Theoretical analysis shows that FCP behaviors are closely related to the cyclic plastic region size (Δr p) at the crack-tip. In the early stage of near-threshold region, Δr p is restricted within a grain-size scale for both steels, thus leading to a similar FCP rate. However, from the I-L to the Ⅱ-E, coarse B/ferrite-grains in M52 are always larger than the Δr p of fatigue crack-tip, and thereby lead to numerous micro-cracks formation and crack deflections at the carbides and B boundaries, inducing crack closure. In the later stage of Paris region, B/ferrite-grains in the two cases are much smaller than Δr p , so that FCP behaviors depend on the microstructure group effects, or overall strength and fracture toughness of materials, which cause the close FCP rate. [ABSTRACT FROM AUTHOR]

High-Mn austenitic steels utilizing TWIP (twinning induced plasticity) effect have excellent combination of tensile strength and ductility. The near-threshold fatigue crack propagation (FCP) behavior, as represented by the ΔK th value, of high-Mn steels was examined with the emphasis on the effect of stacking fault energy (SFE), grain size, twinning and tensile properties. Even though no predominant parameter determining the near-threshold FCP behavior of high-Mn steels was found, the SFE showed the most reasonable correlation to the ΔK th values among the variables examined. It was also suggested that the slip reversibility as determined by SFE could not solely explain the near-threshold FCP behavior of high-Mn steels. The presence of twin boundaries appeared to be not beneficial in improving the resistance to FCP of high-Mn steels in low ΔK regime. The near-threshold FCP characteristics of high-Mn austenitic steels were discussed and correlated with the well-known parameters presumably affecting FCP. [ABSTRACT FROM AUTHOR]

Extending double-gate FinFET scaling to sub-10nm technology regime requires device-engineering techniques for countering the rise of direct source to drain tunneling (DSDT), edge direct tunneling (EDT) and short channel effects (SCE) that degrade FinFET I-V characteristics. Symmetric underlap is effective for eliminating EDT, diminishing DSDT, and lowering the fringe component of gate capacitance. However, excessive symmetric underlap also lowers the on-current, which is mainly due to thermionic emission. In this work, it is demonstrated that at sub-10nm node, asymmetric underlapped FinFETs with slightly longer underlap toward drain side than source side are superior to symmetric underlapped FinFETs due to further improvement in Ion/Ioff and reduction in gate-to-drain capacitance. Using quantum mechanical device simulations, FinFETs with various degrees of underlap have been analyzed for improvement in I-V characteristics. A FinFET model for circuit simulations has been constructed that captures the major sub-10nm leakage components, namely, thermionic emission, DSDT, EDT, direct gate oxide tunneling and its associated components. By simulating a 10-stage NAND circuit and a LEON3 processor with interconnect parasitics using these devices, it is shown that asymmetric underlap instead of symmetric underlap in sub-10nm Fin- FETs can offer lower energy consumption with improved performance for near-threshold logic and higher energy-efficiency for super-threshold logic operation. [ABSTRACT FROM AUTHOR]

The partial awareness hypothesis is a theoretical proposal that recently provided a reconciling solution to graded and dichotomous accounts of consciousness. It suggests that we can become conscious of distinct properties of an object independently, ranging from low-level features to complex forms of representation. We investigated this hypothesis using classic visual word masking adapted to a near-threshold paradigm. The masking intensity was adjusted to the individual perception threshold, at which individual alphabetical letters, but not words, could be perceived in approximately half of the trials. We confined perception to a pre-lexical stage of word processing that corresponded to a clear condition of partial awareness. At this level of representation, the stimulus properties began to emerge within consciousness, yet they did not escalate to full stimulus awareness. In other words, participants were able to perceive individual letters, while remaining unaware of the whole letter strings presented. Cortical activity measured with MEG was compared between physically identical trials that differed in perception (perceived, not perceived). We found that compared to no awareness, partial awareness of words was characterized by suppression of oscillatory alpha power in left temporal and parietal cortices. The analysis of functional connectivity with seeds based on the power effect in these two regions revealed sparse connections for the parietal seed, and strong connections between the temporal seed and other regions of the language network. We suggest that the engagement of language regions indexed by alpha power suppression is responsible for establishing and maintaining conscious representations of individual pre-lexical units. [ABSTRACT FROM AUTHOR]

In this paper, the performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation. The adder structures are selected from both the carry propagate adders (CPAs) and parallel prefix adders (PPAs). The performance parameters which are used in the comparative study include delay, power, energy, and energy-delay-product (EDP) of the adders. Additionally, the impacts of the process variation and negative bias temperature instability (NBTI) on the delays of the adders under the aggressive supply voltage scaling are investigated. Also, the efficacies of the adders are compared using a merit function based on their performance and reliability parameters for a wide range of supply voltage levels, from the nominal voltage down to the near-threshold voltage. The study is performed for the 32-bit adder structures designed based on the 14-nm FinFET and 45-nm bulk CMOS technologies. The results which are obtained using HSPICE simulations, reveal that the reliability parameters similar to the performance parameters are a function of the adder architectures and those are the key components to determine the efficiencies of the adders. Also, the results show that the impacts of the process variation and NBTI on the delays of the high performance PPA structures are more than those of the CPA structures for the whole range of the supply voltage. The PPAs, however, have the higher merit factors compared to the CPAs under a wide range of supply voltage levels. The results presented in this paper may provide some guidelines for the designers to select proper adder structures based on their design requirements and constraints. [ABSTRACT FROM AUTHOR]

Objective To improve the recognition and possibly prevent confounding peripheral activation of the facial nerve caused by leaking transcranial electrical stimulation (TES) current during corticobulbar tract monitoring. Methods We applied a single stimulus and a short train of electrical stimuli directly to the extracranial portion of the facial nerve. We compared the peripherally elicited compound muscle action potential (CMAP) of the facial nerve with the responses elicited by TES during intraoperative monitoring of the corticobulbar tract. Results A single stimulus applied directly to the facial nerve at subthreshold intensities did not evoke a CMAP, whereas short trains of subthreshold stimuli repeatedly evoked CMAPs. This is due to the phenomenon of sub- or near-threshold super excitability of the cranial nerve. Therefore, the facial responses evoked by short trains TES, when the leaked current reaches the facial nerve at sub- or near-threshold intensity, could lead to false interpretation. Conclusions Our results revealed a potential pitfall in the current methodology for facial corticobulbar tract monitoring that is due to the activation of the facial nerve by subthreshold trains of stimuli. This study proposes a new criterion to exclude peripheral activation during corticobulbar tract monitoring. Significance The failure to recognize and avoid facial nerve activation due to leaking current in the peripheral portion of the facial nerve during TES decreases the reliability of corticobulbar tract monitoring by increasing the possibility of false interpretation. [ABSTRACT FROM AUTHOR]

In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low V TH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the I on / I off ratio of its access transistors, a high V TH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The results reveal high write and read margins, the highest I on / I off ratio, a fast write, and ultra-low leakage power in the hold “0” state for the cell. Therefore, the suggested 7T cell may be considered as one of the better design choices for both high performance and low power applications. Also, the changes of cell parameters when the temperature rises from −40 °C to 100 °C are investigated. Finally, the write margin as well as the read and hold SNMs of the cell in the presence of the process variations are studied at two supply voltages of 400 mV and 500 mV. The study shows that the proposed cell meets the required cell sigma value (6 σ ) under all conditions. [ABSTRACT FROM AUTHOR]

This paper presents a design approach for upgrading the resiliency of ultra-low-voltage (ULV) microprocessors through a voltage-scalable and low-overhead in-situ error detection and correction (EDAC) technique. Particular efforts are made to overcome the poor voltage scalability and area/energy/throughput overhead of the existing EDAC techniques when applied to ULV designs. The 16 bit microprocessor employing the proposed EDAC and dynamic voltage scaling schemes is demonstrated in a 65 nm. The microprocessor can automatically modulate VDD based on timing error flags across static/slow variations and in-situ detect and correct the timing errors from fast dynamic variations, virtually eliminating timing and voltage margins. At a typical process/voltage/temperature corner, the proposed design improves the minimum energy consumption by 42% with 140 mV additional voltage scaling, as compared to the baseline design. At the same throughput (80 MHz), the proposed design consumes 38% less energy than the baseline operating at its minimum energy point. At the same energy consumption, the proposed design achieves 2.3\times higher throughput than the baseline design. The area overhead of the proposed design is 8.3%. [ABSTRACT FROM AUTHOR]

To minimize energy consumption of a digital circuit, logic can be operated at sub- or near-threshold voltage. Operation at this region is challenging due to device and environment variations, and resulting performance may not be adequate to all applications. This article presents two variants of a 32-bit RISC CPU targeted for near-threshold voltage. Both CPUs are placed on the same die and manufactured in 28 nm CMOS process. They employ timing-error prevention with clock stretching to enable operation with minimal safety margins while maximizing performance and energy efficiency at a given operating point. Measurements show minimum energy of 3.15 pJ/cyc at 400 mV, which corresponds to 39% energy saving compared to operation based on static signoff timing. [ABSTRACT FROM AUTHOR]

In this paper, a voltage-scaled SRAM for both error-free and error-tolerant applications is presented that dynamically manages the energy/quality trade-off based on application need. Two variation-resilient techniques, write assist and Error Correcting Code, are selectively applied to bit positions having larger impact on the overall quality, while jointly performing voltage scaling to improve overall energy efficiency. The impact of process variations, voltage and temperature on the energy-quality tradeoff is investigated. A 28 nm CMOS 32 kb SRAM shows 35% energy savings at iso-quality and operates at a supply 220 mV below a baseline voltage-scaled SRAM, at the cost of 1.5% area penalty. The impact of the SRAM quality at the system level is evaluated by adopting a H.264 video decoder as case study. [ABSTRACT FROM AUTHOR]

This paper presents two novel low-voltage level shifter designs: one based on cross-coupled PMOS transistors and the other using current mirror structure. These two level shifters are designed to address the problems of the existing state-of-the-art level shifters. Simulation at 65 nm shows that both of the proposed level shifters achieve significantly better performance (up to 12×) and energy consumption (up to 8×) than the state-of-the-art level shifters with similar or less area consumption while operating from near-threshold to super-threshold region, making them optimal for level shifting in low-power systems with multiple scalable voltage domains. [ABSTRACT FROM AUTHOR]

A low-power multi-functional electrocardiogram (ECG) signal processor is presented in this paper. To enable long-term monitoring, several architecture-level power saving techniques are proposed, including global cognitive clocking, pseudo-downsampling wavelet transform, adaptive storing, and denoising-based run-length compression. An ultra-low-voltage ADC is designed for low-power signal digitization with adaptive clocking. Through these architecture-level techniques, the total power consumption can be significantly reduced by 63% as compared to the conventional design. Several circuit-level design techniques are also developed, including ultra-low-voltage operation and near-threshold level shifting, to further reduce the power consumption by 33%. In addition, a low-complexity cardiac analysis scheme is proposed to realize comprehensive on-chip cardiac analysis. Implemented in 0.18 µm CMOS process, the proposed cognitive ECG processor consumes only 457 nW at 0.5 V for real-time ECG recording and diagnosis. [ABSTRACT FROM AUTHOR]

Abstract: The near threshold 7Li(p,n)7Be neutrons generated by incident proton energy having Gaussian distribution with mean energies from 1.85 to 1.95MeV, were studied as a practical neutron source for BNCT wherein an RFQ accelerator and a thick Li-target are used. Gaussian energy distributions with the standard deviation of 0, 10, 20 and 40keV for mean proton energies from 1.85 to 1.95MeV were surveyed in 0.01MeV increments. A thick liquid Li-target whose dimensions were established in our previous experiments (i.e., 1mm-thick with 50mm width and 50mm length) was considered in this study. The suitable incident proton energy and physical dimensions of Pb layer which serves as a gamma absorber and a Polyethylene layer which is used as a BDE were surveyed by means of the concepts of TPD. Dose distribution were calculated by using MCNP5. A proton beam with mean energy of 1.92MeV and a Gaussian energy distribution with a standard deviation of 20keV at a current of 10mA was selected from the viewpoint of irradiation time and practically achievable proton current. The suitable thicknesses of Pb gamma absorber was estimated to be about 3cm. The estimated thickness of the polyethylene BDE was about 24mm for an ideal proton current of 13mA, and was 18mm for a practical proton current of 10mA. [Copyright &y& Elsevier]

A 0.16 nJ/b MICS transmitter and 0.18 nJ/b super-regenerative receiver are demonstrated, where each is specifically designed to operate in the near-threshold region. The low-VDD transmitter utilizes a sub-harmonic injection-locked ring oscillator, edge combiner for frequency multiplication, and class-C power amplifier. The low-VDD receiver introduces a replica super-regenerative receiver as a method to reject common-mode noise sources, such as supply/substrate coupling, thereby reducing undesired self-oscillations and improving BER. Designed in a 90-nm CMOS process, the test-chip measurements show a sensitivity of -80 dBm at 500 kb/s and -65 dBm at 1 Mb/s, respectively, at a BER less than 10^-3, with 340 \muW total power. [ABSTRACT FROM PUBLISHER]