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Mucilage is a gelatinous high-molecular-weight substance produced by almost all plants, serving numerous functions for plant and soil. To date, research has mainly focused on hydraulic and physical functions of mucilage in the rhizosphere. Studies on the relevance of mucilage as a microbial habitat are scarce. Extracellular polymeric substances (EPS) are similarly gelatinous high-molecular-weight substances produced by microorganisms. EPS support the establishment of microbial assemblages in soils, mainly through providing a moist environment, a protective barrier, and serving as carbon and nutrient sources. We propose that mucilage shares physical and chemical properties with EPS, functioning similarly as a biofilm matrix covering a large extent of the rhizosphere. Our analyses found no evidence of consistent differences in viscosity and surface tension between EPS and mucilage, these being important physical properties. With regard to chemical composition, polysaccharide, protein, neutral monosaccharide, and uronic acid composition also showed no consistent differences between these biogels. Our analyses and literature review suggest that all major functions known for EPS and required for biofilm formation are also provided by mucilage, offering a protected habitat optimized for nutrient mobilization. Mucilage enables high rhizo-microbial abundance and activity by functioning as carbon and nutrient source. We suggest that the role of mucilage as a biofilm matrix has been underestimated, and should be considered in conceptual models of the rhizosphere.

Aims: This study investigated the influence of climate and soil on the exudation rate and polysaccharide composition of aerial nodal root mucilage from drought-resistant and drought-susceptible maize varieties. Methods: Two maize varieties were grown in two different soils (sandy-clay loam Acrisol and loam Luvisol) under simulated climatic conditions of their agroecological zones of origin in Kenya and Germany. The exudation rate of mucilage from the aerial nodal roots was quantified as dry weight per root tip per day and the mucilage was characterized for its polysaccharide composition. Results: On average, the mucilage exudation rate was 35.8% higher under the Kenyan semi-arid tropical than under the German humid temperate climatic conditions. However, cultivation in the loam Luvisol soil from Germany led to 73.7% higher mucilage exudation rate than cultivation in the sandy-clay loam Acrisol soil from Kenya, plausibly due to its higher microbial biomass and nutrient availability. The drought-resistant Kenyan maize variety exuded 58.2% more mucilage than the drought-susceptible German variety. On average, mucilage polysaccharides were composed of 40.6% galactose, 26.2% fucose, 13.1% mannose, 11% arabinose, 3.5% glucose, 3.2% xylose, 1.3% glucuronic acid, and 1% an unknown uronic acid. Overall, significantly higher proportions of the uronic acids were found in the mucilage of the plants grown in the Kenyan sandy-clay loam soil and under the Kenyan semi-arid tropical climatic conditions. Conclusions: Maize is able to enhance its mucilage exudation rate under warm climatic conditions and in soils of high microbial activity to mitigate water stress and support the rhizosphere microbiome, respectively. Graphical abstract: [Figure not available: see fulltext.].

Technology scaling has enabled drastic growth in the computational and storage capacity of integrated circuits (ICs). This constant growth drives an increasing demand for high-bandwidth communication between and within ICs. In this dissertation we focus on low-power solutions that address this demand. We divide communication links into three subcategories depending on the communication distance. Each category has a different set of challenges and requirements and is affected by CMOS technology scaling in a different manner. We start with short-range chip-to-chip links for board-level communication. Next we will discuss board-to-board links, which demand a longer communication range. Finally on-chip links with communication ranges of a few millimeters are discussed. Electrical signaling is a natural choice for chip-to-chip communication due to efficient integration and low cost. IO data rates have increased to the point where electrical signaling is now limited by the channel bandwidth. In order to achieve multi-Gb/s data rates, complex designs that equalize the channel are necessary. In addition, a high level of parallelism is central to sustaining bandwidth growth. Decision feedback equalization (DFE) is one of the most commonly employed techniques to overcome the limited bandwidth problem of the electrical channels. A linear and low-power summer is the central block of a DFE. Conventional approaches employ current-mode techniques to implement the summer, which require high power consumption. In order to achieve low-power operation we propose performing the summation in the charge domain. This approach enables a low-power and compact realization of the DFE as well as crosstalk cancellation. A prototype receiver was fabricated in 45nm SOI CMOS to validate the functionality of the proposed technique and was tested over channels with different levels of loss and coupling. Measurement results show that the receiver can equalize channels with maximum 21dB loss

A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.

With the increasing bandwidth requirements of computing systems and limitations on power consumption, optical signaling for chip-to-chip interconnects has gained a lot of interest. Hybrid integration of optical devices with electronics has been demonstrated to achieve high performance [1]-[4], and recent advances in silicon photonics have led to fully integrated systems [5]. These approaches pave the way to massively parallel optical communications. Dense arrays of optical detectors require very low-power, sensitive, and compact optical receiver circuits. Existing designs for the input receiver, such as TIA, require large power consumption to achieve high bandwidth and low noise, and can occupy large area due to bandwidth enhancement inductors. In this work, a compact low-power optical receiver that scales well with technology has been designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication. In most optical receivers, the photodiode current is converted to a voltage signal. A simple resistor can perform the I-V conversion if the resulting RC time constant is in the order of the bit interval (T_b) [5]. However, for a given photodiode capacitance and target SNR, the RC limits the bandwidth and hence the data rate. To avoid this problem, TIAs are commonly employed, which are highly analog, power hungry, and do not scale well with technology. One alternative is the integrating front-end to eliminate the need for resistance and breaking the bandwidth trade-off. However, this technique suffers from voltage headroom limitations, and requires short-length DC-balanced inputs [6]. The proposed receiver resolves this problem by employing an integrating RC front-end along with dynamic offset modulation technique that decouple the bandwidth/data-rate and integration/headroom trade-offs [7].

Using optics for chip-to-chip interconnects has recently gained a lot of interest. As data rates scale to meet increasing bandwidth requirements, the shortcomings of copper channels are becoming more severe. Hybrid integration of optical devices with electronics has been demonstrated to achieve high performance, and recent advances in silicon photonics have led to fully integrated optical signaling. These approaches pave the way to massively parallel optical communications. Dense arrays of optical detectors require very low-power, sensitive, and compact optical receiver circuits. Existing designs for the input receiver, such as TIA, require large power consumption to achieve high band width and low noise, and can occupy large area due to bandwidth-enhancement inductors. In this work, a compact low-power optical receiver that scales well with technology is designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication.

A 20Gb/s transmitter employing an analog filtering pre-emphasis equalization technique is presented. The transmitter dissipates 10mW from a 1.2V supply and occupies 0.01mm2. This high-frequency boosting equalization technique allows for compensating channel losses up to 20dB at Nyquist-rate. The prototype was fabricated in 65nm CMOS technology and characterized using lossy cables and 5" and 10" FR4 PCB traces.

In this paper, we present a low-power receiver that supports high data rates over bandwidth-limited and coupled links. The receiver employs a half-rate 2-tap speculative DFE architecture with a far-end cross-talk (FEXT) cancellation technique. Figure 25.6.1 shows the top-level architecture of the DFE receiver. Conventionally, analog taps of the equalizer are implemented using current mode summers, thus the power consumption of the DFE increases proportion ally with the number of taps. In the proposed architecture, a switched-capacitor S/H is employed to sample the input signal and combine it with the feedback coefficients at the front-end of the receiver, as shown in Fig. 25.6.2 (S/H/summer). In this design, the switched-capacitor network is modified to support two taps of DFE without any signal loss. This technique can be further extended to realize more number of taps. The extra power due to sampling capacitors, switches and voltage-mode DACs is very small.