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First principle calculations for efficient transition metal contacts with monolayer MoS2-WSe2 are carried out for complementary device application. The four parameters analysed are exchange energy, density of states, entropy measurements, and effective potential periodicity at interface. Each characterises the electrical contact, as exchange energy establishes stable interface with minimum energy (contacts with strong bonding); density of states determines the charge polarity selection (electron or hole transport) and carrier flow rate through interfaces; entropy measurement reveal contacts with minimum phonon scattering rate (enhanced mobility); and effective potential continuity provides an alternative view of contact resistance from quantum mechanical perspective. Combining these results reveal that in specific crystallographic orientation among the 3d group: V, Cr, Co, and Ni; from 4d group: Tc, Ru, Pd, Ag and from 5d group: Ir, Pt, Au form suitable elemental electrodes for MoS2-WSe2 complementary FET applications.

In this article, a 2-D TCAD simulation study on the forward and reverse characteristics of oxygen-terminated diamond (D:O) m-i-p+ Schottky barrier diode (SBD) is carried out considering the effects of Fermi level pinning due to surface states (SSs) and metal-induced gap states (MIGS). The device simulation considers drift-diffusion transport, SS charge neutrality level (CNL), MIGS through Fermi level pinning parameter (S), doping and temperature-dependent mobility model, incomplete ionization of dopants, and impact ionization models. The simulation validation is carried out for Al/Au Schottky metals at room temperature and at higher temperatures. A good comparison between the simulation and experiment is obtained around turn-on voltage (V T0∼ 1.0 V for Al and 2.0 V for Au Schottky contacts) and for anode voltage (VA) > VT 0. Through simulations, we estimated the type of SSs and their quantity, and the position of CNL (ECNL) within the diamond bandgap. The effect of ECNL position and pinning parameter on the forward and reverse characteristics is also simulated. The impact of ECNL and SS on reverse leakage current is also analyzed using a nonlocal barrier tunneling model. At higher temperatures, a good match between simulation and experiment of forward characteristics is achieved. © 1963-2012 IEEE.

The effect of interface trap variability (ITV) on horizontally stacked nanosheet FET (NSHFET) has been explored using TCAD based 3-D quantum corrected Drift-Diffusion simulation framework for sub-3 nm technology node. It is revealed that 3-stacked NSHFET shows 9.09% lesser VT variation compared to 3-stacked nanowire FET (NWFET) due to combined ITV sources such as charge neutrality level (CNL), single charged traps (SCTs), and random interface traps (RITs). The 3-stacked NSHFET and NWFET reduces the ITV induced VT variation by 31.3% and 28.8% respectively compared to the single stacked transistors. The NSHFETs of higher effective channel width shows better immunity to ITV. It is found that both Si NSHFET and NWFET transistors effectively suppresses the combined ITV sources induced VT, ION, and drain induced barrier lowering (DIBL) variations when the CNL is positioned between midgap and conduction band edge of the semiconductor bandgap. © 2021 IEEE.

A Density Functional Theory based simulation study on cubic crystal orientation dependent transition metal contact with monolayer MoS2/WS2 in reference to exchange energy, density of states and thermodynamic entropy measurements are studied. Exchange energy states the stability of the interfaces between MoS2/WS2 and transition metals. The density of states calculation reveals the transport dominance with respect to charge polarity (electron or hole) and magnitude of charge flow through the interface. Entropy gives an alternative view to analyse carrier-phonon scattering at the interface. Our calculations suggest that (100) and (111) orientated transition metals from 3d group like Sc, Ti, Cr, Co, and Ni, (110) orientated transition metals from 4d group like Tc, Pd, Zr, and Ag and from 5d group (100), (110) orientated elements like Ta, W, Os, Ir, Pt are better suited for elemental contact applications in MoS2 and WS2 channel-based CMOS logic FETs. © 1980-2012 IEEE.

In this article, the impact of random fluctuation sources, such as metal gate granularity (MGG), line edge roughness (LER), and random dopant fluctuations (RDFs), are numerically studied for U-shaped n-channel fully depleted silicon on insulator (FDSOI) MOSFET (U-SOIFET) over conventional n-channel FDSOI MOSFET (C-SOIFET) for 7-nm technology node. This article reports that improved short-channel effect immunity in U-SOIFET results in less $1\sigma $ threshold voltage ( ${V}_{T}$ ) and ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) fluctuations compared to C-SOIFET due to MGG and LER variability sources. U-SOIFET exhibits a low ${V}_{T}$ mismatch index ( ${A}_{\Delta VT}=1.78$ mV. $\mu \text{m}$ ) close to the literature reported. Due to combined variability sources, U-SOIFET shows less ${V}_{T}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}$ , subthreshold swing (SS), and DIBL fluctuations compared to C-SOIFET. Immunity to statistical variability sources makes U-SOIFET a suitable silicon on insulator (SOI) device architecture for future CMOS logic device applications.

In this article, we investigate the electro-thermal (ET) performance of stacked Si gate-all-around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) engineered contacts such as M0-wrap around the Si S/D epitaxial regions and M0 filling through S/D trenched regions in addition to the conventional scheme where metal (M0) epi on the S/D. The device ET performance is enhanced by increasing the device on-state current ( ${I_{on}}}$ ) by more than 10% with better device lattice heat removal from the hot-spot location of the NSHFET. This results in decreased device self-heating by lowering lattice hot-spot temperature ( $T_{L, max}$ ) and device effective thermal resistance ( $R_{th, eff}$ ) by more than 11% compared to conventional M0-epi-based NSHFET design. The junction temperature difference between the nanosheet channels is also lowered, which decreases the inter-sheet threshold voltage ( $V_{T}$ ) difference. The benchmarking study of the device designs reveals that M0-trench-based NSHFET gives the best performance from both electrical and thermal perspective for future sub-5-nm CMOS logic technologies.

First principle based atomistic simulations are carried out to study the contact interface between monolayer MoS and transition metals. Density functional theory is used to calculate total energy at the contact interface, density of states and effective electrostatic potential to investigate elemental transition metals for Ohmic contact with transition metal dichalcogenides. Interface study of cubic lattice orientation with monolayer MoS reveals that (100) plane for 3d group elements and (110) plane for 4d and 5d group elements exhibit stable configuration for Ohmic contact formation. The electronic density of states reveals the choice of suitable transition metals as appropriate electrode material for ideal Ohmic contact with MoS monolayer, while the effective crystal potential calculation reveal the electronic potential energy discontinuity at the contact interface for engineering lowest Schottky barrier height. © 2020 IEEE.

With scaling FinFETs in advanced logic technologies, fin thickness, source/drain (S/D) regions doping and lattice hot-spot temperature predominantly affect the fin channel thermal conductivity due to enhanced phonon boundary scattering and phonon-dopant impurity (mass and size) fluctuations and leads to more device SHE. In this paper, we investigated these effects on silicon-on-insulator (SOI) fin field effect transistor (FinFET) electro-thermal performance by TCAD analysis considering Boltzmann transport equation (BTE) for phonons with relaxation time approximation. Results showed that the channel kth is reduced for $\mathrm{W}_{\text{Fin}} < 50\ \text{nm}$, doping $\mathrm{N} > 1\times 10^{19}\ \text{cm}-3$ and it is further degraded due to increasing local hot-spot temperature. However, Silicon-on-diamond (SOD) technology improves the device ET performance due to increase in heat energy flux through diamond (higher kth) BOX layer towards the substrate. Impact of within-chip ambient temperature $(\mathrm{T}_{\mathrm{A}})$ on device logic performance reveals that the SOD FinFET exhibits lower hot-spot temperature compared to conventional SOI FinFET. It is also revealed that with SOD technology, FinFETs can be aggressively scale down to sub-10nm node with better lattice heat mitigation, which improves the FinFET logic performance. © 2020 IEEE.

BiCMOS technology can be a possible replacement for FDSOI and FinFET technology due to their higher transconductance, which allows them to operate at in THz range i.e. radio frequencies (RF) in addition to their higher voltage handling ability. The most advanced SiGe heterojunction bipolar transistor (HBT) technology (55-nm BiCMOS) demonstrates room temperature cut-off frequency ($f_{\mathrm{t}}$) and maximum oscillation frequency ($f_{\max}$) of 320 GHz and 370 GHz respectively. In this paper, we performed TCAD analysis to investigate the performance metrics, $f_{\mathrm{t}}$ and $f_{\max}$ of the SiGe HBT at different cryogenic temperatures. The calibrated Gummel characteristics reveals that a record DC current gain of $1.2\times 10^{4}$ is obtained at 77 K for $\mathrm{V}_{\text{BE}}=\mathrm{V}_{\text{CE}}=1.2\ \mathrm{V}$. The HBT device employs bandgap engineering by linearly varying the Ge concentration in the base region, which enhances the device performance. Both the bandgap engineering with linearly graded Germanium (Ge) profile (induces intrinsic drift field in the base) and the cryogenic operation of the HBT device results in enhancement of $f_{\mathrm{t}}$ and $f_{\max}$. Our simulations predict that the value of peak $f_{\mathrm{t}}$ decreases below 100 K due to increase in the emitter junction capacitance and the peak $f_{\max}$ increase is due to decrease in collector junction capacitance and base resistance. The aggregate metric $f_{\mathrm{t}}+f_{\max} > 1.2\ \text{THz}$ is achieved under cryogenic condition without scaling the device, this advantage can be utilized in the THz device applications. © 2020 IEEE.

The oxygen-terminated bulk boron doped diamond MOSFET has been designed and simulated using coupled drift-diffusion transport-poisson solver within the TCAD analysis. The diamond MOS capacitor (MOSC) performance is dictated by accumulation, depletion, and deep depletion regimes of operation. We successfully calibrate the fitting parameters in the physical models such as doping and high-field limited carrier mobility, dopant ionization energies, and energy band gap dependence on temperature with experimental C-V and transfer characteristics. We show that the threshold voltage is sensitive to high temperatures. The device exhibits reasonably good ON to OFF current ratio of 108-104at wide temperature range from 300 K-550 K. We also show that the device exhibits a breakdown voltage of-270 V with the chosen impact ionization coefficients

We have studied the impact of thermal contact resistance (TCR) ( Rth ) and within-chip ambient temperature ( TA ) on the device self-heating effect (SHE) and its effect on transient and steady-state performance of Si 3-Fin FinFET-based CMOS inverter (from N-14 to N-7 technologies) using coupled hydrodynamic-thermodynamic (HD-TH) mixed-mode simulations. The effect of the load capacitance ( CL ) on device lattice temperature ( TL ) and its impact on propagation delay ( tpd ) of the targeted CMOS inverter circuit are analyzed. The impact of technology scaling on SHE of inverter and its effect on circuit performance is also studied. We investigated the SHE in the 3-Fin FinFET-based ring oscillator (RO) and estimated the stage delay and frequency of oscillations. Our simulation results revealed that within-chip TA and Rth of gate, source, and drain ( Rth,GSD ) have significant effect on the logic circuit performance in terms of degradation of noise margin (NM), inverter gain ( gmax), and increase in tpd due to SHE from N-14 to N-7 technologies. © 1963-2012 IEEE.

This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron-phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heating effect (SHE) and reliability. We have investigated the HITR of Si/SiO2 and Si/metal-silicides on SHE of vertically stacked Si GAA NSHFET. Our simulation predictions reveal that a very noticeable effect of the HITR of Si/ M0 at front end of line (FEOL) and back end of line (BEOL) interface (FEOL/BEOL) is that the hot-spot location is shifted into the channel away from drain depletion region, which affects the device SHE and degrades device performance. The impact of nanosheet width ( ${W}_{NSH}$ ) and sheets stacking number ( ${N}$ ) on device SHE and drive current degradation with and without HITR effect are also studied. It is revealed that wider nanosheets with lower HITR can be a better device design choice for heat mitigation in high performance logic transistors.

Self-heating effect (SHE) is a serious issue in ultradown scaled 3-D transistors especially in silicon-on-insulator (SOI) transistors due to lower thermal conductivity SiO2 buried oxide (BOX) region. However, recently, diamond has become an attractive dielectric material due to its superior thermal conductivity (kth = 2000 W.m-1 .K-1 ). In this paper, we designed FinFETs with diamond as BOX region material (i.e. SOD FinFET) and investigated the SHE in comparison with bulk and SOI FinFETs with similar design parameters using 3D TCAD analysis from 14nm to 7nm CMOS technology node. The SOD FinFET shows better heat removal from device active (channel) region by lowering the active region temperature by 17% and 28% compared Bulk and SOI designs respectively. The effective thermal resistance (Rth,eff) is also lowered by 40% and 54% compared Bulk and SOI FinFETs respectively. This result in lower degradation in drive current for SOD FinFET with efficient active region heat energy removal enabling continued energy-efficient scaling to sub-7nm node. The impact of thermal boundary conditions (Rth,GSD and TA) on transistor performance are also investigated in this work.

We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge roughness (LER) using quantum corrected 3-D drift diffusion (DD) simulation framework. The statistical simulation predictions reveal that for ultra downscaled SOI FinFET, the MGG predominantly affects device threshold voltage. Similarly, the LER sources are found to strongly influence the variability of device short channel effect immunity and channel mobility of carriers. Both MGG and long correlation length LER are found to strongly influence the overlap and outer fringing parasitic capacitances variability, resulting in increased variability of device intrinsic speed. It is predicted that the presence of combined random fluctuation sources results in the increased variability of threshold mismatch index ( $A_{\text {VT}}$ ) for the sub-10-nm SOI FinFET technology.

The current and voltage characteristics of a MOSFET device are maily characterized by the source to channel barrier which is controlled by the gate voltage. The Boltazmann statistics which govern the number of carriers that are able to cross the barrier indicates that to increase the current by a decade, atleast 60 mV of rise in gate voltage is required. As a result of this limitation, the threshold voltage of modern MOSFETs cannot be less than about 0.3 V for an ION to IOFF ratio of 5 decades. This has put a fundamental bottleneck in voltage downscaling increasing the power consumption in modern IC based chips with billions of transistors. Sayeef Salahuddin and Supriyo Dutta proposed the idea of including ferroelectric in MOSFET gate stack which allows an internal voltage ampli�cation at the MOSFET channel which can be used to achieve a smaller subthreshold swing which would further reduce the power consumption of the devices. In this thesis we have undertaken a simulation based study of such devices to study how the inclusion of negative capacitance ferroelectrics leads changes in various device characteristics. Initially we have taken a compact modeling based approach to study device characteristics in latest industry standard FinFET devices. For this purpose we have used the BSIM-CMG Verilog A model and modi�ed the model appropriately to include the e�ect of negative capacitance ferroelectric in the gate stack. This simulation allowed us to observe that negative capacitance (NC) devices can indeed give a subthreshold swing lesser than 60 mV/dec. Further other interesting properties like negative output resistance and drain induced barrier rising are observed. Using the compact models developed above, we have analyzed some simple circuits with NC devices. Initially an inverter shows a hysteresis in the transfer characteristics. This can be attributed to negative di�erential resistance. Ring oscillator analysis shows that RO frequency for NC devices is lesser than

Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designing well-tempered CMOS devices for future logic nodes. The device thermal contact resistances are strongly influenced by both the ambient temperature and within device lattice temperature. The ambient heat energy coupling through the thermal contact resistances will strongly impact device SHE in FinFETs due to increase in the surface-to-volume ratio of confined geometry thin Si Fin. In this paper, we report a 3-D quantum-corrected electrothermal numerical device analysis involving a coupled hydrodynamic and thermodynamic transport models for a target Si 3-Fin bulk n-FinFET. The numerical device simulations quantitatively predicted the impact of ambient and electrical contact temperatures on device short-channel effect immunity and performance. The simulation parameters are calibrated with the state-of-the-art Si FinFET measurement data from the literature. Our numerical simulation findings establish the phenomena of ambient temperature-induced device SHE on Si n-FinFETs performance for sub-14-nm technology nodes. The simulation predictions establish the fact that the thermal contact resistances and the within-chip ambient temperature (TA) have adverse effects on device lumped thermal resistance (Rth,eff) and performance metrics. Finally, we have numerically analyzed the FinFET design solutions (tapered source and drain regions) to improve the tolerance against the ambient temperature-induced SHE.

In this paper, we present a variability-aware 3-D mixed-mode device simulation study of Si Gate-All-Around (GAA) Nanowire MOSFET (NWFET) based 6-T SRAM bit-cell stability and performance considering metal-gate granularity (MGG) induced intrinsic device random fluctuations and quantum corrected room temperature drift-diffusion transport. The impact of MGG contributed intrinsic variability on Si GAA n- and p-NWFETs based SRAM cell Static Noise Margins (SNM), write and read delay time are statistically analyzed. Our statistical simulations predict acceptable stability for the Si NWFET 6-T SRAM cell with V DD downscaling up to 0.5 V. The simulation estimated mean hold SNM values follow a lowering trend with V DD downscaling, similar to the hold SNM experimental data reported in literature for Si GAA NWFET based SRAM arrays. We further show a linear variation in statistical variance of hold SNM with gate metal grain size and work function.