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A fully photolithographic dual threshold voltage (VT) organic thin-film transistor (OTFT) process suitable for flexible large-area integrated circuits is presented. The nearroom-temperature (<; 95 °C) process produces integrated dual VT pentacene-based p-channel transistors. The two VT 's are enabled by using two gate metals of low (aluminum) and high (platinum) work function. The Al and Pt gate OTFTs exhibit nominally identical current-voltage transfer curves shifted by an amount ΔVT. The availability of a high-VT device enables area-efficient zero-Vos high-output-resistance current sources, enabling high-gain inverters. We present positive noise margin inverters and rail-to-rail ring oscillators powered by a 3-V supply-one of the lowest supply voltages reported for OTFT circuits. These results show that integrating nand p-channel organic devices is not mandatory to achieve functional area-efficient low-power organic integrated circuits., Semiconductor Research Corporation. Focus Center Research Program for Center for Circuits and Systems Solutions (Contract 2003-CT-888)

An integrated organic temperature-sensing circuit array compatible with flexible and large-area substrates is presented. The array outputs an average value of 6.8 mV/A[over-carat][degree symbol]C, which is 22A[over-tilde] more responsive than the MOSFET implementation while dissipating 90 nW/cell. Highly linear outputs enable two-point calibrations that remove the effects of cell-to-cell variation., Semiconductor Research Corporation. Focus Center Research Program for Center for Circuits and Systems Solutions (C2S2) (contract 2003-CT-888), Natural Sciences and Engineering Research Council of Canada (NSERC), Hewlett-Packard Company

The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage [DELTA]V for a given current. An empirical equation describing [DELTA]V in terms of different gate and drain bias stress measurements and stress times is presented and verified. In the measured devices, [DELTA]V saturates at 14 V, independent of the gate bias-stress condition. A model based on carrier trapping rate equation that accounts for this [DELTA]V saturation is developed. The model suggests that the [DELTA]V saturation is due to the small density of traps compared to the channel carrier density., Semiconductor Research Corporation. Focus Center Research Program (Contract 2003-CT-888)

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009., Page 179 blank. Cataloged from PDF version of thesis., Includes bibliographical references., Organic semiconductors offer the potential of large-area, mechanically flexible electronics due to their low processing temperatures. We have developed a near-room-temperature (< 95°C) process flow to fabricate pentacene integrated organic thin-film transistors (OTFTs) compatible with plastic substrates such as polyethylene terephthalate (PET). Integration of inkjet printed organic photoconductors (OPDs) based on titanyl pthalocyanine with OTFTs is demonstrated for the first time in an integrated process. Using the OTFT as a switch in series with an OPD, a pixel circuit was designed and measured, in addition to a proof-of-concept 4x4 active matrix imager. The individual pixels were measured to have a responsivity of 6x10-5 A/W, and a pixel on/off conductance ratio of 880, both at an irradiance of 5 mW/cm 2. The imager uses a 25 V power supply and was shown to correctly image a "T" pattern after 1st order calibration. A model for the current-voltage characteristics based upon amorphous silicon models was implemented in MATLAB to investigate design trade-offs in organic digital circuits. A dual threshold voltage process is suggested to enable area-efficient zero-VGS current sources. The area and power savings of this approach is discussed compared to a single VT process. We also motivate the necessity for lowering the power supply, both for area savings and improvement in circuit lifetime due to reduction in bias stress effects. A process flow for a dual VT OTFT technology, enabled using two gate metals, is presented. By using a low work function metal (aluminum) and a high work function metal (platinum), we can obtain two threshold voltage devices., (cont.) Devices were measured to be nominally identical, shifted by a VSG which we call the [Delta]VT. A [Delta]VT of 0.6 V was consistently observed over multiple wafer lots. This is the first demonstration of modification of OTFT VT by changing the gate work function. Area-minimized digital logic designed in the dual VT technology was demonstrated with a 3 V supply, the lowest supply reported for integrated OTFTs. In addition, we report some of the first analog organic integrated circuits, including a differential pair with differential gain of 23 dB and common-mode rejection ratio (CMRR) of 23 dB. A two-stage uncompensated operational amplifier was fabricated and measured to have an open-loop gain of 36 dB and unity gain frequency of 7.5 Hz. The op-amp has a unity gain-bandwidth product of 473 Hz while dissipating < 2 nW with a 5 V supply. The comparator uses 5 nW of power, and has an input offset of 200 mV. We show the frequency response of the op-amp and comparator are dominated by parasitic overlap capacitances. The parasitics of the zero-VGs load limits frequency response, and technological improvements to increase operating frequency are suggested. We motivate a self-aligned process flow, which uses a high optical density gate to serve as a mask layer. A backside exposure patterns the source/drain layer. It is demonstrated that the parasitic capacitances can be reduced by almost an order of magnitude, from 1 fF/jlm to 0.15 fF/jm. A method to improve carrier mobility is also presented. These process improvements have the potential to improve the switching speeds of organic circuits by more than two orders of magnitude., by Ivan Alexander Nausieda., Ph.D.

For the first time, we demonstrate control of organic thinfilm transistor's (OTFT) threshold voltage (V [subscript T]) by modifying the gate work function. We present a near-room-temperature, fully lithographic process to fabricate integrated pentacene dual V [subscript T] OTFTs suitable for large-area and flexible mixed signal circuits. Platinum and aluminum are used as the gate metals for the high V [subscript T] (more depletion-like) and low V [subscript T] (more enhancement-like) p-channel devices, respectively. The availability of a high V [subscript T] device enables area-efficient zero-VGS current source loads. We demonstrate positive noise margin inverters which use pico Watts of power and a 3 V supply. Compared to a single V [subscript T] implementation, the dual V [subscript T] inverter occupies an area that is 30Ã Â smaller, and is 17Ã Â faster. These results show that p-channel only organic technologies can produce functional and low-power circuits without integrating a complementary device., Semiconductor Research Corporation. Center for Circuits and Systems Solutions (Contract 2003-CT-888), Martin Family Society of Fellows for Sustainability