Search

Background Many of these plants, have therapeutic effects and can be extracted and used in preparation of drugs, used directly or in combination with other plant extracts for medication which is a common practice in developing counties. Unfortunately, many of those who utilize these plants therapeutically do not have adequate knowledge or training in the safe use of the products. For these reasons, natural plant products need to be standardized and preliminary studies done to evaluate possible risks such as undesirable side effects, overdose and toxicity. Results Ethyl acetate extract of Musa × paradisiaca L shown anticervical carcinoma and anti-malignant melanoma activity in our study. Antioxidant activity demonstrated, that Musa × Paradisiaca L. leaves ethyl extract exhibited % inhibition at absorbance 517 nm with IC50 values = 3.70 to 45.50 at different concentration and compared with ascorbic acid as standard drug. Conclusions The present study indicates the anticancer and antioxidant activity on the basis of biological and phytochemical screening of Musa × paradisiaca L leaves extract. Ethyl acetate extract of leaves was evaluated for its anticancer activity. In vitro anticancer activity of extract were estimated by measuring significant inhibition of HeLa and A375 cell lines by MTT assay. The MTT assay clearly indicates that the inhibition or inhibitory activity of the extract was concentration dependent. Maximum inhibition of cell growth was found at the concentration of 320 µg/ml which was 54.35 and 55.97, respectively for HeLa and A375 cell lines. Therefore, 320 µg/ml concentration of extract was used to study the IC50 value that was calculated as 249.1 and 224.4, respectively. Antioxidant activity demonstrated that, plant extract exhibited percentage inhibition with IC50 values = 3.70 to 45.50 at different concentration and compared with ascorbic acid as standard drug.

The elliptic curve cryptographic (ECC) technique is employed for various security standards like security key management, digital signature and data authentication. The ECC technique is capable of undertaking sequential and equivalent mode processes through the unified design that is used equally for binary field and in the leading area of cryptosystems. Furthermore, a progressive transposition method and control information route are combined with the ECC mainframe, which offers efficient throughput, and adaptive calculation with low power. The dual-field Montgomery multiplier-carry save adder (DMM-CSA) structure is designed for the ECC system. The DMM structure has been developed using CSA in this method. The adder requires more number of Full Adders for the circuit design, which has occupied more area. To overcome this problem, this work introduces the dual field Vedic multiplier-look up table carry select adder (DVM-LCSLA) which is used to increase the performance of the ECC scheme for 256 bit. The first aim of the methods mentioned above is to develop a high-performance modular inversion for the ECC technique by employing application specified integrated chip and field programmable gate array (FPGA) implementation with the help of Verilog code. FPGA results indicate the analysis of power utilization, time delay information and Hardware area overhead in DVM-LCSLA used in ECC system compared to the state-of-art methods.

The emerging growth in communication arena firmly demands a secure channel and needless to mention that security and privacy of the user are the top priorities in audio communication. To transmit audio signals safely, cryptography is being adopted widely. Chaos-based cryptography is one of the effective strategies that attract researchers to develop more techniques. Characteristics of chaotic systems such as ergodicity and stochasticity are the main motivators for using them in encryption schemes. This work presents an field programmable gate array (FPGA) governed chaotic audio encryption scheme based on Lorenz attractor. This scheme of encryption undergoes two consecutive steps of operations, namely confusion by linear feedback shift register (LFSR) and diffusion through the random numbers generated in X, Y, and Z planes of the chaotic attractor. A study has also been carried out to analyze the best diffusion from the obtained results. Evaluation of the proposed scheme includes entropy, correlation, histogram, PSNR, and MSE. Further, NIST SP 800-22 batteries of test have been performed to ensure that the encrypted audio data possesses more randomness. Moreover, this work consumed 15,422 logic elements and 14.22 mW of dynamic power to accomplish the design. Noticeably, the proposed work has achieved 10.346 Mbps as a throughput to encrypt 216 × 16 bit samples of audio data.

Neurocysticercosis (NCC) is a parasitic disease of the central nervous system, which is caused by the metacestode of the pork tapeworm,Over a period of 2 years, 152 active epilepsy patients were investigated based on clinical, epidemiological, neuroimaging (contrast-enhanced computerized tomography), and immunological techniques to establish the diagnosis of NCC. A precoded questionnaire was administered to patients and/or guardians to collect detailed medical history.Ninety-three cases (61.2%) fulfilled either definitive or probable diagnostic criteria for NCC. Anti-cysticercus immunoglobulin G antibodies were detected by ELISA and enzyme electro-immune transfer blot in 69 (45.4%) active epilepsy patients. Seroprevalence was higher in males, 46.6% (54/116); than in females, 41.7% (15/36), and increased significantly with age; peaking in the 20-39 years age group (36/76; χThis study indicates that NCC is a major cause of active epilepsy in Assam. A high prevalence of pediatric NCC is also a major concern.

This study was performed to assess the anticancer potential of Musa × pardisiaca L. It has several traditional benefits due to the presence of various bioactive compounds. Ethyl acetate extract of leaves was prepared and characterized by Gas Chromatography-Mass spectrometry (GC-MS). Compounds ( 1-40 ) were isolated from leaves, out of which two major compounds i.e. eugenol and phytol are potentially responsible for anticancer activity and oxidative stress. In vitro cytotoxicity of extract showed significant inhibition of cells in cervical carcinoma and malignant melanoma when treated by MTT assay against Hela and A375 cell lines. Ethyl acetate extract of musa × paradisiaca L. shown anticervical carcinoma and anti-malignant melanoma activity in our study.

In the current semiconductor technology evolution, reliability is a primary concern especially for the applications like banking, defense, medical, etc. To improve the reliability, redundancy techniques are most commonly used by means of either in hardware, software, time or information. Once the correctly designed circuit is manufactured, there must a testing procedure to check there are no flaws. Here, the importance of hardware redundancy to enhance the reliability and testing to verify the designs are explored. This study mainly deals with exhaustive single stuck-at fault coverage of majority voters (MV) of triple modular redundancy (TMR) configuration which in turn helps to mitigate single event upset (SEU) errors. In total, there are eight different majority voters of TMR configuration are analyzed, and a minimal test set is obtained in each voter circuits. In this paper, theoretical study conveys that the majority voter circuits namely MV4, MV5, MV5, MV6, MV7 and MV8 produce a minimal test covering all faults.

Looking at the demands of secure communication schemes, new platforms for information security have a significant role in the data protection. In this paper, image encryption on reconfigurable hardware FPGA has been proposed with the confluence of the chaotic map and DNA schemes. Confusion and diffusion were performed with both Chaotic and DNA approaches. The image encryption architecture with 128 × 128 grayscale image which was implemented on Cyclone II FPGA EP2C35F672C6 consumed 23,877 (72%) logic elements, 131,072 (27%) internal M4KRAM memory units with a total thermal power dissipation of 273.55 mW for a test image. NPCR, UACI, Correlation, Uniform distribution and entropy analyses revealed the strength of the proposed scheme which requires a specific bitstream and hardware to retrieve and decrypt the hidden secret image on FPGA.

As the technology is growing rapidly in recent years, communication and signal processing systems become more complex with the increase in a number of elements or devices. To produce more reliable devices by eliminating the errors occurred by transient faults, there is a need for fault-tolerant techniques like Dual Modular Redundancy, Triple Modular Redundancy, and N-Modular Redundancy. These techniques often contain hardware redundancy which allows continued operation in the presence of faults and recovers the faulty hardware quickly and efficiently. Digital filters are one of the most commonly used in many applications, communications with filtering applications, data storage in CD-ROM or any hard disk drive, audio processing applications, and video processing applications. In this paper, different 5-modular redundancy configurations are used to get better performance, to lower the total power dissipation and to occupy less area. The circuits are synthesized and implemented on Altera EP4CE115F29C7 FPGA device using Quartus II 13.1 synthesis tool.

Our daily life is surrounded by agreements, whether we realize it or not. From breakfast to supper we make a number of agreements, irrespective of our ability to do so. For example, the transfer of property through sale, mortgage, lease, exchange, or gift, the formation of partnerships and companies, performing arbitration, mediation, negotiation and conciliation, registering patents, copyrights, intellectual properties, the execution of negotiable instruments, insurances and various services. When the agreement is made by a competent person then it is recognized and protected by law; while in the case of an incompetent party (particularly a minor) it lacks such recognition and protection by law (vide sections 10 and 11 of the Indian Contract Act, 1872). A minor's agreement stands void ab initio (Mohiri Bibee, 1903 PC), hence a minor is discharged from the contractual obligations. But under several laws, such as the TPA, the Sales of Goods Act, the Partnership Act, the Companies Act and the Insurance Laws etc. a minor is allowed to be a beneficiary through the contract created thereunder. Though the Indian Contract Act, 1872, does not allow a minor directly to be a beneficiary, even through judicial pronouncements, this gap has been filled. On the contrary the situation is not clear where this minor is fraudulent. Accordingly the consequence of a minor's agreement in terms of nature and effects is not clear under the Indian Contract Act, 1872, or under the Specific Relief Act, 1963. This legislative gap under the Act of 1872was what attracted to the author to do the analytical research deploying doctrinal research methodology applying null hypothesis. This article has been divided into sections. Under section 2 the formal introduction of agreement and contract is discussed with its essentials, section 3 concerns the legislative gap pertaining to the consequences of a minor's agreement, section 4 examines the fulfilment of the legislative gap through judicial pronouncement and section 5 contains the conclusion with suggestions.

Image encryption plays a crucial role in modern day secure multimedia communication. Confusion and diffusion are the two important mechanisms to encrypt the images employed in most of the image encryption schemes. In this paper, a grayscale image encryption method has been proposed with the confluence of Linear Feedback Shift Register (LFSR), Cellular Automata (CA) and hardware generated synthetic image. CA manages scrambling as well as diffusion. LFSR generates diffused bits which are sampled with hardware created clock source on Cyclone II FPGA in order to generate synthetic image. Synthetic image obtained through this random sampling process on FPGA enhances the randomization of encrypted images which has been evaluated with parameters such as entropy, correlation, histogram, differential, encryption quality and error metric analyses. The encryption and decryption processes were implemented using LabVIEW 2013 platform.

Image encryption is being adopted as a secure strategy to protect the confidential images across the information sharing arena. Scrambling process plays an important role in achieving better confusion during the image encryption. An image encryption scheme based on cyclic shift and chaotic system has been proposed by Wang X-Y et al, 2015 [1]. In that approach, the scrambling process based on logistic map sequence was not efficient to randomize the pixels during image encryption. The randomization resulted in repetitive pixel addresses before reaching the maximal length sequence i.e. total number of image pixels. The lossless reproduction of the secret image during the decryption can only be improved by choosing proper scrambling source during the encryption. This paper addresses some of the issues of that work and proposes an alternate way to perform scrambling with enhanced multiuser improved authentication mechanism.

The volume of image files transmitted over internet is humongous in the present world. Secure transmission of confidential images requires critical attention with the growing demand on new techniques for protecting them. The proposed work aims at developing an image encryption solution with the mix of software and hardware. The technique adopted in this work is based on the confluence of optic system and chaotic-cellular automata dual. Logistic map and opto-coupler have been employed to perform confusion and diffusion of grayscale image. The encryption algorithm was implemented using LabVIEW platform with NI 6212 Multifunction DAQ utilized for interfacing the opto-coupler for random sequence generation.

Present complexity of System on Chip (SoC) design is increasing rapidly in the number of test patterns, huge switching activity and its transition time. This large test data volume is becoming one of the major problems in association with huge switching activity and its corresponding response time. This paper considers the problem of huge test pattern in scan based design. This proposed algorithm is based on reducing test pattern on scan shift in operation. This is achieved by identifying test data transition and equally segmenting the scan based test patterns. Each scan test pattern is considered by its transition and segmented into equal necessary blocks. This finally gives the compressed test patterns in reduced test patterns. Theoretical analysis and experimental results on ISCAS89 shows that the proposed method reduces test pattern by 37% when compared to the traditional approaches.

Steganography has become a predominantly employed information security technique in this modern era. Although the software methods which work on spatial as well as transform domain steganography offer a lot of data hiding options, the steganographic system on hardware platform shows enormous potential by means of multiple advantages such as high speed embedding, specific hardware dependency etc.,. In this paper we have proposed image steganographic architecture which employs data embedding technique in square sized cover image blocks that are stored in internal/external memory of a processor and reconfigurable hardware. The traversal path for information hiding in cover image uses an equisum arrangement of the quad block locations which is used as a Look up Table in our approach. The K-bit message will be hidden in row by row and column by column according to the order suggested by the quad block. The proposed approach is implemented in Cyclone II EP2C20F484C7 FPGA as well as ARM7RISC Processor. The timing analysis, hardware consumption and error metrics after implementation in both platforms have been estimated.

paper discusses about implementation of image steganographic system on Field Programmable Gate Array and the information hiding techniques in various images that are stored in the reconfigurable hardware and external memory. As a spatial domain steganography approach, Linear Feedback Shift Register (LFSR) method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different polynomial expressions have been implemented at the hardware level for hiding the secret data. Altera Cyclone II FPGA has been used to implement stego architecture. Synthesis report, Total time taken for hiding information at hardware level, Performance of reconfigurable hardware under various LFSR address generator schemes, MSE and PSNR issues are also discussed in this paper.

The present study was undertaken to examine the influence of the application of fly ash (FA) into garden soil for Cajanus cajan L. cultivation and on accumulation and translocation of hazardous metals from FA to edible part. Numerous studies have been reported on the growth and yield of agricultural crops under FA stress; however, there is a dearth of studies recommending the safe utilization of fly ash for crop production. Pot experiments were conducted on C. cajan L., a widely cultivating legume in India for its highly nutritious seeds. C. cajan L. were grown in garden soil and amended with varying concentrations of FA in a weight/weight ratio (0%, 25%, 50% and 100%; w/w). Incorporation of fly ash from 25% to 100% in garden soil increases the levels of pH, particle density, porosity and water holding capacity from 3.47% to 26.39%, 3.98% to 26.14%, 37.50% to 147.92% and 163.16% to 318.42%, respectively, than the control while bulk density decrease respectively from 8.94% to 48.89%. Pot experiment found that accumulation and translocation of heavy metals in tested plant depends on the concentration of FA. Addition of FA at lower concentration (25%) had shown positive results in most of the studied parameters of growth and yield (14.23% than control). The experimental results confirmed that lower concentration of FA (25%) is safe for C. cajan cultivation, which not only enhanced the yield of C. cajan L. significantly but also ensured the translocation of heavy metals to edible parts within the critical limits.

This study presents self-checking designs for arithmetic and logic circuits using Field Programmable Gate Array (FPGA) design. At present, we are implementing every circuit using VLSI technology because of its excellent features like low power, less area, wide implementation. Since finding error manually is a tedious process, self-checking method would be most wanted. Self-checking circuits are preferable to Automatic Testing Equipment (ATE) because they demand less hardware, low cost and takes very less test application time. The replica construction and pattern recognition are the two methods presented for self-checking logic gates. Self-checking single-bit full adder, 4-bit adder and 2-bit multiplier circuits are implemented and tested on EP2C20F484C7 Altera Cyclone-II FPGA device using Very High-Speed Integrated Circuits Hardware Description Language (VHDL) script. The test data input samples are applied through input switches and the Error/No Error results are obtained on the 7-segment display device. This study discuss in detail about basic self-checking methods with a experimental way. If the complexity of the circuit increases, the components used and the number of connections between the components increases. As a result, the probability of error occurrence increases for complex designs. But this error occurrence can be avoided to the maximum by using self-checking circuits at different build stages in the complex circuit model. The reliability of any system becomes very important especially in the area of applications such space technology, medical image analysis, military communications, etc.

In the current semiconductor technology evolution, there is a huge demand in designing a low power, high speed adders with less area. As adders are essential components in the data-path of any computer system, adder modules are needed to be enhanced for better performance. One such efficient adder implementation is the Carry Look-Ahead Adder (CLA) which is designed to overcome the latency introduced by rippling effect of carry bits in a conventional Ripple Carry Adder (RCA). Further, the use of this CLA module in the place of Ripple Carry Adder module inside a Carry Select Adder (CSEA) is proposed for increased speed. Also, a novel implementation of adder, making use of the fact that the sum and carry are compliment of one another, except when all the inputs are same is presented. Simulation results show that a 4-bit carry select adder provides a better performance at the cost of power dissipation as 89.211 μW compared with 38.414 μW by a ripple carry adder with 0.12 μm technology processes. In this study, these high speed adders are implemented with the help of the Digital Schematic (DSCH) software tool, Micro wind layout editor tool and Quartus II synthesis software tool. This Quartus II synthesis tool is used for the implementation of adders on Altera EP2C20F484C7 FPGA device. These kinds of adders are further to be extended to build high-speed multipliers which are most important for the applications like digital signal processors, microprocessors, etc.

Field Programmable Gate Array (FPGA) based designs are the most popular trend towards semiconductor technology evolution. The important subsystem in a configurable logic block is a Look-Up Table (LUT) in the FPGA chip. If the power reduction techniques are implemented in the LUTs, there would be an overall very less power while implementing the design in FPGAs. This study mainly focuses on designing LUTs using Programmable Read Only Memory (PROM) circuits. To implement these LUTs, half adder, full adder, half subtract and full subtractor circuits are chosen with PROM concept. Both the conventional CMOS and pseudo-nMOS style architectures are built for the LUTs. Pseudo-nMOS based LUTs are offering less area and low power compared with conventional CMOS approach. A pseudo-nMOS based full adder LUT design produce 564.5 μm 2 layout area, which is less compared with 765.5 μm 2 produced by conventional CMOS full adder LUT. A pseudo-nMOS based full subtractor design produce 1.119 μW dynamic power dissipation, which is less compared with 3.905 μW produced by conventional CMOS full subtractor. Also the design cycle time for FPGAs are much less compared with ASICs. Simulation results are verified using Microwind and Digital Schematic (DSCH) Electronic Computer Aided (CAD) design tools with BSIM4 MOSFET model in 60 nm technology. This study conveys that how the Programmable Read Only Memory (PROM) can act as a Look-Up Table (LUT) within a FPGA architecture. Since engineers are designing the circuits with most care with circuit design, layout design, etc., Application Specific Integrated Circuits (ASIC) are the best at providing low power, high speed and low size at the cost of design cycle time. But with the current semiconductor technology growth, even FPGAs are being manufactured with high speed with more versatile functionalities.

In a current very large-scale integration (VLSI) technology evolution, the reliability issues are the major concern for the improvement of the system. The most fundamental method used for the fault-tolerant system is triple modular redundancy (TMR) in which the majority voter circuit is used to obtain the fault-free response. In this study, the different voter circuits are implemented to analyse the least layout area and lower power dissipation with an application-specific integrated circuits (ASIC) approach using the Microwind layout editor tool. This work is carried out with the eight voting circuits including two proposed methods. The application examples such as a 32-bit adder, an unsigned 8×8 array multiplier, bitwise XOR operation and a 3 × 3 high-pass filter are demonstrated to compare the performance of different voters. The simulation results (power, area, delay) for all the four application examples are obtained and compared.

In this paper, we present design and FPGA implementation of a low power fractional bit encoded (FBE)–spatial modulation (SM) based transmitter for the multiple-input multiple output (MIMO) systems. This Modulation scheme includes the data dependency check before the spatial multiplexing. The proposed data dependency check allows efficient selection of antennas for parallel transmission of data. The Fractional bit encoding is modulus conversion scheme which convert the incoming bit stream to numbers in an arithmetic base, or modulus, that is not a power of 2 .When applied to SM, FBE results in a more versatile system design allowing transmitter to be equipped with an arbitrary number of antennas for a wider range of spectral efficiencies given restrictions on space and power consumption. The synthesis results of the implementation of transmitter on FPGA are included in the paper.