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A novel on-chip test circuit to measure single-event transient (SET) pulse widths has been developed and implemented in IBM 130-nm and 90-nm processes for characterizing logic soft errors. Test measurements with heavy ions and alpha particles show transient widths ranging from 100 ps to over 1 ns, comparable to legitimate logic signals in such technologies. Design options to limit the SET pulse width and hence to mitigate soft errors are evaluated with the test circuit to demonstrate the effectiveness of such design techniques. Index Terms--Alpha particle, combinational logic, guard rings, integrated circuit reliability, pulse width, radiation hardening, single event, single-event transient (SET), soft error, soft error rate (SER).

3D-TCAD simulations in a 130-nm process are used to show the effect of guard rings and guard drains in mitigating charge collection and charge sharing between nodes. Experimental results quantifying the reduction in SET pulse width and the error cross section were obtained with the use of SET pulse width and SET error rate measurement test circuits fabricated in 130-nm and 180-nm processes. Results indicate that guard drains results in 30% lower error cross section compared to guard ring circuits. Index Terms--Collected charge, guard drain, guard ring, pulse width, single event, Single-Event Transient (SET).

Mixed mode simulations and heavy-ion experiments indicate the presence of multi-node charge collection in advanced technologies. For logic circuits, such charge collection may result in concatenation of transients, extending the width of SETs. Mixed-mode simulations of a 4-bit adder circuit indicate that the increase in SET pulse width due to two-node charge collection can be as high as 75%. An analytical model for the increase in the SET width is developed showing the increase in SET width is proportional to the width of the individual transients, the relative delay between charge collection nodes, and the circuit topology. Index Terms--Charge sharing, multi-node charge collection, pulse width, single event, single-event transient (SET).

Single event transients were characterized experimentally in fast logic circuits fabricated in 0.18-[micro]m FDSOI CMOS process using laser-probing techniques. We show that the transient pulse widens as it propagates; the widening is largely eliminated by the body contact. Good agreement is observed between pulsed-laser and heavy ion testing. Index Terms--Floating body, fully depleted silicon-on-insulator, heavy ions, laser irradiation, single-event transients.

Mixed mode TCAD simulations are used to show the effects of guard bands and high density well contacts in maintaining the well potential after a single event strike and thus reduce the width of long transients in a 130-nm CMOS process. Experimental verification of the effectiveness in mitigating long transients was achieved by measuring the distribution of SET pulse widths produced by heavy ions for circuits with isolated contacts and for circuits with guard bands combined with larger contacts in a 130-nm process using an autonomous characterization technique. Heavy-ion test results indicate that controlling the well potential by using guard bands, along with high density well contacts, helps eliminate > 70 % of SETs longer than 1 ns. Index Terms--CMOS, guard band, parasitic bipolar, pulse width, single event transient (SET), single event upset (SEU), soft error, well contact.

Heavy ion-induced single events transients (SETs) in advanced digital circuits are becoming a significant reliability issue for space-based systems. In this work, two experiments are performed on devices designed to look specifically at digital single event transients. Small voltage variations, like those that can be found across an integrated circuit, are shown to affect the digital single event transient response significantly. For technologies with supply voltages near 1 V, these potential variations may result in unexpected vulnerability. Index Terms--Heavy ion, ion radiation effects, single event upset (SEU).

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location. Index Terms--CMOS, combinational logic, DSET, pulse-width, SET, SEU, single event, single event transient, soft error.

Propagation and attenuation of Single Event Transient (SET) pulses in combinational logic circuits are examined. A Miller feedback mechanism that affects the minimum pulse width needed for SET propagation in combinational logic circuits is identified. Analytical models that are commonly employed to predict the combinational Soft Error Rate (SER) of future integrated circuit (IC) technologies do not include this feedback effect. Inclusion of this effect increases the critical charge required for SET propagation through a combinational logic circuit by more than 30%. This feedback phenomenon reduces the estimated SER, which is sensitive to changes in critical charge, by more than 40 %. Index Terms--Critical charge, feedback, Miller effect, SER, SET, single event, soft error.

A novel D-Flip-Flop design using hysteresis to improve single-event hardness with low performance overhead is presented. Layout-aware sensitive area simulations were used to estimate the improvement in cross-section for the proposed hysteresis DFF (HDFF) vs. a standard DFF. A test chip with the standard DFF, HDFF, and the DICE FF was designed in a 28 nm CMOS process and exposed to alpha, neutron, and heavy-ion beams. The HDFF design shows 14\times and 3\times improvements in the alpha and neutron SER, respectively, compared with a standard DFF. [ABSTRACT FROM AUTHOR]

Heavy-ion broad-beam experiments on a 130 nm CMOS technology have shown anomalously-short single-event transient pulse widths. 3D TCAD mixed-mode modeling in 90 nm and 130 nm bulk CMOS has identified a mechanism for simultaneous charge collection on proximal circuit nodes interacting in a way as to truncate, or "quench," a propagated voltage transient, effectively limiting the observed SET pulse widths at high LET. This quenching mechanism is described and analyzed. [ABSTRACT FROM AUTHOR]