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形態: カラー図版あり, Physical characteristics: Original contains color illustrations, Accepted: 2021-06-03, 資料番号: PA2210003000

We investigated the seasonal occurrence and vertical distribution/migration of larval and juvenile northern smoothtongue,Leuroglossus schmidti(Pisces, Bathylagidae), in oceanic areas of the western subarctic Pacific. This species was the most abundant larval fish and one of the most abundant juvenile/adult fish at the study site. Larval recruitment of this species occurred in early March to mid-October. Larvae were found, however, throughout all seasons, suggesting that some had overwintered. The highest abundance (5.8 individuals m–2) of larvae was in summer. During summer and autumn, hatching mainly occurred at 100–150-m depth and larvae migrated toward the surface with growth. Once larvae reached about 20 mm in length, they moved below 100 m, and larger larvae (over 24 mm) exhibited diel vertical migration. The abundance of juveniles integrated through the water column was relatively constant (0.3 individuals m–2) throughout the study period. They were collected from below 300 m during the day, and part of the population (13–38%) swam into the epipelagic layer at night. The information on early stages ofL. schmidtipresented here provides a basis for future investigations of mesopelagic fish ecology in oceanic areas of the western subarctic North Pacific Ocean.

Accepted: 2019-04-04, 資料番号: SA1190018000

形態: カラー図版あり, Physical characteristics: Original contains color illustrations, Accepted: 2018-01-10, 資料番号: PA1810001000

Simulations of magnetic particles are mostly carried out under spatially and temporally static magnetic fields. It is well known that chain-like clusters are formed under these constant fields. However the hysteresis characteristics of particles are therefore often neglected. In this paper, methods to analyze behavior of magnetic particles with hysteresis characteristics under fluctuating fields are proposed. Consideration of hysteresis characteristics and fluctuating fields brings nonlinearity and driving forces to the system in addition to the energy dissipation caused by particle collisions. This research aims to find the foothold of chaotic behavior, which is often found in these systems, among particle clustering. The proposed methods start from the discretization of fields. Collisions and clustering are modeled by treating mechanical contacts, namely, by solving Hertz's contact problem. A symplectic integrator is used for time integration. For the simulation, behavior of 200 magnetic particles under spatially and temporally fluctuating fields were examined. The results imply hysteresis characteristics have a great effect on clustering patterns.

Many applications these days require data processing that is both efficient and reliable. Distributed databases are one way to meet these requirements, but must be updated using distributed transactions. To manage foreign key constraints, secondary indices, and materialized views in distributed environments, read atomic multi-partition (RAMP) transactions demonstrate high efficiency. RAMP transactions achieved high performance distributed transaction processing by relaxing the isolation level. However, the use of fast interconnect to accelerate performance has not yet been considered. This paper proposes the acceleration of RAMP transactions by exploiting remote direct memory access (RDMA) on the InfiniBand interconnect. We first present GET+ and PUT+ operations that accelerate the RAMP transaction by exploiting RDMA write operations. We then present the GET* operation, which further accelerates GET+ operations exploiting RDMA read operations. To evaluate the proposed methods, we implemented a prototype distributed in-memory key-value store in C/C++. The results of the experiments show that compared with RAMP transactions on IP over InfiniBand, GET* and PUT+ achieve a 2.67× performance improvement on the Yahoo! Cloud Serving Benchmark. All of our code is publicly available.

We have investigated a polycrystalline silicon (poly-Si)/chemical vapor deposited titanium nitride (CVD-TiN) stacked structure as a metal gate with a high-k for p-type metal insulator semiconductor field effect transistors (p-MISFETs). A divided-CVD method provided an appropriate effective work function (4.9–5.2 eV) on HfSiON for p-MISFETs. However, the deposition of poly-Si on CVD-TiN films shifted the effective work function to a midgap (~4.6 eV), and Ti, Hf, and Si diffused into poly-Si/CVD-TiN/high-k structures during poly-Si deposition. Then, we found that an increase in the deposition temperature of CVD-TiN films and the insertion of a physical vapor deposited (PVD)-TiN film between the poly-Si and CVD-TiN layers are effective in suppressing these diffusions. In particular, the insertion of the PVD-TiN film provided an appropriate effective work function of 4.9 eV. Therefore, we found that the diffusion control techniques for poly-Si/TiN/high-k stacked structures are highly effective for obtaining the appropriate work function for p-MISFETs.

This paper describes a pixel size shrinkage of an amplified MOS image sensor (AMI). We have developed a new circuit technique to achieve the reduction of a pixel size while realizing vertical two-line mixing and high sensitivity. A 1/4-in format 250-k pixel image sensor was developed using a 0.8-/spl mu/m CMOS process. The difference from the conventional CMOS process is an additional layer of ion-implantation process. The power supply voltages of this imager are 4 and 6 V. The dynamic range of 75 dB, the sensitivity of 1.8 /spl mu/A/Ix, and the smear noise of less than -120 dB have been attained for the pixel size of 7.2 (H)/spl times/5.6 (V) /spl mu/m/sup 2/. Although the measured fixed pattern noise ratio (FPN) of this imager is -55 dB, analysis with a test chip shows that FPN can be improved by 2 dB by adopting a suitable gate length for amplifier and resetting MOSFET, respectively.

A 1/4-inch format 250k pixel amplified MOS image sensor has been developed with the CMOS process. We developed a new circuit technique that uses a 0.8μm design rule to reduce pixel size while attaining vertical two line mixing and high sensitivity. Considering high speed operation and stacking photoconversion layers, we have designed scanner circuits and determined photodiode potential. As a result, a dynamic range of 75 dB and a sensitivity of 1.8μA/lx have been attained for a pixel size of 7.2 (H) × 5.6 (V) μm2. Fixed pattern noise is-55dB for saturation current, additional smear is under 2.5 × 10-6, and lag is under 1% on first field. We also confirmed high-speed operation up to a HDTV data rate.

An image sensor for image processing has been developed. A 1/4-inch 250, 000 pixel amplified MOS imager has been equipped with three independent outputs. The amplified MOS imagers nondestructive read-out operation and three lines of memory built in the sensor make it possible to output the signals of three independent lines simultaneously. By applying this function, a vertical DTL circuit and an FPN suppression of 10.8 dB are realized without an external memory.

We propose a new, large-scale, logic TEG, which is called flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and imitates a logic LSI. We implemented a 10-Mgate FF-RAM using our 65 nm CMOS process. The test results show that it is effortless to detect failure locations and layers by using fail bit maps. Owing to this TEG, we can significantly shorten the development period for advanced CMOS technology.

A 1/4 inch format 250K pixel amplified MOS image sensor has been developed with the CMOS process. We have developed a new circuit technique using a 0.8 /spl mu/m design rule to achieve reduction of pixel size while realizing vertical two line mixing and high sensitivity. Considering high speed operation and stacking photoconversion layers, we have designed scanner circuits and photodiode potential. As a result, a dynamic range of 75 dB and a sensitivity of 1.8 /spl mu/ A/lx have been attained at a pixel size of 7.2(H)/spl times/5.6(V)/spl mu/ m/sup 2/. Also we confirmed high speed operation up to a HDTV data rate. >

Recent progress in solid-state imaging sensor technology has increased the number of pixels. The increased sensor array size inevitably raises the data rate and leads to difficulties in image processing. Most of these difficulties come from the scanning operation in which spatially adjacent vertical pixels are arranged separately in a time axis. To solve the problem, this amplified MOS imager (AMI) outputs three neighboring lines simultaneously. This permits signals from spatially-adjacent vertical pixels to be handled at the same time. Two advantages made it possible to realize this sensor. One is signal charge amplification to prevent SNR degradation, the other is a non-destructive read-out function. The sensor is fabricated with 0.8 /spl mu/m, double-polysilicon double-aluminum CMOS process technology. >