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Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of 80 μW/MHz. The operating frequency of the core reaches 850MHz at 1.2V.

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT DMB baseband receiver SoC is fabricated using 0.13 μm technology and shows successful operation with a 50 mW power dissipation.

This paper describes the implementation of a digital audio effect system-on-a-chip (SoC), which integrates an embedded digital signal processor (DSP) core, audio codec intellectual property, a number of peripheral blocks, and various audio effect algorithms. The audio effect SoC is developed using a software and hardware co-design method. In the design of the SoC, the embedded DSP and some dedicated hardware blocks are developed as a hardware design, while the audio effect algorithms are realized using a software centric method. Most of the audio effect algorithms are implemented using a C code with primitive functions that run on the embedded DSP, while the equalization effect, which requires a large amount of computation, is implemented using a dedicated hardware block with high flexibility. For the optimized implementation of audio effects, we exploit the primitive functions of the embedded DSP compiler, which is a very efficient way to reduce the code size and computation. The audio effect SoC was fabricated using a 0.18 µm CMOS process and evaluated successfully on a real-time test board.

This paper proposes a virtual prototype based on the Aldebaran CPU core developed independently by ETRI. The virtual prototype provides instruction and function profiling functionality for software optimization as well as standard integration emulation interface (SystemC, Verilog, Netlist, etc.) compatibility, and architecture performance analysis for efficient adoption into a system-level design environment.

This paper presents an MPEG-4 video codec, called MoVa, for video coding applications that adopts 3G-324M. We designed MoVa to be optimal by embedding a cost-effective ARM7TDMI core and partitioning it into hardwired blocks and firmware blocks to provide a reasonable tradeoff between computational requirements, power consumption, and programmability. Typical hardwired blocks are motion estimation and motion compensation, discrete cosine transform and quantization, and variable length coding and decoding, while intra refresh, rate control, error resilience, error concealment, etc. are implemented by software. MoVa has a pipeline structure and its operation is performed in four stages at encoding and in three stages at decoding. It meets the requirements of MPEG-4 SP@L2 and can perform either 30 frames/s (fps) of QCIF or SQCIF, or 7.5 fps (in codec mode) to 15 fps (in encode/decode mode) of CIF at a maximum clock rate of 27 MHz for 128 kbps or 144 kbps. MoVa can be applied to many video systems requiring a high bit rate and various video formats, such as videophone, videoconferencing, surveillance, news, and entertainment.

H.265 (HEVC) is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264. However the burden of coding unit (CU) mode decision with rate distortion optimization (RDO) is too costly to implement it with hardware. The key idea of this paper is a novel mode decision architecture to reduce the HW complexity of RDO that is the most effective on an encoder's performance without a noticeable PSNR loss. To shrink the size the Hypernova H.265 encoder uses simplified RDO blocks and shares the transform resources. Its operating clock frequency is 300MHz@60fps on FHD image and BD-BR increase is negligible at 6.02% on hardware aspect. The estimated gate count of its is around 1M.

A partial new design and porting of linux device drivers for a commercial Ethernet chip, a proprietary SD card host controller, and open-source USB host controller for an SoC system called Aldebaran is described. Aldebaran is an SoC including a SPARCv8 based dual issue 13 stage pipeline processor core designed by ETRI. How the drivers work in relation to the kernel core is also explained with the porting procedures. The newly written SD controller driver breaks a single command for a scatterlist into many commands for single buffer to fake the kernel as if the host is processing scatterlist DMA. The three peripherals and the drivers proved to work properly after some bug fixes. For driver porting with initial hardware and software bugs, the engineer needs to know many areas of the kernel like memory management and scheduling as well as each related kernel subsystem and this paper hopes to give a basic idea about the linux driver for those who are not familiar with the topic.

In this demo, a scalable HEVC hardware decoder is demonstrated for various applications including UHD. The architecture includes a control logic for multi-core management and flexible in-loop filters that can process boundaries of picture partitions without a separate in-loop filter unit from the pipeline. Two-level parallel processing approach makes the decoder operate in real-time for high-performance applications. The demonstration on FPGA prototype board shows the efficiency of the proposed scalable architecture achieved by multi-core design. The system is estimated to be able to decode UHD video coded by HEVC in real-time.

There are ongoing efforts to enable development and optimization of hardware and software simultaneously. It is believed that the most effective solution is a system-level virtualization based on a virtual model. This paper proposes a multi-level virtual model of our 32-bit RISC Aldebaran AP with support for several features that further enhances system development efficiency.

Superscalar GP-GPU of SIMT architecture is implemented on VC707 SoC Platform. GP-GPU of current generation is used for processing graphics as well as a general purpose. GP-GPU becomes a credible alternative to general purpose processors for many applications. This paper proposes a design of superscalar GP-GPU of SIMT architecture for parallel processing in the embedded environment. In this paper, the application is processed parallel and its performance is compared using existing multi-core CPU of the embedded environment and the implemented GPU. The performance of parallel processing with the implemented GP-GPU was improved about 65%.

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a onetime, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below 20 . The chip has been fabricated using a 0.8-m n-well complementary metal oxide semiconductor technology with two layers of metalization.

This thesis is intended to design multi thread mobile GPGPU optimized in mobile environment, and to verify an effective thread management method of the multi thread mobile processor. For the verification of the multi thread management method, Lane detection algorithm was implemented to compare nVidia's CUDA Architecture and the designed GPGPU in terms of thread management efficiency. The number of thread is normalized to 48 threads. An implemented Lane Detection Algorithm is composed of Gaussian filter algorithm and Sobel Edge Detection algorithm. As a result, the designed GPGPU's thread efficiency is up to 2 times higher than CUDA's thread efficiency.

Multiple international video standards in the market have been developed successfully for many commercial products. This paper proposes a new multimedia core and multi-core architecture for multi-standard video decoding. The proposed multimedia core is based on the 6-stage pipelined dual issue VLIW+SIMD architecture and efficient instructions for video decoding. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. The multi-core architecture consisting of eight multimedia cores is efficient for parallel decoding of various video compression formats including MPEG-2, MPEG-4, AVS and H.264/AVC.

This paper describes the implementation of the SoC (System-on-Chip) for the virtual keyboard system exploiting computer vision technique. The SoC integrates 32-bit RISC and 16-bit DSP processor core, camera interface, and a number of peripheral blocks necessary for the implementation of virtual keyboard system. This paper presents also the finger motion recognition algorithm embedded in the SoC. The SoC is tailored to the requirements of the virtual keyboard system which are low power consumption, low computation, and system interfaces. The implementation of the SoC introduces some hardware and software features to meet these requirements. The cal-DMA is the special DMA which is able to calculate simple arithmetic operation with normal DMA function and reduces the computation of the algorithm performed in the SoC. The SoC was fabricated by using 0.18 um CMOS process and it was evaluated successfully on the real-time test board.

In this paper, a hardware design of an H.264/SVC video decoder is presented. Large size inter-coded pictures in a high frame rate require a high external memory bandwidth in decoding process. Inter-layer predictions of SVC further increase data transfer from or to an external memory. A cache-based motion compensation to sufficiently reduce overhead cycles for external SDRAM access and the bandwidth requirement is proposed. Much variation of macroblock processing cycles for CABAC decoding is another obstacle to design a SVC video decoder with macroblock based pipelining scheme. A frame level delaying method is proposed to remove the cycle variations, so that the decoder works with a steady throughput. The proposed SVC decoder shows HD1080p 60fps of decoding capability operating at 166.7MHz.

As mobile computing technologies are developed, multi-core processors are introduced to the mobile devices. Multi-core, multi-thread systems require parallel processing software. In this paper, we propose an effective method of tile based rendering for a multi-core based GP-GPU environment.[1] A tile based rendering technique is adopted to reduce an amount of data transfer between the processor and external memory for resource-limited mobile environment.[2] The proposed algorithm is parallelized for multi-core environment with Global Scratch Counters. Tiling performance is also improved using hierarchical tiling technique.

Application-specific instruction processor is a new design methodology to develop optimized processors for specific applications. This paper proposes a new application-specific instruction processor and compiler for multi-standard video decoding. They are based on the 6-stage pipelined dual issue VLIW+SIMD architecture, efficient instructions for multi-standard video decoding, and compiler mapping techniques such as CKF(compiler known function) and inline assembly. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. Compared to the existing ARM processor, the proposed architecture and compiler result in about 20% improvement in video decoding in terms of total cycles as well as smaller hardware complexity.

This paper presents an implementation of portable sound effector using the tiny packaged sound effect module which includes implemented sound effects, sound effect SoC, and EEPROM. The SoC integrates the embedded DSP core, an audio codec, some peripheral blocks, and various sound effect algorithms where cost savings made by reducing the chip count and size. In the implementation of sound effect algorithms, we employ the primitive functions of the DSP compiler, which provide an efficient way to optimize the compiled code. This portable sound effector is developed as an all-in-one product for the low cost and high portability.

In frame memory recompression, decompression latency consists of two components, i.e., memory access cycles for compressed data fetch, and decompression time. Compared to most earlier works which mainly focused on the compression ratio and, therefore, only reducing memory access cycles, this paper proposes a low-latency variable-length coding method called non-zero bit selection scheme (NBS). The proposed NBS enables highly parallel decompression achieving a three-cycle decompression for an 8×8 block, compared to previous methods requiring as many as twelve clock cycles for the case of exponential Golomb code. It is notable that the proposed NBS scheme has achieved this without deterioration of the compression ratio. Experimental result on a number of full HD videos shows that the compression ratio of the proposed method is at least not worse than that obtained with the exponential Golomb code on the average, while reducing the decompression time to 25% compared to the exponential Golomb code.

This paper describes the implementation of digital audio effect SoC (System on Chip) which integrates the embedded DSP core, audio codec IP, a number of peripheral blocks and various audio effect algorithms. The audio effect SoC is developed by a software and hardware co-design method. The embedded DSP and some dedicated hardware blocks are developed as a hardware design while the audio effect algorithms are realized by a software centric way. In the implementation of audio effects, we employ the primitive functions of the embedded DSP compiler which provide the efficient way to implement the audio effect algorithms. Most of the algorithms are implemented by C language with the primitive functions and they are run on the embedded DSP while the equalizer which requires a large amount of computing power is implemented by the dedicated hardware block with high flexibility. The audio effect SoC was fabricated by using 0.18 um CMOS process and it was evaluated successfully on the real-time test board.

The advancement of process technology enables the integration of multiple cores featuring the parallel processing with low operating energy and efficient resource utilization in embedded media processors. We propose mobile media processor SoC integrating RISC core and quad-core data processing engines with shared array of memory modules. The implicative dynamic parallel programming model dynamically distributes the programmer-specified parallelizable functions into multiple cores. The experimental result with parallelized audio processing algorithm on FPGA platform shows the effectiveness of the proposed processor SoC.

The TETRA (terrestrial trunked radio) speech codec is mandatory for all TETRA mobiles and networks. This paper presents the cost-effective implementation of the TETRA speech codec using the primitive functions of the compiler for the 16 bit fixed-point eDSP (embedded DSP), which was developed by ETRI for the purpose of use in various SoCs. Generally, the simple implementation of the speech codec is using the cross compiling but it probably does not operate in real-time. The more optimized implementation is the fully hand-written assembly code but this approach is very time consuming compared to the cross compiling methods. More efficient way is using the cross compiling with the primitive functions. In this way, we convert the basic arithmetic function in TETRA speech codec into the compact one using primitive functions of the compiler in order to reduce the computation where we used the in-house compiler of the eDSP. Employing the primitive functions makes it possible to obtain the optimized assembly code because our compiler is fully customized to the eDSP. The number of cycles can be reduced into the 8 % of the complexity of the simple cross compiling version. We also describe the comparison among some implementation approaches and their results.

In this paper, the method to generate and use a lookup table from a variable length codes (VLC) table, the so-called N-bit code table is described. The original VLC table is stored in a tree structure, and then transformed to the N-bit code table through the process presented on the paper. The proposed method can be applied to any VLC table regardless of the video formats. The implementation of the method accelerating a general RISC reduces the number of memory access from 48.3% up to 95.17% compared to the RISC without the implementation when applied to VLC tables of H.264/AVC.

This paper proposes a new application specific processor and compiler targeting H.264 inverse transform and inverse quantization. They are based on the 6-stage pipelined dual issue VLIW+SIMD architecture, efficient instructions for inverse transform and inverse quantization, and compiler mapping techniques such as CKF (compiler known function), inline assembly and CGD (code generator description). The proposed architecture whose approximate gate count is about 130 K runs at 100 MHz. Compared to the ARM1020E processor, the proposed architecture and compiler result in about 20~46% improvement in terms of total cycles as well as smaller hardware complexity.

This paper describes a system on chip (SoC) implementation of terrestrial digital multimedia broadcasting (T-DMB) receiver which integrates RF tuner, analog to digital converter (ADC), baseband processor, and multimedia processor in single silicon wafer. The pseudo-SRAM (PSRAM) and SDRAM are doubly stacked with method of silicon in package (SIP). A low-IF RF tuner and a 10 bits pipelined ADC is used in this work as IP cores. Baseband processor contains Eureka-147 digital audio broadcasting (DAB) modem, MPEG1-Layer2 decoder, and outer decoder for T-DMB. Multimedia processor is consists of 32 bit embedded micro processor, 24 bit fixed-point DSP, and H.264/AVC hardware core. The T-DMB SoC was fabricated by using 0.13 um 1 poly 8 metal (1P8M) CMOS process and it gives successful performance of 159.2 mW total power dissipation including PSRAM and SDRAM at supply voltages of 1.2 V, 2.5 V for core and I/O respectively.

In this paper, we implement the configurable processor for CAVLC function module of a H.264/AVC baseline profile decoder as the starting point to implement the H.264/AVC decoder system in a multiprocessor platform. The requirements of the implementations are the low-power processor and speed optimized algorithms tailored to the processor architecture. An arithmetic formula mapping method for fast CAVLC algorithms and a dual-issue VLIW processor architecture with custom instructions are proposed. The experiment results show that the synthesized processor has about 75 K gates and can carry out the decoding of 30-fps CIF (352x288 pixels) images around 120 Mega cycles.

In this paper, we present the dedicated hardware H.264/AVC video encoder with reducing memory access scheme. This engine performs 30 frame/sec with D1(720x480) resolution at 40 MHz. It has dedicated hardware architecture, memory reducing scheme, double buffering structure to decrease memory bus bandwidth and early decision mode for fast estimation at motion estimation. It supports to H.264/AVC base profile level 3. Its gate count is 427K and can be applied various application, such as, IPTV, surveillance system and portable multimedia devices to need low frequency and low power.