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This paper introduces design and FPGA implementation of sound encryption system based on a fractional-order chaotic system. Also, it presents the FPGA implementation of Tang, Yalcin, and Ozoǧuz fractional order chaotic systems. The Grunwald-Letnikov (GL) definition is used to generalize the investigated systems into the fractional-order domain. Also, the variation of parameters for each system is investigated against the window size of the GL definition. Xilinx ISE 14.5 is used to simulate the proposed design. Also, some hardware reduction techniques are applied to decrease hardware utilization and increase throughput. Moreover, Yalcin system is employed as a chaotic generator in a speech encryption algorithm. Security analysis techniques are presented to show the robustness of the proposed algorithm. They include basic perceptual and statistical aspects, the NIST tests, key space analysis, mean square error (MSE) and key sensitivity. Statistical analyses including correlation, histogram, spectrogram, and entropy analysis are presented. The system is implemented on Artix-7 FPGA with one clock latency. Finally, experimental results are illustrated.

Chaotic systems have remarkable importance in capturing some complex features of the physical process. Recently, fractional calculus becomes a vigorous tool in characterizing the dynamics of complex systems. The fractional-order chaotic systems increase the chaotic behavior in new dimensions and add extra degrees of freedom, which increase system controllability. In this chapter, FPGA implementation of different integer and fractional-order chaotic systems is presented. The investigated integer-order systems include Chua double scroll chaotic system and the modified Chua N-scroll chaotic system. The investigated fractional-order systems include Chua, Yalcin et al., Ozuogos et al., and Tang et al., chaotic systems. These systems are implemented and simulated based on the Grunwald–Letnikov (GL) definition with different window sizes. The parameters effect, along with different GL window sizes is investigated where some interesting chaotic behaviors are obtained. The proposed FPGA implementation utilizes fewer resources and has high throughput. Experimental results are provided on a digital oscilloscope.

This paper introduces FPGA implementation of fractional order double scrolls chaotic system based on Chua circuit. Grunwald-Letnikov's (GL) definition is used to generalize the chaotic system equations into the fractional-order domain. Xilinx ISE 14.5 is used to simulate the proposed design and Artix-7 XC7A100T FPGA is used for system realization. Experimental results are presented on digital oscilloscope and the error between theoretical and experimental results is calculated. Also, various interesting attractors are obtained with respect to different parameters values and window sizes. Some techniques have been employed to increase the throughput to 7.685 Gbit/Sec with 96-bits overall output.