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Modern condition monitoring and industrial fault prediction have advanced to include intelligent techniques, aiming to improve reliability, productivity, and safety. The integration of ultrasonic signal processing with various machine learning (ML) models can significantly enhance the efficiency of industrial fault diagnosis. In this paper, ultrasonic data are analyzed and applied to ensemble ML algorithms. Four methods for reducing dimensionality are employed to illustrate differences among acoustic faults. Different features in the time domain are extracted, and predictive ensemble models including a gradient boosting classifier (GB), stacking classifier (Stacking), voting classifier (Voting), Adaboost, Logit boost (Logit), and bagging classifier (Bagging) are implemented. To assess the model’s performance on new data during experiments, k-fold cross-validation (CV) was employed. Based on the designed workflow, GB demonstrated the highest performance, with less variation over 5 cross-folds. Finally, the real-time capability of the model was evaluated by deployment on an ARM Cortex-M4F microcontroller (MCU).

Ultrasonic diagnostics is the earliest way to predict industrial faults. Usually, a contact microphone is employed for detection, but the recording will be contaminated with noise. In this paper, a dataset that contains 10 main faults of pipelines and motors is analyzed from which 30 different features in the time and frequency domains are extracted. Afterward, for dimensionality reduction, principal component analysis (PCA), linear discriminant analysis (LDA), and t-distributed stochastic neighbor embedding (t-SNE) are performed. In the subsequent phase, recursive feature elimination (RFE) is employed as a strategic method to analyze and select the most relevant features for the classifiers. Next, predictive models consisting of k-Nearest Neighbor (KNN), Logistic Regression (LR), Decision Tree (DT), Gaussian Naive Bayes (GNB), and Support Vector Machine (SVM) are employed. Then, in order to solve the classification problem, a stacking classifier based on a meta-classifier which combines multiple classification models is introduced. Furthermore, the k-fold cross-validation technique is employed to assess the effectiveness of the model in handling new data for the evaluation of experimental results in ultrasonic fault detection. With the proposed method, the accuracy is around 5% higher over five cross folds with the least amount of variation. The timing evaluation of the meta model on the 64 MHz Cortex M4 microcontroller unit (MCU) revealed an execution time of 11 ms, indicating it could be a promising solution for real-time monitoring

The quality factor of microelectromechanical resonators is a crucial performance metric and has thus been the subject of numerous studies aimed at maximizing its value by minimizing the anchor loss. This work presents a study on the effect of elastic wave reflectors on the quality factor of MEMS clamped–clamped flexural beam resonators. The elastic wave reflectors are a series of holes created by trenches in the silicon substrate of the resonators. In this regard, four different shapes of arrayed holes are considered, i.e., two sizes of squares and two half circles with different directions are positioned in proximity to the anchors. The impact of these shapes on the quality factor is examined through both numerical simulations and experimental analysis. A 2D in-plane wave propagation model with a low-reflecting fixed boundary condition was used in the numerical simulation to predict the behavior, and the MEMS resonator prototypes were fabricated using a commercially available micro-fabrication process to validate the findings. Notably, the research identifies that half-circle-shaped holes with their curved sides facing the anchors yield the most promising results. With these reflectors, the quality factor of the resonator is increased by a factor of 1.70 X in air or 1.72 X in vacuum.

A deep neural network architecture for the automatic sizing of analog circuit components is proposed, with a focus on radio frequency (RF) applications in the 2 to 5 GHz region. It addresses the challenges of the typically small number of examples for network training and the existence of multiple solutions, of which impractical values for integrated circuit implementation. We address these issues by restricting the learning to one component size at a time, thanks to a cascade of dedicated shallow neural networks (SNN), where each network constrains the prediction of the next ones. Moreover, the SNNs are individually tuned by a genetic algorithm for the prediction order and accuracy. This reduction of the solution space at each step allows the use of small training sets, and the introduced constraints between SNNs handle component interdependencies. The method is successfully validated on three different types of RF microcircuits: a low-noise amplifier (LNA), a voltage-controlled oscillator (VCO), and a mixer, using 180 nm and 130 nm CMOS implementations. All the predictions were within 5 % of the true values, both at the component and performance levels, and all the responses were obtained in less than 5 s, after 4 to 47 min. training on a regular PC station. The obtained results show that the proposed method is fast and applicable to arbitrary analog circuit topologies, with no need to retrain the developed neural network for each new set of desired circuit performances.

A wideband cascaded receiver and a stacked receiver using an improved clock strategy are proposed to support the software-defined radio (SDR). The improved clock strategy reduces the number of mixer switches and the number of LO clock paths required to drive the mixer switches. This reduces the dynamic power consumption. The cascaded receiver includes an inverter-based low-noise transconductance amplifier (LNTA) using a feed-forward technique to enhance the noise performance; a passive mixer; and an inverter-based transimpedance amplifier (TIA). The stacked receiver architecture is used to reduce the power consumption by sharing the current between the LNTA and the TIA from a single supply. It utilizes a wideband LNTA with a capacitor cross-coupled (CCC) common-gate (CG) topology, a passive mixer to convert the RF current to an IF current, an active inductor (AI) and a 1/f noise-cancellation (NC) technique to improve the noise performance, and a TIA to convert the IF current to an IF voltage at the output. Both cascaded and stacked receivers are simulated in 22 nm CMOS technology. The cascaded receiver achieves a conversion-gain from 26 dB to 36 dB, a double-sideband noise-figure (NFDSB) from 1.4 dB to 3.9 dB, S11<−10 dB and an IIP3 from −7.5 dBm to −10.5 dBm, over the RF operating band from 0.4 GHz to 12 GHz. The stacked receiver achieves a conversion-gain from 34.5 dB to 36 dB, a NFDSB from 4.6 dB to 6.2 dB, S11<−10 dB, and an IIP3 from −21 dBm to −17.5 dBm, over the RF operating band from 2.2 GHz to 3.2 GHz. The cascaded receiver consumes 11 m from a 1 V supply voltage, while the stacked receiver consumes 2.4 m from a 1.2 V supply voltage.