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Static Random Access Memory (SRAM) is volatile and uses latching flip-flops to store each bit. To make SRAM work as non-volatile memory (NVM), memristor-based SRAM is a feasible choice mainly due to its high-speed operation and low power consumption. In this paper, the operational characteristics of 4T2M SRAM have been studied based on three different memristor models developed by Biolek et al. (2009), Joglekar and Wolf 2009, and Prodromakis et al. (2011), and comparative performance analysis has been made to assess its adaption to NVM. These three different models are compared in terms of delay, power consumption, and static noise margin. From the simulation, it has been observed that Biolek 4T2M SRAM produces better performance in write delay calculation scoring 0.873 ns when '0' is written and 0.166 ns when '1' is written. This model also provided a low power consumption value compared to other models. However, ternary plot analysis finds that Prodromakis is performing in average better in all positive traits. All the simulations are done in LTSpice and the transistor uses TSMC 180 nm CMOS technology. [ABSTRACT FROM AUTHOR]

Abstract In this work, multi-level storage in the via RRAM has been first time reported and demonstrated with the standard FinFET CMOS logic process. Multi-level states in via RRAM are achieved by controlling the current compliance during set operations. The new current compliance setting circuits are proposed to ensure stable resistance control when one considers cells under the process variation effect. The improved stability and tightened distributions on its multi-level states on via RRAM have been successfully demonstrated.

Neuromorphic computing offers a promising solution to overcome the von Neumann bottleneck, where the separation between the memory and the processor poses increasing limitations of latency and power consumption. For this purpose, a device with analog switching for weight update is necessary to implement neuromorphic applications. In the diversity of emerging devices postulated as synaptic elements in neural networks, RRAM emerges as a standout candidate for its ability to tune its resistance. The learning accuracy of a neural network is directly related to the linearity and symmetry of the weight update behavior of the synaptic element. However, it is challenging to obtain such a linear and symmetrical behavior with RRAM devices. Thus, extensive research is currently devoted at different levels, from material to device engineering, to improve the linearity and symmetry of the conductance update of RRAM devices. In this work, the experimental results based on different programming pulse conditions of RRAM devices are presented, considering both voltage and current pulses. Their suitability for application as analog RRAM-based synaptic devices for neuromorphic computing is analyzed by computing an asymmetric nonlinearity factor. [ABSTRACT FROM AUTHOR]

Physical Unclonable Functions (PUFs) have been widely considered an attractive security primitive. They use the deviations in the fabrication process to have unique responses from each device. Due to their nature, they serve as a DNA-like identity of the device. But PUFs have also been targeted for attacks. It has been proven that machine learning (ML) can be used to effectively model a PUF design and predict its behavior, leading to leakage of the internal secrets. To combat such attacks, several designs have been proposed to make it harder to model PUFs. One design direction is to use Non-Volatile Memory (NVM) as the building block of the PUF. NVM typically are multilevel cells, i.e, they have several internal states, which makes it harder to model them. However, the current state of the art of NVM-based PUFs is limited to 'weak PUFs', i.e., the number of outputs grows only linearly with the number of inputs, which limits the number of possible secret values that can be stored using the PUF. To overcome this limitation, in this work we design the Arbiter Non-Volatile PUF (ANV-PUF) that is exponential in the number of inputs and that is resilient against ML-based modeling. The concept is based on the famous delay-based Arbiter PUF (which is not resilient against modeling attacks) while using NVM as a building block instead of switches. Hence, we replace the switch delays (which are easy to model via ML) with the multi-level property of NVM (which is hard to model via ML). Consequently, our design has the exponential output characteristics of the Arbiter PUF and the resilience against attacks from the NVM-based PUFs. Our results show that the resilience to ML modeling, uniqueness, and uniformity are all in the ideal range of 50%. Thus, in contrast to the state-of-the-art, ANV-PUF is able to be resilient to attacks, while having an exponential number of outputs. [ABSTRACT FROM AUTHOR]

DRAM-NVM-based hybrid memory opens up a varied range of power-performance-area operational configurations through page migration between the high-performance DRAM and the reliable NVM. The amalgamation of two technologies requires various modifications for the existing monolithic DRAM-based systems. This paper summarizes the current research work in the areas of data placement and page migration in hybrid memories. The challenges and design solutions from a range of NVMs-PCM, STT-RAM, ReRAM is presented. This paper also identifies several research challenges in these areas. [ABSTRACT FROM AUTHOR]

The AI and IoT era requires software and hardware capable of efficiently processing massive amounts data quickly and at a low cost. However, there are bottlenecks in existing Von Neumann structures, including the difference in the operating speed of current-generation DRAM and Flash memory systems, the large voltage required to erase the charge of nonvolatile memory cells, and the limitations of scaled-down systems. Ferroelectric materials are one exciting means of breaking away from this structure, as Hf-based ferroelectric materials have a low operating voltage, excellent data retention qualities, and show fast switching speed, and can be used as non-volatile memory (NVM) if polarization characteristics are utilized. Moreover, adjusting their conductance enables diverse computing architectures, such as neuromorphic computing with analog characteristics or 'logic-in-memory' computing with digital characteristics, through high integration. Several types of ferroelectric memories, including two-terminal-based FTJs, three-terminal-based FeFETs using electric field effect, and FeRAMs using ferroelectric materials as capacitors, are currently being studied. In this review paper, we include these devices, as well as a Fe-diode with high on/off ratio properties, which has a similar structure to the FTJs but operate with the Schottky barrier modulation. After reviewing the operating principles and features of each structure, we conclude with a summary of recent applications that have incorporated them. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM)-based convolutional neural networks (NvCNNs) have received widespread attention as a promising solution for hardware edge intelligence. However, there still exist many challenges in the resourceconstrained conditions, such as the limitations of the hardware precision and cost and, especially, the large overhead of the analog-to-digital converters (ADCs). In this study, we systematically analyze the performance of NvCNNs and the hardware restrictions with quantization in both weight and activation and propose the corresponding requirements of NVM devices and peripheral circuits for multiply-accumulate (MAC) units. In addition, we put forward an in situ sparsity-aware processing method that exploits the sparsity of the network and the device array characteristics to further improve the energy efficiency of quantized NvCNNs. Our results suggest that the 4-bit-weight and 3-bit-activation (W4A3) design demonstrates the optimal compromise between the network performance and hardware overhead, achieving 98.82% accuracy for the Modified National Institute of Standards and Technology database (MNIST) classification task. Moreover, higher-precision designs will claim more restrictive requirements for hardware nonidealities including the variations of NVM devices and the nonlinearities of the converters. Moreover, the sparsity-aware processing method can obtain 79%/53% ADC energy reduction and 2.98×/1.15× energy efficiency improvement based on the W8A8/W4A3 quantization design with an array size of 128 × 128. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM)-based computing-in-memory (nvCIM) is a promising candidate for artificial intelligence (AI) edge devices to overcome the latency and energy consumption imposed by the movement of data between memory and processors under the von Neumann architecture. This paper explores the background and basic approaches to nvCIM implementation, including input methodologies, weight formation and placement, and readout and quantization methods. This paper outlines the major challenges in the further development of nvCIM macros and reviews trends in recent silicon-verified devices.

In this article, we analyze Android applications’ memory reference behaviors, and observe that smartphone memory accesses are different from traditional computer systems with respect to the following five aspects: 1) A limited number of hot pages account for a majority of memory writes, and these hot pages have similar logical addresses regardless of application types; 2) The identities of these hot pages are shared library, linker, and stack regions; 3) The memory access behaviors of hot pages do not change significantly as time progresses even after applications finish their launching; 4) The skewness of memory write accesses in Android is extremely stronger than that of desktop systems; 5) In predicting re-reference likelihood of hot pages, temporal locality is better than reference frequency. Based on these observations, we present a new smartphone memory management scheme for DRAM-NVM hybrid memory. Adopting NVM is effective in power-saving of smartphones, but NVM has weaknesses in write operations. Thus, we aim to identify write-intensive pages and place them on DRAM. Unlike previous studies, we prevent migration of pages between DRAM and NVM, which eliminates unnecessary NVM write traffic that accounts for 32-42% of total write traffic. By judiciously managing the admission of hot pages in DRAM, our scheme reduces the write traffic to NVM by 42% on average without performance degradations.

Recently, NVM (non-volatile memory) has advanced as a fast storage medium, and traditional memory management systems designed for HDD storage should be reconsidered. In this article, we revisit the page sizing problem in NVM storage, specially focusing on virtualized systems. The page sizing problem has not caught attention in traditional systems because of the two reasons. First, the memory performance is not sensitive to the page size when HDD is adopted as storage. We show that this is not the case in NVM storage by analyzing the TLB miss rate and the page fault rate, which have trade-off relations with respect to the page size. Second, changing the page size in traditional systems is not easy as it accompanies significant overhead. However, due to the widespread adoption of virtualized systems, the page sizing problem becomes feasible for virtual machines, which are generated for executing specific workloads with fixed hardware resources. In this article, we design a page size model that accurately estimates the TLB miss rate and the page fault rate for NVM storage. We then present a method that has the ability of estimating the memory access time as the page size is varied, which can guide a suitable page size for given environments. By considering workload characteristics with given memory and storage resources, we show that the memory performance of virtualized systems can be improved by 38.4% when our model is adopted.

Ge-rich GST alloys are the most promising materials for phase-change memory (PCM) to fulfill the soldering compliance and the tough data retention requirements of automotive applications. Significant efforts have been made to engineer those materials and optimize their integration inside the fabrication process of PCM. In this perspective, the physical characterization of the device and the material is instrumental in understanding the underlying physics, improving the process, and optimizing the interactions between the device, the process, and the material itself. Especially, microscopic investigations have gathered increasing interest, giving detailed descriptions of local material modulations that have a crucial role in cell programming and reliability performances. In this work, a deep analysis of Ge-rich GST microscopic alloy evolution during the integration process has been performed, exploiting analysis by EELS with TEM supported by a novel statistical data post-processing method. The new proposed statistical-based methodology also introduces new simple metrics for elemental compositional evaluations that have been exploited for process engineering.

Edge storage stores the data directly at the data collection point, and does not need to transmit the collected data to the storage central server through the network. It is a critical technology that supports applications such as edge computing and 5G network applications, with lower network communication overhead, lower interaction delay and lower bandwidth cost. However, with the explosion of data and higher real-time requirements, the traditional Internet of Things (IoT) storage architecture cannot meet the requirements of low latency and large capacity. Non-volatile memory (NVM) presents new possibilities regarding this aspect. This paper classifies the different storage architectures based on NVM and compares the system goals, architectures, features, and limitations to explore new research opportunities. Moreover, the existing solutions to reduce the write latency and energy consumption and increase the lifetime of NVM IoT storage devices are analyzed. Furthermore, we discuss the security and privacy issues of IoT devices and compare the mainstream solutions. Finally, we present the opportunities and challenges of building IoT storage systems based on NVM. [ABSTRACT FROM AUTHOR]

Emerging non-volatile memory (NVM) technologies are of dynamic random access memory (DRAM)-like, high capacity, and low cost, at the expense of slower bandwidth and higher read/write latency compared to DRAM. Typically, NVM finds its primary application in serving as an extension of conventional DRAM to create hybrid memory systems tailored to non-uniform memory access (NUMA) architectures. This strategic integration offers the potential for high performance, enhanced capacity efficiency, and a favorable balance of cost considerations. Traditional NUMA memory management policies distribute data uniformly across both DRAM and NVM, overlooking the inherent performance gap between these heterogeneous memory systems. This challenge becomes particularly pronounced when provisioning resources for deep learning and big data applications in hybrid memory systems. To tackle the performance issues in the hybrid memory systems, we propose and develop a unified memory system, UniRedl, which automatically optimizes data migration between DRAM and NVM based on data access patterns and computation graphs of applications. To improve application performance, we provide a new memory allocation strategy named HiLowAlloc. We further design two data migration strategies in UniRedl, Idle Migration and Dynamic Migration, for management of hybrid memory systems. Specifically, Idle Migration aims to manage data placed in DRAM, while Dynamic Migration manages data saved in NVM. The experimental results demonstrate that on average UniRedl improves application performance by 33.2%, 20.6%, 19.0%, and 17.5% compared to the traditional NUMA, NUMA with anb, BMPM, and OIM, respectively. It also achieves 52.0%, 34.3%, 30.6%, 22.1% on average improvement in data locality against the state-of-the-art solutions. • UniRedl abstracts DRAM and NVM across the whole cluster into a unified memory space. • UniRedl features a new memory allocation strategy named HiLowAlloc. • UniRedl offers two data migration strategies, Idle Migration and Dynamic Migration. [ABSTRACT FROM AUTHOR]

Distributed storage systems and computing systems are the foundation for constructing big data processing systems.High availability of the system is the cornerstone of any distributed system.High-availability technologies generally rely on consensus protocols.The classic non-Byzantine distributed consensus protocol was discussed,as well as the RDMA communication protocol and NVM storage media under the development of new technologies to achieve higher performance high availability systems by combining them.The consensus protocol to make the better use of the features of RDMA and NVM was modified.The implemented system effectively improves the performance of the protocol while ensuring the consistency and availability of the system data.Experiments show that the system implemented in this paper can achieve 40% performance improvement compared to existing systems.

QoS-aware big data analysis is critical in Information-Centric Internet of Things (IC-IoT) system to support various applications like smart city, smart grid, smart health, intelligent transportation systems, and so on. The employment of non-volatile memory (NVM) in cloud or edge system provides good opportunity to improve quality of data analysis tasks. However, we have to face the data recovery problem led by NVM failure due to the limited write endurance. In this paper, we investigate the data recovery problem for QoS guarantee and system robustness, followed by proposing a rarity-aware data recovery algorithm. The core idea is to establish the rarity indicator to evaluate the replica distribution and service requirement comprehensively. With this idea, we give the lost replicas with distinguishing priority and eliminate the unnecessary replicas. Then, the data replicas are recovered stage by stage to guarantee QoS and provide system robustness. From our extensive experiments and simulations, it is shown that the proposed algorithm has significant performance improvement on QoS and robustness than the traditional direct data recovery method. Besides, the algorithm gives an acceptable data recovery time.

Byte-addressable, non-volatile memory (NVM) presents an opportunity to rethink the entire system stack. We present Twizzler, an operating system redesign for this near-future. Twizzler removes the kernel from the I/O path, provides programs with memory-style access to persistent data using small (64 bit), object-relative cross-object pointers, and enables simple and efficient long-term sharing of data both between applications and between runs of an application. Twizzler provides a clean-slate programming model for persistent data, realizing the vision of Unix in a world of persistent RAM. We show that Twizzler is simpler, more extensible, and more secure than existing I/O models and implementations by building software for Twizzler and evaluating it on NVM DIMMs. Most persistent pointer operations in Twizzler impose less than 0.5 ns added latency. Twizzler operations are up to 13× faster than Unix, and SQLite queries are up to 4.2× faster than on PMDK. YCSB workloads ran 1.1-2.9× faster on Twizzler than on native and NVM-optimized SQLite backends. [ABSTRACT FROM AUTHOR]

A novel hybrid antiferroelectric (AFE)-based charge trap (CT) memory is reported focusing on an amplified tunnel oxide field (ETO) via the dynamic of an AFE hysteresis dipole switching. The role of dynamic permittivity increase and the saturated polarization at the instant of the write operation are explored for enhanced ETO. The hybrid CT concept is studied by benchmarking the controlled properties of the HfO2 CT layer via the Si elemental doping in order to stabilize the linear dielectric (DE), ferroelectric (FE), or AFE response. The Si-doped HfO2 (HSO) with AFE stabilized phase shows the largest memory window (4.5 V) compared to the DE- or FE-based CT layers. The dynamic AFE dipole switching enables a maximized ETO at the instant of switching such that a high-speed and low-power CT memory is realized. The role of the tailored hysteresis shape on the ETO magnitude is studied for different Si contents and benchmarked to the Zr-doped hafnium oxide (HZO). The AFE CT multilevel coding as 1–3 bit/cell, the role of the pass voltage disturb, and a mini-NAND array operation are demonstrated. The global variability and area scalability of the HSO CT devices are studied to indicate the effect of Si content distribution and the area dependence of the AFE film variability. AFE CT devices are characterized for a switching speed (< 1 μs), ten-year data retention, and 105 endurance. Moreover, the improved CT characteristics by the AFE dipole switching are explored for enhanced long-term potentiation and depression of a synaptic device. [ABSTRACT FROM AUTHOR]

Noncompaction of the ventricular myocardium (NVM), the third most diagnosed cardiomyopathy, is characterized by prominent trabeculae and intratrabecular recesses. However, the genetic etiology of 40%-60% of NVM cases remains unknown. Here, we identify two infants with NVM, in a nonconsanguineous family, with a typical clinical presentation of persistent bradycardia since the prenatal period. A homozygous missense variant (R223L) of RCAN family member 3 (RCAN3) is detected in both infants using whole-exome sequencing. In the zebrafish model, marked cardiac dysfunction is detected in rcan3 deficiency (MO-rcan3 ATG -injected) and rcan -/- embryos. Developmental dysplasia of both endocardial and myocardial layers is also detected in rcan3-deficient embryos. RCAN3 R223L variant mRNAs can not rescue heart defects caused by rcan3 knockdown or knockout; however, hRCAN3 mRNAs rescue these phenotypes. RNA-seq experiments show that several genes involved in cardiomyopathies are significantly regulated through multiple signaling pathways in the rcan3-knockdown zebrafish model. In human cardiomyocytes, RCAN3 deficiency results in reduced proliferation and increased apoptosis, together with an abnormal mitochondrial ultrastructure. Thus, we suggest that RCAN3 is a susceptibility gene for cardiomyopathies, especially NVM and that the R223L mutation is a potential loss-of-function variant., Competing Interests: Conflict of interest The authors declare no conflicts of interest., (Copyright © 2024 Institute of Genetics and Developmental Biology, Chinese Academy of Sciences, and Genetics Society of China. Published by Elsevier Ltd. All rights reserved.)

In order to protect the data during system crash, traditional DRAM–DISK architecture file systems (e.g., EXT4) need to synchronize the dirty metadata and data from the memory to disk. At the same time, the disk synchronization may break the consistency of file system upon a crash, so traditional file systems use some mechanisms to guarantee the file system consistency when the dirty metadata and data is synchronized onto persistent storage devices (e.g., HDD and SSD). Journaling is a consistency mechanism widely used by file systems. We observe that the overhead of periodic disk synchronization and journaling is high. Emerging non-volatile memories (NVMs) can be potentially utilized to reduce these overheads. In this paper, we present hybrid architecture for storage file system (HasFS), a file system designed for the DRAM–NVM–DISK architecture. HasFS extends the main memory with NVM and considers NVM as a persistent page cache to eliminate the periodic disk synchronization overhead of dirty data. Then we design an efficient consistency mechanism based on the hybrid memory architecture to provide strong (both metadata and data) consistency guarantee with low overhead. The evaluation demonstrates that HasFS outperforms mainstream DRAM–DISK file systems for many workloads. For instance, HasFS has between 1.6X to 46.6X performance improvement over other tested file systems in random write workload. In particular, HasFS outperforms EXT4 without journal in some cases even though HasFS provides metadata and data consistency guarantees (similar to EXT4 with journal data mode). [ABSTRACT FROM AUTHOR]

3D XPoint is the first commercially available main memory NVM solution targeting mainstream computer systems. Previous database studies on NVM memory evaluate their proposed techniques mainly on simulated or emulated NVM hardware. In this paper, we report our initial experience experimenting with the real 3D XPoint main memory hardware. [ABSTRACT FROM AUTHOR]

Paravirtual I/O systems have been paid much attention to due to their reasonable performance levels. To increase these levels, Non-Volatile Memory (NVM) such as flash memory is considered and used as their storage media alternative to HDD. Although the storage media is fast, the performance of paravirtual I/O systems using the media is much lower than expected. The performance is lowered because the I/O process in the guest and host OSes is serialized and the OSes are run ignoring the processor affinity while the same software layers performing I/O are duplicated in the OSes. We present our methodology to employ towards optimizing the performance of NVM-based paravirtual I/O systems: the use of polling rather than interrupt, and parallel batching in order to maximize the parallelism in performing the sequence of I/O operations, and avoidance of context switches in order to consider the processor affinity. Our experiments with Kernel Virtual Machine (KVM) I/O systems using different NVM storage devices suggest that the use of the methodology can lead to enhancements in throughput by 50% to more than 80% while reducing CPU usage by up to 25% for a microbenchmark program and by up to 100% for workloads in mixed-read/write patterms. [ABSTRACT FROM AUTHOR]

This paper presents the theory, fabrication and experimental testing results for a multiple state Non-Volatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore's Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations. [ABSTRACT FROM AUTHOR]

Featured Application: The authors anticipate that memory and storage configurations explored in this article will be helpful in the design of system software for future computer systems with ever-growing memory demands and the limited density of DRAM. Recently, non-volatile memory (NVM) has advanced as a fast storage medium, and legacy memory subsystems optimized for DRAM (dynamic random access memory) and HDD (hard disk drive) hierarchies need to be revisited. In this article, we explore the memory subsystems that use NVM as an underlying storage device and discuss the challenges and implications of such systems. As storage performance becomes close to DRAM performance, existing memory configurations and I/O (input/output) mechanisms should be reassessed. This article explores the performance of systems with NVM based storage emulated by the RAMDisk under various configurations. Through our measurement study, we make the following findings. (1) We can decrease the main memory size without performance penalties when NVM storage is adopted instead of HDD. (2) For buffer caching to be effective, judicious management techniques like admission control are necessary. (3) Prefetching is not effective in NVM storage. (4) The effect of synchronous I/O and direct I/O in NVM storage is less significant than that in HDD storage. (5) Performance degradation due to the contention of multi-threads is less severe in NVM based storage than in HDD. Based on these observations, we discuss a new PC configuration consisting of small memory and fast storage in comparison with a traditional PC consisting of large memory and slow storage. We show that this new memory-storage configuration can be an alternative solution for ever-growing memory demands and the limited density of DRAM memory. We anticipate that our results will provide directions in system software development in the presence of ever-faster storage devices. [ABSTRACT FROM AUTHOR]