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As the technology is scaled-down and with a decrease in oxide thickness, the effect of NBTI is a major reliability issue in semiconductor industries. NBTI is an aging phenomenon in which the PMOS transistor degraded over time. Deviation in the threshold voltage of PMOS transistor results from NBTI with stress time which affects various parameter of SRAM memory such as degradation in drain current, RSNM, HSNM and access time. NBTI induced aging effect on 6 T and 8 T SRAM cell have been analyzed in this paper for the stress time of 10 years. The reliability parameters of 6 T SRAM cell obtained from simulation result shows there is 6.53%, 23.86%, 3.36% and 13.42% change in Hold SNM (HSNM), Read SNM (RSNM), Write margin and standby leakage current respectively after 10 years. Similarly in 8 T SRAM cell HSNM, RSNM, Write margin and leakage current changes by 5.81%, 5.01%, 3.11%, and 13.24% respectively. This paper also presents the leakage current sensing technique based NBTI monitoring sensor using NMOS transistors only. The sensitivity of the sensor is 40 µV/nA and the linearity of the sensor is upto the practical leakage current range of SRAM cell. Thus we can conclude that the proposed sensor works fine with greater linearity and sensitivity.

This paper presents an amplifier-chain-based XOR physical unclonable function (AC-XOR PUF), with the process- and/or bias-dependent voltage and amplification information of two identical amplifier chains serving as the entropy sources. The current-biased PUF cell using only 4 NMOS transistors achieves a small area with reduced temperature and supply sensitivity. Optimization on both the stage gain and stage number can reduce the input-referred noise (IRN) and improve the PUF reliability. We further employ an XOR gate to process the amplifier-chain outputs for the final response to improve the energy efficiency and uniqueness. The process- and bias-dependent stage amplification and the nonlinear amplifier-chain multiplication, which can significantly increase the number of modeling parameters and introduce a complex decision boundary respectively, can effectively resist machine learning (ML) modeling attacks. Fabricated in standard 65nm CMOS, the proposed AC-XOR PUF occupies an active area of 6845μm². Without discarding any challenge-response pairs (CRPs), this work features a measured worst case bit error rate (BER) of 5.70% across 1.06~1.55V and -30~125°C, while demonstrating a reliability (intra-die HD) and uniqueness (inter-die HD) of 0.58% and 49.92%, respectively. It also achieves a ML prediction accuracy of 50.72% using 80x 80x80 artificial neural network (ANN) with 1M CPRs as training set.

A new approach based on a strong degeneracy state to design oscillators that exhibit low phase noise and low power consumption is presented. A 100-MHz oscillator is designed using a periodic structure based on a degenerate band edge that is augmented with an NMOS cross-coupled pair. The analysis and simulation results show 16 dB phase noise improvement compared to oscillators based on a conventional single-ladder periodic structure. It is also shown that this oscillator dissipates less power than a conventional LC oscillator that requires a buffer to drive a 50Ω load.

Effects of ~35 years of aging during storage are investigated on the radiation response and 1/f noise of Oki nMOS and pMOS transistors with high oxygen vacancy densities in SiO2. Short-term interface-trap buildup during irradiation is enhanced significantly, relative to that observed in 1989, 1997, and 2008. In contrast, similar latent interface-trap buildup is observed for aged pMOS devices irradiated and annealed at room and elevated temperatures at positive bias in this and earlier studies. Significant latent interface-trap buildup is observed for nMOS devices irradiated at 0 V and annealed at room and elevated temperatures under positive bias, a condition not evaluated in prior work. Results strongly suggest that latent interface-trap buildup is due to H2 diffusion and dissociation at charged or dipolar O vacancies in SiO2, followed by proton transport to the Si/SiO2 interface and reactions with Si-H complexes. Models that attribute latent interface-trap buildup to long-term proton trapping at O vacancies in SiO2 appear to be ruled out by these results. Additional insight is provided into mechanisms of post-irradiation interface- and border-trap buildup after long-term MOS device storage.

2-D-material channels enable ultimate scaling of MOSFET transistors and will help Moore's Law scaling for years. We demonstrate the state of both n- and p-MOSFETs using monolayer transition metal dichalcogenide (TMD) channels of sub-1 nm thickness and manufacturable CVD, molecular beam epitaxy (MBE), or seeded growth. nMOS devices on transferred MBE MoS₂ using novel contact metal show low variation, one of the lowest reported contact resistances ( $R_{c}$ ) of 0.4 kΩ ·μ m, low hysteresis, and good subthreshold swing (SS) of 77 mV/dec. pMOS devices using CVD WSe₂ show 89 mV/dec SS, best reported for pMOS on grown films, but on-current remains behind nMOS. We show $R_{C}$ is improved by 5x by using a bake process prior to contact metal deposition. Transfer-free, area-selective seeded growth techniques for WS₂ and MoS₂ are demonstrated as options for wafer-scale TMD channel growth. WS₂ transistors achieve 10 μA/μm on-current, highest reported on WS₂ using seeded growth. A new capacitance method is shown to monitor 2-D material contact interface quality. Gate-oxide interface engineering through metal seeding and atomic layer deposition (ALD) demonstrates that a single 2-D channel material can selectively make pMOS or nMOS transistors, alike Si CMOS, and can also be used as a method to achieve p-type doping. We compare back-gated bare channel devices with dual-gate devices and observe hysteresis-free operation and an improvement in mobility with proper passivation.

The polynomial form of the input impedance of a CMOS cross-coupled amplifier with NMOS only active inductor are proposed. The formula of polynomial form and novel coefficients are programmed in Scilab and MATLAB so that the pole position of the fourth order polynomial can be found. From experience of a simple cross coupled oscillator design, the proposed circuit diagram may not oscillate as a triangular wave signal because the two poles are complex (underdamped case) but its real part could not be minimized to 0.001 so that it has a stable amplitude and additional two poles are real poles. The impulse sensitivity function (ISF) of the proposed circuit is derived for the first time so that it may be used to derive phase noise in the future.

Total ionizing dose (TID) degradation is caused by radiation-induced charge buildup in oxides. Radiation hardening of silicon-on-insulator (SOI) devices with deep submicrometer nodes or nanonodes is mainly concerned with the field oxide and buried oxide. In this article, a back-channel adjustment technique for TID hardening is proposed. The technique is compatible with the 130-nm partially depleted silicon on an insulator (PDSOI) commercial process with no extra effort applied to the design. After testing the key electrical parameters and characterizing the radiation tolerance of the typical T-gate I/O nMOS devices, the results show that the radiation tolerance of the devices can reach more than 1 Mrad(Si) with the back-channel adjustment technique, and electrical performance is comparable to that of commercial process devices.

This brief presents an inductorless $g_{m}$ -boosted wideband balun low noise amplifier (LNA) for low power sub-GHz IoT applications. The proposed common source (CS) - common gate (CG) based $g_{m}$ -boosted balun LNA uses nMOS-pMOS configuration for doubling the transconductance and gain efficiency. Loads of CS and CG stages are capacitively coupled to remove the tradeoff between voltage gain and voltage headroom. In addition to this, the circuit employs noise cancelation using the CS-CG pair. The LNA is implemented in 0.18 $\mu \text{m}$ RFCMOS process, which achieves a maximum voltage gain of 19.6 dB with a minimum noise figure (NF) of 3.6 dB. The 3-dB bandwidth ranges from 0.13 GHz to 0.93 GHz. The minimum IIP3 and IIP2 measured are −8.5 dBm and 12 dBm, respectively. The LNA core area is 0.18 $mm^{2}$ and dissipates a total power of 3 mW from 1.8 V power supply.

A dual-MOS-triggered silicon-controlled rectifier (DMTSCR) has been firstly developed for high-voltage (HV) electrostatic discharge (ESD) protection. Compared to the reported SCRs with modified structures, the DMTSCR harvests a series of advantages such as a high holding voltage ( $V_{h}$ ), a strong ESD robustness, and a low $V_{t1}$ , thanks to its embedded structures including a gate-to-VDD PMOS, a gate-grounded NMOS, and a modified SCR. Thus, the DMTSCR has the largest figure of merit as high as 1.8 mA/ $\mu \text{m}^{2}$ . By further optimizing the layout and the key spacing between the embedded PMOS and NMOS of DMTSCR, $V_{h}$ increased from 8.4 to 17.4 V, the turn-on resistance remarkably decreased to $0.4~\Omega $ , and the turn-on voltage was clamped at $V_{h}$ . The optimized DMTSCR with a small chip area possesses an ESD robustness of 3000 V evaluated by the human body model. Meanwhile, the operation mechanism simulated by Sentaurus exhibited good agreements with the theoretical circuit analysis, and the simulated electrical characteristics were consistent with those measured from the experimental devices. The layout-optimized DMTSCR with good clamping ability and zero snapback voltage is a promising solution for stacking to meet various HV ESD protection requirements.

Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET has been explored for low power applications. This paper presents an analytical model of subthreshold current of Stacked Dielectric Triple Material Cylindrical Gate All Around (SD-TM-CGAA) Junctionless MOSFET. The analytical results are compared with TMSG MOSFET and good agreement was obtained. The sub-threshold current of the device is very low and is considered for the implementation of CMOS inverter. A PMOS transistor is designed and the drive current of the PMOS transistor is tuned with the NMOS device to obtain the ideal matching in the drive current. A CMOS inverter has been designed. The transient and DC behavior of the device have been examined. The power dissipation of the CMOS inverter has been computed and compared with the CMOS DMG-SOI JLT inverter. The power dissipation is found to be 5 times less for the proposed device as compared to the CMOS DMG-SOI JLT inverter. This exhibits an excellent improvement in power dissipation which is useful for making low-power future generation devices.

An improved Gilbert mixer with the current reuse and source degeneration techniques is investigated. This design and simulation carried out by considering UMC 180 nm CMOS process in the Cadence Tool 6.1.6 with 2.4 GHz. The investigation is presented with the current reuse topology by stacking both pMOS and nMOS transistors. The reduction of the power consumption is obtained due to the self-biasing of the shunt feedback resistor. An improvement in the conversion gain and linearity is shown through the source degeneration in this mixer design. The proposed design achieves the maximum conversion gain (CG) of 13.2 dB with the noise figure (NF) of 8.6 dB. The design circuit consumes 0.7 mW power from 1.2 V with the 1 dB compression point of −2.63 dBm and third-order input intercept point (IIP3) of 8.2 dBm. The chip area occupied is 0.128 × 0.180 mm2 shown in the layout design. This compact layout of the mixer helps to create an opportunity as a suitable building block for RF integrated circuit (RFIC) applications with moderately high performance in the receiver front end.

A high-speed and low energy-consuming SRAM design based on single-ended cells is demonstrated in this work. To resolve poor SNM (static noise margin) of prior single-ended memory cells, the proposed SRAM cell is equipped with a pull-up PMOS and a high-Vthn NMOS foot switch such that the cell state is not bothered by noise when the supply voltage is getting lowered. Moreover, a PFOS (Positive Feedback Op-Amp Sensing) circuit is added between bitlines ( $\overline {\text {BL}}$ , BL) to reduce the read delay and generate full-swing output. Last but not least, a voltage mode select (VMS) circuit is added to each column to reduce the static power of unselected cells such that idle power is drastically reduced. The reason is that the a lower voltage able to keep the state of bits is applied to those unselected cells. A 1-kb SRAM prototype based on the proposed cells with BIST (build-in self test) circuit is physically fabricated using typical 40-nm CMOS logic process. The maximum operating clock rate is 200 MHz. The energy/access and energy/bit are measured on silicon to be 0.2313 pJ, and 0.00723 pJ, respectively.

A unique failure mechanism for International Electrotechnical Commission (IEC) stress through a common-mode (CM) choke is investigated. The presence of a CM choke in the stress path was found to change the current waveform shape that the electrostatic discharge (ESD) protection device experiences on-chip. Minor variations in the stress current waveform shape for specific IEC stress levels are found to cause an unexpected window failure in drain-extended nMOS silicon controlled rectifier (DeNMOS-SCR). The 3-D technology computer-aided (TCAD) simulations are used to understand the device behavior and failure under the peculiar two-pulse-shaped IEC current waveform attributed to the presence of a CM choke. DeNMOS-SCR failure sensitivity to different components of the unique pulse shape is studied in detail. A novel device architecture is proposed to increase the DeNMOS-SCR robustness against the peculiar two pulse stimuli. The proposed DeNMOS-SCR was found to eliminate the window failures against system-level IEC stress through a CM choke in communication pins in automotive ICs. The proposed concept is universal and can be extended to all high-voltage DeNMOS-SCRs. A detailed physical insight is provided for the operation of the engineered structure.

This work presents a fully planar, nondestructive readout, and high-performance impact ionization random access memory ( ${I}^{\,2}$ -RAM) cell having static random access memory (SRAM) characteristics. The proposed memory cell consists of a bipolar ${I}^{\,2}$ MOSFET (BIMOS) whose source region is shared with the drain region of a control gate (CG)-nMOS. The proposed ${I}^{\,2}$ -RAM offers excellent static characteristics, including write “1” (W1) time of ~0.5 ns, superior nondestructive readout time of ~0.4 ns, and sense margin (SM) of $\sim 242~\mu \text{A} / \mu \text{m}$ at room temperature (300 K). The proposed ${I}^{\,2}$ -RAM cell also shows a static retention time (RT) >3600 s at a lower supply voltage of ${V}_{\text{DS}} =1.1$ V for 300 K and 358 K temperatures. It additionally has a high read current ratio of $\sim 2\times 10^{9}$ and $\sim 4\times 10^{7}$ at temperatures 300 and 358 K, respectively. The proposed $I^{2}$ -RAM cell is promising candidate for embedded-RAM and high-performance applications.

This paper presents a fast and power-efficient high voltage level shifter architecture capable of converting low level of input voltages into extremely high output voltage levels. The presented architecture uses single type of PMOS and NMOS transistors, operated at three times the safe operating area limit of transistors. The circuit is designed to take an input signal of 1V/0 and provides multiple output signals varying between 15, 10 and 5V/0 under the specified load condition. Circuit is designed and implemented in 110nm-BCD technology using 5V capable transistors. Post-layout simulation results demonstrate a total Energy Per Transition of 5.6pJ, a static current consumption of 180pA, and a propagation delay of 2nS for an input frequency of 100MHz.

With the increase in communication requirements, new communication technologies and implementation methods have developed rapidly. The rise of emerging markets such as the Internet of Things, smart homes, smart cities, and wearables has promoted the development of wireless communication integrated circuits in the direction of monolithic, low energy consumption, and high energy efficiency. This paper proposes a new dual branch charge pump based on CTS charge pump with enhanced current drive capability and undesired charge transfer completely eliminated. Clock matched technology is proposed to completely eliminate undesired charge transfer caused by delay turn on and off of the auxiliary transistors in the traditional CTS charge pump. The current drive capability is enhanced by employing NMOS transistors with 2Vdd gate drive voltage, while traditional dual branch CTS charge pumps are based on PMOS with 1Vdd gate drive voltage. The output voltage ripple is also reduced resulting from a dual branch structure. Simulation results of output voltage gain and power efficiency for the proposed charge pump and other traditional charge pumps are provided. Comparisons are made to show the improvement of the proposed charge pump compared with other traditional charge pumps.

CMOS circuits based on scaled transistors are typically more susceptible to soft errors caused by energetic particles in the radiation environment than circuits employing their large-area counterparts. In this paper, a soft error tolerant latch built on a Schmitt trigger, which is entirely realized with NMOS transistors with an additional voltage booster, which we refer to as NST-VB, is proposed. To evaluate the circuits’ radiation resilience, we identify the most sensitive nodes by analyzing the critical charges at the various latches’ internal sensitive nodes. We also examine the linear energy transfer (LET) of the essential latches and observe that the NST-VB latch has an improved LET of $$0.386~\mathrm {MeV~cm^2/mg}$$ as compared to $$0.231~\mathrm {MeV~cm^2/mg}$$ and $$0.365~\mathrm {MeV~cm^2/mg}$$ for unhardened latch and ST latch, respectively. For the process variation analysis, we further examined 5k Monte Carlo simulations to analyze the impact of device variability on our design and observe that the proposed NST-VB latch has $$1.96\times $$ less variability critical voltage concerning the ST latch. Further, the logic flipping probability for NST-VB latch is 48.32% compared to 53.04% for ST latch. Also, the critical charge to power delay area product ratio (QPAR) is calculated and evaluated for the proposed latch’s effectiveness compared to other considered latches.

It is a big challenge to construct large-scale, high-resolution and high-performance inkjet-printed metal oxide thin film transistor (TFT) arrays with independent gates for the new printed displays. Here, a self-confined inkjet printing technology has been developed to construct large-area (64 × 64 array), high-resolution and high-performance metal oxide bilayer (In2O3/IGZO) heterojunction TFTs with independent bottom gates on transparent glass substrates. Inkjet printing In2O3 dot arrays with the diameters from 55 to 70 μm and the thickness of ∼10 nm were firstly deposited on UV/ozone treated AlOx dielectric layers, and then IGZO dots were selectively printed on the top of In2O3 dots by self-confined technology to form In2O3/IGZO heterojunction channels. When the inkjet-printed IO layers treated by UV/ozone for more than 30 min or oxygen plasma for 5 min prior to print IGZO thin films, the mobility of the resulting printed In2O3/IGZO heterojunction TFTs are correspondingly enhanced to be 18.80 and 28.44 cm2 V−1 s−1 with excellent on/off ratios (>108) and negligible hysteresis. Furthermore, the printed N-Metal-Oxide-Semiconductor (NMOS) inverter consisted of an In2O3/IGZO TFT and an IGZO TFT has been demonstrated, which show excellent performance with the voltage gain up to 112. The strategy demonstrated here can be considered as general approaches to realize a new generation of high-performance printed logic gates, circuits and display driving circuits.

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LETth) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V.

Highlights Fully inkjet-printed transparent high-performance thin-film transistors (TFTs) with ultrathin indium tin oxide (ITO) as semiconducting channels were achieved. The energy band alignment at ITO/Al2O3 channel/dielectric interface was investigated by in-depth spectroscopy analysis. Fully printed n-type metal–oxide–semiconductor inverters based on ITO TFTs exhibited extremely high gain of 181 at a low-supply voltage of 3 V, promising for applications in advanced electronic devices and circuits. Supplementary Information The online version contains supplementary material available at 10.1007/s40820-021-00694-4., Metal oxide thin-films transistors (TFTs) produced from solution-based printing techniques can lead to large-area electronics with low cost. However, the performance of current printed devices is inferior to those from vacuum-based methods due to poor film uniformity induced by the “coffee-ring” effect. Here, we report a novel approach to print high-performance indium tin oxide (ITO)-based TFTs and logic inverters by taking advantage of such notorious effect. ITO has high electrical conductivity and is generally used as an electrode material. However, by reducing the film thickness down to nanometers scale, the carrier concentration of ITO can be effectively reduced to enable new applications as active channels in transistors. The ultrathin (~10-nm-thick) ITO film in the center of the coffee-ring worked as semiconducting channels, while the thick ITO ridges (>18-nm-thick) served as the contact electrodes. The fully inkjet-printed ITO TFTs exhibited a high saturation mobility of 34.9 cm2 V−1 s−1 and a low subthreshold swing of 105 mV dec−1. In addition, the devices exhibited excellent electrical stability under positive bias illumination stress (PBIS, ΔVth = 0.31 V) and negative bias illuminaiton stress (NBIS, ΔVth = −0.29 V) after 10,000 s voltage bias tests. More remarkably, fully printed n-type metal–oxide–semiconductor (NMOS) inverter based on ITO TFTs exhibited an extremely high gain of 181 at a low-supply voltage of 3 V, promising for advanced electronics applications. Supplementary Information The online version contains supplementary material available at 10.1007/s40820-021-00694-4.

We found that specific pairs of pMOS and nMOS transistors in dual interlocked storage cell flip flop (DICEFF) become sensitive to soft errors by device simulations. We propose several layout structures that can improve soft-error tolerance with additional 39%–46% area overhead. We evaluated soft-error tolerance of a D-type FF (DFF) and DICEFFs in a 65-nm bulk process by heavy ions. Our experimental results showed that the DICEFF has more than $300\times $ better soft-error tolerance than the DFF by Kr (LET $40.3~\text {MeV}\cdot \text {cm}^{2}$ /mg) irradiation when the supply voltage is 1.2 V, and the DICEFF has only $9\times $ better soft-error tolerance than the DFF when the supply voltage is 0.6 V. However, the proposed DICEFF with 46% area overhead has $58\times $ better soft-error tolerance than the DFF when the supply voltage is 0.6 V. DICEFF has so many sensitive pairs and lower soft-error tolerance as supply voltage decreases that cannot be applied to highly scaled process technologies.

This brief presents a simple and power-efficient impedance adapting compensation scheme for high current NMOS low-dropout regulators (LDOs). By the proposed technique, the low-frequency node impedance retains to high value, while the high-frequency impedance is greatly attenuated. Therefore, both high gain and decent transient response is achieved simultaneously. Besides, the proposed impedance adaption waived the need for a commonly required power-hungry driver circuit, leading to a more simplified and energy-efficient design. In addition, the load-tracking technique is applied to further cancel the effect of load current variations, and helps achieve decent frequency and transient responses over a wide load range. Fabricated in a 0.35 ${\mu }\text{m}$ CMOS process, the chip regulates an output voltage form 0.8 V to 1.8 V with 6 A current capacity and 114 mV maximum dropout voltage. The measurement results show an over-/undershoot voltages of 35.4 mV and −32.2 mV, respectively, for load transitions between 400 mA and 5A. The load and line regulations are 0.7mV/A and 0.12 mV/V, respectively, and the power supply rejections are −55 dB and −30 dB at 10 KHz and 1 MHz, respectively.

This article presents a monolithic hybrid boost converter suitable for a high conversion ratio (CR). It uses two inductors, two cross-connected flying capacitors ( $C_{F}\text{s}$ ), and six power switches, allowing a two-phase operation and $C_{F}\text{s}$ near-soft charging. With the internal voltages halved by the $C_{F}\text{s}$ , the inductor current ripple and voltage stress of the switches decrease, thus allowing a reduction in both power loss and silicon area. In addition, the cross-connected $C_{F}\text{s}$ double the pulsewidth of the control signals, thereby allowing a higher switching frequency even under a very high CR. Moreover, this design shares the large bootstrap capacitors of the high-side NMOS switches and also eliminates the need for an additional bootstrap voltage generation for the stacked NMOS switches, enabling an area-efficient full integration of the bootstrap capacitors. The converter, fabricated in 0.35- $\mu \text{m}$ CMOS, occupies a core area of 0.86 mm2. It achieves a 93.5% peak efficiency when the CR is 4.5, with two 3.3- $\mu \text{H}$ inductors (3010 package), two 0.47- $\mu \text{F}~C_{F}\text{s}$ , and a 2-MHz switching frequency.

This paper provides the design, simulation andimplementation of a very wide dynamic range and a low readoutnoise CMOS image sensor (CIS) with high sensitivity by using adiode connected transistors in parallel with floating diffusionnode and sensor output. The sensor is simulated, designed andimplemented in a 130 nm CMOS technology using cadence tool.The area of the proposed pixel reaches to 3 um x 3 um andconsists of seven NMOS transistors and one capacitor. Thereadout circuit has the following parameters as very low outputnoise of 20 uVrms with a 5 MHz bandwidth for pixel circuitry.Power dissipation of 10 uW was achieved at an operation voltageof 1.6 V for pixel circuitry. The proposed sensor has goodfeatures of low noise and a 140 dB wide dynamic range due to thediode connected transistor configuration that has been used. Thispaper provides the effect of adding a diode connected transistorsM7 and M8 on an increasing dynamic range of CMOS imagesensor to 140 dB and reducing its readout noise to 20 uVrms. Also,this paper provides a mathematical simulation of noise model ofCIS using Matlab and cadence.

The emergence of SMPTE ST 2110 as a key technology enables flexible and scalable audiovisual (AV) over Internet Protocol (IP) infrastructures to be deployed. Until recently, a common control system was not available. Spearheaded by the Advanced Media Workflow Association (AMWA), the Networked Media Open Specification (NMOS) initially defined IS-04 (Registration & Discovery) and IS-05 (Connection Management), which was a great start to getting a unified control system in place and met the needs of many users. Now NMOS has expanded to exceed the capabilities found in legacy serial digital interface (SDI) switching systems, including adding a much needed security layer. This paper dives into the details about what NMOS is, how it works, and everything one should know to become an expert on the control system for AV over IP .

A new sub-1V and low power multiphase voltage-controlled oscillator (QVCO) with current-reused structure is proposed. The proposed core oscillator consists of two N-metal oxide semiconductor (NMOS) and P-metal oxide semiconductor (PMOS) transistors and an additional NMOS-only cross-coupled pair that enhances the effective negative transconductance and facilities the start-up condition at sub-1V supply voltages in modern nm CMOS technologies. In the proposed coupling scheme, the gate of cross-coupled transistors is used for coupling in an ‘in-phase−anti-phase’ manner. Parallel capacitors to the drain-source of transistors have been used for further enhancement of effective transconductance and thus lower power consumption; though the increase of parallel capacitors reduces the tuning range, indicating a trade-off in the proposed QVCO. The proposed quadrature oscillator is designed and simulated in a standard 0.18 μm RF-CMOS technology. The results of the simulation show that the QVCO has a 9% tuning range from 5.35 GHz to 5.88 GHz, and the phase noise is −119.6 dBc/Hz at 1-MHz offset from the 5.7 GHz carrier while consumes only 1.4 mW from a 0.85-V supply voltage; yielding an excellent figure-of-merit (FOM) of −193.3 dBc that is amongst the best FOMs. Several Monte Carlo and PVT analyses verify the robust performance of the QVCO.

In mobile applications, power density highly affects mobility, cost, form factor, and battery time. To improve power density, high switching frequency operation is highly desirable for a power converter. However, with high switching frequency, switching power loss increases significantly, compromising efficiency and battery time. This article presents an on-chip 3-level DC–DC converter, using all NMOS devices as power switches, which reduces switching power loss and silicon cost. To facilitate the all-NMOS power stage operation and enhance the robustness to input supply variation, a 3-switch boost-strap gate driver is designed. Meanwhile, an interception coupling dead-time (ICDT) control is introduced to minimize dead-time related power loss. An integrated circuit prototype was fabricated using a 0.35 μm CMOS process. Robustly working with a variable input voltage from 3 to 6 V, it regulates a programmable power output from 0.4 to 1.6 V, with a maximum power efficiency of 85.5% over a full power range of 800 mW and a maximum power density of 1.07 W/mm2. Thanks to the ICDT control, it achieves a 0.5 ns dead-time over a full-load range of 500 mA.

In this work, we report the characterization and modeling of a 14 nm bulk FinFET technology from room-temperature down to 4.6 K. A cryogenic device model is used which shows excellent fit to measured data and can accurately predict the performance of the devices at low temperatures. The nMOS device showed subthreshold swing of 20 mV/decade, V T shift of 80 mV and gm enhancement of 30%, all at 4.6 K. These results show that a tailored cryogenic FinFET technology, i.e. one accounting for the change in V T and SS, could achieve a sharp reduction of dissipated power by reducing the drive bias. Such technology has potential for strong impact e.g. in quantum computing, by enabling integration of dense advanced cryogenic ICs inside the cryostat.

This paper proposes three modified memristor ratioed logic (MRL) gates: NOT, NOR and A AND (NOR B) (i.e., $$A \cdot \bar{B}$$ ), each of which only needs 1 memristor and 1 NMOS. Based on the modified MRL gates, we design some combinational logic circuits, including 1-bit comparator, 3-bit binary encoder, 3-bit binary decoder and 4:1 multiplexer. Furthermore, an improved multifunctional logic module is proposed, which contains one NMOS transistor and five memristors, and can implement AND, OR and XOR logic operations. Using this multifunctional logic module, a 4-bit comparator and a 1-bit full adder are designed. Finally, the proposed combinational logic circuits are verified by LTSPICE simulations. Compared with other memristor-based logic circuits and the traditional CMOS technology, the proposed logic circuits have made great progress in reducing delay, power consumption and the number of transistors.

Compared to poly Si gate, metal gate has no gate depletions and experiences inversion capacitance gain, which makes an advantage for devices scaling. In this paper, we investigated the gate oxide leakage current and Time Dependent Dielectric Breakdown (TDDB) characteristics of TiN and poly Si electrodes with a 3.5 to 5 nm SiO2 dielectric thickness range. According to the Transmission Electron Microscope (TEM) analysis there is difference in oxide thickness. The SiO2 thickness of TiN gate electrode has been reduced by ~0.25 nm, considerably because of a scavenging effect. We normalized the reduced SiO2 thickness with an electrical oxide field, and there were no differences between the two electrodes in gate leakage current, accumulation breakdown voltage (BV), and accumulation TDDB lifetime. Therefore, we found the scavenging effect of TiN electrodes seems to affect little the leakage current and TDDB reliability of SiO2 dielectric. On the other hand, the BV and TDDB lifetime of TiN electrode in the inversion region are little bit better than that of the poly electrode. We think this differences are originated from the difference between TiN/SiO2 and poly Si/SiO2 interfaces.

This work reports on charging damage induced by gate antennae in high- $\kappa $ (HK) Replacement Metal Gate (RMG) technology for the HK-first and HK-last integration flows, comparing plate and comb layouts. For the HK-first devices, a significant degradation of the Gate Induced Drain Leakage (GIDL) occurs for both types of antennae, which is analyzed in terms of activation energy and corresponding trap characteristics. The degradation of the HK-last transistors is attributed to top oxide deposition which causes a different degradation pattern. In this case, charging damage leads to a degradation of the gate leakage which correlates with the “aspect ratio” of the antenna. These differences are explained and analyzed based on the plasma characteristics.

In this article, a novel subthreshold voltage reference (VR)-based physical unclonable function (PUF) is presented. With two native nMOS transistors stacked on top for providing bias current and two bottom low threshold voltage (LVT) nMOS transistors forming the self-cascode MOSFETs structure, a 4T all-MOSFET VR is proposed, which features low power consumption and high stability under largely varied VT conditions for the wide range of Internet of Things (IoT) applications. By integrating a pair of the proposed VRs and a digital voltage comparator in each PUF cell, the mismatched output voltages of the VR pair can be locally compared and digitized immediately with the system’s power on, leading to ultrashort signal path and maximized immunity to the influence of temporal noise. Fabricated using standard 0.18- $\mu \text{m}$ CMOS process, the proposed PUF design is validated based on extensive measurement results of 20 PUF chips. By passing the widely exploited bias test, National Institute of Standards and Technology (NIST) test and autocorrelation function (ACF) test, the proposed PUF’s excellent randomness is well-verified. In addition, the uniqueness is measured to be 49.92%, and the bit error rate (BER) sensitivities in terms of BER per 10 °C and BER per 0.1 V are averaged and reported to be 0.39% and 0.26%, for the temperature range of −40 °C–120 °C and supply voltage range of 1.2–1.8 V, respectively. Moreover, by operating the proposed implementation at a throughput of 50 Mb/s, the measured overall energy consumption is reported to be as low as 163 fJ/bit.

This paper presents a wide input range active rectifier using a bipolar-CMOS-DMOS (BCD) process with a high voltage conversion ratio (VCR) and high power conversion efficiency (PCE). The proposed rectifier ensures safe and robust operation under large input voltage variations, which can be caused by changes in the magnetic coupling or loading conditions. It supports an input voltage range 3–12 V with the adaptive delay-compensated active operation of the power switches. An active signal clamper and voltage-time hybrid gate control circuit with two compensation loops was proposed for the optimal gate transition of low-side NMOS switches. For high-side PMOS switches, a fully integrated low-power-consuming high-side driver is proposed to replace the conventional high-side gate driving structure. The proposed active rectifier was fabricated through a TSMC $0.18\mu \text{m}$ BCD process. The measurement results show that the proposed rectifier achieves stable and well-delay-compensated active operation, resulting in a high VCR and PCE with a wide output power range from 4.5 to 288 mW. Peak VCR and PCE of 96.8% and 93.7%, respectively, were achieved.

An electrostatic discharge (ESD)-protected one-time-programmable (OTP) memory front-end circuit, for high-voltage (HV) applications, designed and manufactured in silicon-on-insulator (SOI) technology, is presented. The SOI technology meets HV functional-isolation and level-shifting requirements but is not suitable for advanced analog circuits. The presented OTP memory is discussed as an introduction to digital programmability in the considered technology. The memory element consists of an antifuse type structure and is implemented using a 5-V nMOS with $\text {L}={1}\,\, \mathbf {\mu \text {m}}$ and $\text {W}={1.2}\,\, \mathbf {\mu \text {m}}$ . The cell memory allows for significant area and power savings in the adopted HV technology. Conditions for this require that an efficient ESD protection will guarantee safe operation, even in the presence of a small and fragile on-chip element whose undesired burning would compromise the programming mechanism, and consequently the reliability, of the circuit. Details about the circuit design implementation of the front-end circuit for both read and write circuits and ESD protection are described with experimental results validating the proposed implementation.

Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, an static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.

This paper proposes a new rad hard layout L style of nmos metal oxide semiconductor field effect transistor (n-MOSFET), which is evaluated to show that its efficacy at reducing radiation-induced leakage currents, thus improving the total ionization dose(TID) tolerance with very less area and parasitic capacitance as compared to enclosed layout transistor(ELT). This proposed layout structure is fully compatible to present commercial fabrication technology without any additional mask requirement as compared to conventional n MOSFET fabrication and can be used as radiation tolerant by design technique. The simulated ID - VG characteristics of the rad hard L n-MOSFET layout demonstrated the effectiveness of eliminating radiation-induced leakage current paths. The leakage current in proposed rad hard L n-MOSFET has been reduced by factor of 108 at 300Krad dose as compared to conventional layout n-MOSFET.

With the continuous shrinking of the technological nodes and the introduction of new device concepts and materials, integrated circuits (IC) are becoming more vulnerable to electrostatic discharge (ESD) induced failures which is one of the major concerns in designing robust ICs. Therefore, to improve the reliability of the ICs against ESD induced failures, extensive research efforts are being conducted. In this paper, we have presented a 6H-SiC based nano-scale grounded-gate NMOS (ggNMOS) ESD protection device and compared the results with the 3C-SiC-based ggNMOS. To design a robust ESD protection device, some critical device parameters, such as substrate doping concentration, source/drain doping concentration, drain to substrate contact spacing, and substrate contact resistance should be optimized. The ESD protection characteristics can be improved by utilizing the near punch-through effect. It was found that the trigger voltage and hold voltage are higher in 6H-SiC than the 3C-SiC having identical device parameters. 6H-SiC shows better voltage clamping performance as the turn-on resistance of 6H-SiC is smaller compared to the 3C-SiC material. Therefore, the results show that 6H-SiC has a better performance compared to 3C-SiC and due to its higher bandgap, and can be used as a good ESD protection device. All the simulations are carried out using the Silvaco ATLAS device simulator.

In this paper, we simulate the electrical characteristics of the n-type metal-oxide-semiconductor (NMOS) transistor in a 65-nm complementary metal-oxide-semiconductor (CMOS) inverter under the actions of heavy ions with different linear energy transfers (LET). We analyze the influence of incident ions with different LETs on a device using technology computer-aided design (TCAD) software, and aim to establish an HSPICE sub-circuit model containing the relationship between the electrical properties of a device and the LET of an incident ion for circuit-level HSPICE simulation. Based on the SEE funnel mechanism, we propose an analytical model to describe the relationship between the charge collected by the NMOS drain and the LET of the incident ion, and build an HSPICE model based on this analytical model. With such a model, the influence of incident ions with different circuit-level LETs can be determined from HSPICE simulation. In addition, good agreement with simulation results is reached, proving the reasonableness of the proposed model.

Total-ionizing-dose (TID) effects and low-frequency noise are evaluated in advanced bulk nMOS and pMOS FinFETs with SiO2/HfO2 gate dielectrics. Otherwise identical devices built with and without through-silicon via (TSV) integration exhibit threshold voltage shifts of less than 25 mV and changes in maximum transconductance of less than 1% up to 2 Mrad(SiO2). TSV integration negligibly impacts threshold shifts and degradation of subthreshold swing and $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ ratios. Similar low-frequency noise magnitudes and frequency dependencies are observed before and after TID irradiation for each device type. Effective densities of the near-interfacial electron traps responsible for the noise in the nMOS devices increase as the surface potential moves toward midgap, while effective densities of the hole traps that cause the noise in the pMOS devices increase as the surface potential moves toward the valence band edge.

This paper proposes a technique to enhance the maximum achievable power gain ( $G_{MAX}$ ) of the two-port active network (2PAN) in the near- $f_{MAX}$ region. This technique is based on using the optimized passive-linear-lossy-reciprocal (PLLR) embedding to increase the unilateral power gain ( $U$ ) of the 2PAN and accordingly the $G_{MAX}$ . Due to the possibility to increase $U$ , it shows the potential to improve the conventional gain-boosting approach which relies on the passive-linear-lossless-reciprocal (PLLLR) embedding and keeps the $U$ constant. The concept itself is demonstrated on pseudo-differential NMOS pair using lossy capacitive feedback as the PLLR. This structure can serve as a basis for further gain optimization by implementing additional PLLLR embedding on top of it. Finally, by using the mentioned technique, a 190GHz amplifier is implemented in 28nm bulk CMOS technology, achieving 14.3dB of gain with 1.5dBm of $P_{SAT}$ and 2.6% of maximum PAE.

A novel electrostatic discharge (ESD) protection device based on an n-type metal–oxide–semiconductor field-effect transistor (NMOSFET) with segmented topology was proposed and investigated, considering the material characteristics of 4H-SiC, which is a wide-bandgap material (3.3 eV). ESD phenomena are important in terms of semiconductor reliability, and the benefits of using 4H-SiC as a material can provide robustness and excellent thermal reliability to ESD protection devices. The proposed device improves the wide range of snapback phenomena caused by the high critical electric field (2.4 MV/cm), in comparison to using Si (0.25 MV/cm); it also improves triggering characteristics and provides a high holding voltage. The proposed device and a traditional silicon-controlled rectifier, a gate-grounded-NMOS, and a gate-body floating NMOS were fabricated using the 4H-SiC process. The electrical characteristics of the experimental devices, determined by a transmission-line-pulsing system, were comparatively analyzed. Additionally, this article presents the analysis of the optimization of electrical characteristics according to the critical design variables of the proposed device, stacking for high-voltage applications, and reliability test results for high temperatures (300–500 K).

MOS transistors in 65-nm CMOS technology exposed to ultrahigh total ionizing dose (TID) levels show clear evidence of a true dose-rate (DR) dependence. In order to assess the impact of this effect and to understand its origin, an extensive measurement campaign has been carried out at different DRs, different temperatures, and different biases. Both nMOS and pMOS devices with different sizes and geometries were studied. The results obtained clearly show that the DR sensitivity of these devices is due to mechanisms that occur in the spacer insulators. Spacers have only recently been identified as an important element in the radiation response of MOS devices exposed to ultrahigh doses and the mechanisms causing their DR sensitivity appear to be largely compatible with the models developed to explain enhanced low dose-rate sensitivity (ELDRS) in linear bipolar transistors.

This article presents a comprehensive analysis of a novel broadband output stage for external RF front-end low-noise amplifiers (eLNAs). Both variants of the output stage are manufactured using a 130nm bulk CMOS technology. They utilize a common-drain output stage with current-reuse topology, switchable resistive feedback, and source-degeneration. Also, a novel inductor-less low insertion-loss bypass mode is implemented for enhanced bypass functionality. The LNAs are implemented with 4 gain modes achieving excellent RF performance in all possible mobile communication scenarios. Furthermore, an auxiliary linearization circuitry (NMOS IMD sinker) is implemented for variant $\beta $ to improve linearity performance in low gain mode. Besides, the LNAs support all frequency bands between 1.4GHz and 2.7GHz by only changing the external matching component, allowing easy adaption to different frequency bands. Two offered solutions are realized with a die size of only 0.16mm2 and 0.11mm2, respectively. The power consumption is 6.0mW in high gain, 3.6mW in low gain and active-bypass and 0.12mW in bypass mode using a supply voltage of 1.2V. Moreover, a 5.15GHz LNA with high-Q on-chip matching and the broadband output stage is realized and manufactured using a 60nm RF SOI technology. A NF performance of only 1.15dB is achieved consuming only 6.0mW power.

The threshold switching properties of the phase transition material (PTM) can be exploited to realize a heterogeneous static random access memory (SRAM) bitcell, which can obviate the need for assist techniques. This unique PTM-SRAM bitcell is designed by placing the PTM in series with the gate of pull-down nMOS transistors. The large insulating state resistance of the PTM device blocks the propagation of read voltage rise during a read operation and noise during retention operation, thereby enhancing read/retention stability. On the flip side, the write-time and write-ability are impacted, which can be improved by tuning the access transistor strength. Overall, the PTM-SRAM bitcell achieves active- $V_{\text {MIN}}$ equivalent to baseline SRAM $V_{\text {MIN}}$ aided by both read- and write-assist techniques. Furthermore, the read access time of the PTM-SRAM bitcell does not degrade with reducing read $V_{\text {MIN}}$ in contrast to other read-assist techniques. For an isoactive- $V_{\text {MIN}}$ of 0.52 V, the PTM-SRAM has 20% lower read access time, 35% lower read power, 16% higher write time, and 55% lower write power compared to the baseline SRAM aided by assist techniques. Also, the dynamic retention stability of the PTM-SRAM improves by $11.36\times $ compared to baseline SRAM. Detailed analysis highlighting the sensitivity of PTM parameters on PTM-SRAM performance metrics is also presented.

In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presented. The design is based on alternating FMCML flip-flops with complementary pMOS or nMOS input differential pairs since common-mode problems arise by using only one type of FMCML flip-flops. The design is carried out after detailed theoretical modeling and analysis versus the flip-flop bias current, thus allowing defining optimized design strategies for the maximum speed or the minimum power-delay product (PDP). The frequency divider architecture and design strategies are validated considering a commercial 28-nm FDSOI CMOS technology. Postlayout simulations of a divider-by-16 show a maximum frequency of about 12 GHz with 74- $\mu \text{W}$ power consumption for the high-speed design and a maximum frequency of 10 GHz with 53- $\mu \text{W}$ power consumption for the minimum PDP design.

This paper models first snapback ambipolar action in NMOS, when subjected to high current stress across the drain terminal. We analyze 2 − D ambipolar current in Gate Grounded NMOS (GGNMOS) devices close to pinch-off region, which is related with S shaped I-V characteristics under highly injected avalanche generated carriers. Furthermore, the first snap-back phenomenon in GGNMOS owing to surface bipolarity is investigated. Due to ambipolar current flow and barrier lowering at source-body junction a novel model of surface bipolar activity has been presented. An analytical model for the surface electrostatics is provided and further compared with 2 − D TCAD device simulation results. Moreover, the electron and hole coupling is reported through a simplified model for a complex and distributed 2 − D parasitic bipolar transistor.

The impact of heavy ion irradiation on the variability of 65 nm bulk Si MOSFETs is experimentally demonstrated in this brief. Due to the intrinsic random incidence of heavy ions, additional variability is introduced in the irradiated devices through displacement damage (DD) and microdose effects. For the smallest size devices, the standard deviation of threshold voltage ( ${V}_{th}$ ) of irradiated devices is up to ~10% larger than fresh devices. The geometry dependence of irradiation-induced variation degradation is illustrated. The irradiation-induced variation degradation increases with decreasing gate width AND/ OR gate length, which is attributed to the irradiation-induced ionization damage fluctuation in the shallow trench isolation (STI) and spacer, respectively. The Pelgrom plot is used to quantify the irradiation-induced variation degradation. After irradiation, the slopes of fitting lines in Pelgrom plots of nMOS and pMOS devices are 10.3% and 5.7% larger, respectively. The results highlight the heavy-ion-induced variation degradation in the nanoscale CMOS devices, which bring new concerns on the design of integrated circuit (IC) for aerospace applications.

In this brief, different characteristics of current starved ring oscillator (CSRO) circuits are investigated and four new designs are proposed. A new parameter, known as phase noise bandwidth product (PNBP), is also proposed to address the trade-off between phase noise performance and frequency tuning range while designing ring oscillators (ROs). The proposed circuits are compared with existing architectures in terms of power consumption, frequency bandwidth, maximum frequency, phase noise, power delay product (PDP) and PNBP. For performance evaluation, three-stage CSROs have been implemented in Cadence software using the 16 nm PTM High Performance (HP) technology model. Simulation results demonstrate that two newly proposed CSRO architectures using one NMOS sink or one PMOS source have similar optimum results in terms of PDP and PNBP as the existing CSRO using an output switch scheme, but with an advantage of lower area requirement. Moreover, all four proposed architectures show improved performance in terms of PDP and PNBP compared to conventional CSRO. The performance of the CSROs is also observed and compared with respect to the variations in process-voltage-temperature (PVT) parameters.

This article investigates the effects of different gate coupling voltage and gate voltage duration on electro-static discharge (ESD) performance of several NMOS-based power rail protection devices. Through simulation and transmission line pulse (TLP) test, it is found that there are two modes in the conduction process of the main clamping NMOS: channel conduction state and parasitic NPN conduction state. Different gate voltage and duration bring the two conduction states different proportions in the whole working process, which give the device very different robustness. The results show that under the condition of small gate voltage and long duration and the condition of large gate voltage and short duration, the device can achieve optimal performance because the trigger voltage can be reduced, and the parasitic NPN can be turned on in time to release most of the current.