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The work describes design and simulations of a three input NAND gate using quantum dot semiconductor optical amplifiers for the first time as far as author's knowledge goes. Both cross gain modulation and cross phase modulations implement the NAND operation in a modified manner. Amplitude modulation, extinction ratio, relative eye opening, contrast ratio, etc. are optimized in terms of control power and their dependence on amplified spontaneous noise has been investigated for three different unsaturated gains of the QDSOA. These parameters show efficient performance for unsaturated gains 20 and 30 dB. REO value more than 99% and Q value more than 16 dB ensure practical feasibility of the logic gate proposed. [ABSTRACT FROM AUTHOR]

All optical logic gates are building blocks for all optical data processors. One way of designing optical logic gates is using threshold switching which can be realized by combining an optical resonator with nonlinear Kerr effect. In this paper we showed that a novel structure consisting of nonlinear photonic crystal ring resonator which can be used for realizing optical NAND/NOR and majority gates. The delay time of the proposed NAND/NOR and majority gates are 2.5 ps and 1.5 ps respectively. Finite difference time domain and plane wave expansion methods were used for simulating the proposed optical logic gates. The total footprint of the proposed structure is about 988 μm2. [ABSTRACT FROM AUTHOR]

For digital applications, researchers are exploring the use of Tunnel Field-Effect Transistors (TFETs) as an alternative to Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). TFETs offer unique qualities that can be harnessed in digital applications. The presented work focuses on the Drain Engineering Dual Metal Gate based Charge Plasma TFET (DE-DMG-CP-TFET) and its ability to implement various logic functions utilizing 2D device simulations. This simulation refers to employing computational tools to analyze electronic devices in two spatial dimensions, considering parameters such as current-voltage characteristics, electric field analysis, and energy band diagrams. This simulation-based approach enables a comprehensive understanding of the device's operation under different conditions and facilitates the optimization of its performance. The simulations provide insights into the impact of design parameters, material properties, and device configurations on its functionality. By leveraging the ambipolar nature and gate-controlled tunneling capability of TFETs, compact logic functions can be realized by carefully designing the gate-source overlap and selecting an appropriate silicon body thickness. This research highlights the potential of TFETs in compact logic implementation and demonstrates the value of two-dimensional device simulations in understanding device behavior and optimizing performance. It is demonstrated that by biasing the two gates individually, a single DE-DMG-CP-TFET may implement logic operations like OR, AND, NAND and NOR. Using a gate-source overlap (LOV) and picking the right silicon body thickness are crucial for obtaining distinct logic functions from a DE-DMG-CP-TFET. For digital applications, researchers are looking into Tunnel Field-Effect Transistors (TFETs) as possible substitute for MOSFETs. Utilizing two-dimensional device simulations, a Drain Engineering Dual Metal Gate-based Charge Plasma TFET (DE-DMG-CP-TFET) is presented to implement various logic functions. It is demonstrated that by biasing the two gates individually, a single DE-DMG-CP-TFET may implement logic gates operation. Using a gate-source overlap and picking the right silicon body thickness are crucial for obtaining distinct logic functions from a DE-DMG-CP-TFET [ABSTRACT FROM AUTHOR]

In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.

This paper proposes a procedure to analyze digital circuits in both Carbon Nanotube Field-Effect Transistors (CNTFET) and Complementary Metal-Oxide-Semiconductor (CMOS) technology for the purpose of comparison. The procedure is applied to study a NAND gate, with an emphasis on its applicability to analyze other digital circuits. To demonstrate this versatility, the procedure is also used to analyze a NOT gate in both CNTFET and CMOS technology. The paper presents the improvements achieved with CNTFET technology compared to CMOS. All simulations are conducted using the Advanced Design System (ADS) software, compatible with the Verilog-A programming language. Results from the analysis reveal that CNTFET technology exhibits superior performance, particularly at lower supply voltages. The paper also quantifies the differences in propagation delay, with CNTFET technology outperforming CMOS technology by a significant margin. [ABSTRACT FROM AUTHOR]

Decoders are one of the significant peripheral components of static random-access memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate biasing to vary the threshold voltage. Row and column decoders are designed and simulated in H-Spice. The leakage power is calculated and compared for both the methods. The NAND gate implemented by Method-1 and Method-2 provides a maximum leakage power savings of 87.67% and 90.81% respectively. The maximum leakage power savings of 96.76% and 98.74% is reported for the row decoder implemented by Method-1 and Method-2 respectively. Similarly, Method-1 gives maximum leakage power savings of 97.09% and Method-2 gives a savings of 99.11% for column decoder. The difference in leakage power savings of Method-1 and Method-at same threshold voltage is 3.14%, 1.98%, and 2.02% for NAND gate, row decoder and column decoder respectively. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Harbin Institute of Technology. Social Sciences Edition / Haerbin Gongye Daxue Xuebao. Shehui Kexue Ban is the property of Harbin Institute of Technology and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Compared with classical algorithms, quantum algorithms can show the advantage of exponential speedup in solving some problems. Solving the NAND‐Tree problem is a typical example, which can be speed up exponentially by quantum walk. This scheme is groundbreaking due to the universality of the negative‐AND (NAND) gate. In fact, the NAND gate is also universal for classical computation, making it an important target for development. Herein, the quantum NAND‐Tree onto the classical circuit network is mapped and a new type of classical logic circuit with the NAND gate that can perform the quantum algorithms is designed. These classical logic gates that are designed have exponential speedup functions compared with conventional ones. Because classical circuit networks possess good scalability and stability, the present scheme is expected to have potential applications for information processing in the era of big data. [ABSTRACT FROM AUTHOR]

Compared with classical algorithms, quantum algorithms can show the advantage of exponential speedup in solving some problems. Solving the NAND‐Tree problem is a typical example, which can be speed up exponentially by quantum walk. This scheme is groundbreaking due to the universality of the negative‐AND (NAND) gate. In fact, the NAND gate is also universal for classical computation, making it an important target for development. Herein, the quantum NAND‐Tree onto the classical circuit network is mapped and a new type of classical logic circuit with the NAND gate that can perform the quantum algorithms is designed. These classical logic gates that are designed have exponential speedup functions compared with conventional ones. Because classical circuit networks possess good scalability and stability, the present scheme is expected to have potential applications for information processing in the era of big data.

This paper studies the problem of data access at the receiver with large bit error rate and low quality factor. Due to this issue the information got inaccurately at the receiver side, the data should have high quality factor and low bit error rate to be simple of identification at the receiver when using the gates. The nonlinear properties of the semiconductor optical amplifier are utilized to accomplish the Boolean variable based math work, in which AND, NAND, and OR gates potentially used to endorse the Boolean function. Through blend this gates together any Boolean function can be accomplished and utilized to perform optical signal processing. The quality factor and BER are measured by utilizing the eye diagram analyzer, the state of the output bit and also shaped by the oscilloscope visualizer in optiwave simulation program. These models can be used for wavelength converter, header recognition, parity checking, binary addition, packet-header modification, encoding and encryption with pattern matching, and data encryption with high speed and high quality factor. [ABSTRACT FROM AUTHOR]

Tailoring MoS2 into nanoribbon (NR) provides an efficient regulation of the electrical property. Herein, high-performance MoS2 transistors are fabricated by optimizing the channel height, width, and length. The electrical performance of the device is improved due to enhanced gate modulation capability from the quasi-3D channel geometry. The devices obtain a high ON-state current of $496 ~\mu \text{A}\,\cdot \, \mu \text{m}$ −1 while offering appropriate field-effect mobility of 52.6 cm2V−1s−1 as the height and width of MoS2 NR are fixed to 20 ± 3 nm and 130 ± 10 nm, respectively. The high performance and desirable current saturation are promising to construct robust logic gates. The NOT and NAND gates are assembled based on an individual MoS2 NR. The inverters demonstrate a voltage gain of −17.8 and a total noise margin of nearly 75%. This work provides an alternative strategy to fully take the advantage of 2-D materials in logic electronics circuits. [ABSTRACT FROM AUTHOR]

Molecular circuits have been used in a wide range of diagnosis applications, from the detection of chemical molecules in solution to the complex processing of cell surface receptors. One of the most important challenges of these systems is the lack of distinguishability between different circuit states when each circuit state represents a specific disease. In this work, we designed a molecular amplification circuit with borderline Boolean states that each state can be distinguished with different color intensity. For this purpose, two DNA complexes and four DNA hairpin structures were designed to detect miR-218 and miR-215 biomarkers. One of the designed DNA complexes has two G-quadruplex structures and the other has only one G-quadruplex structure. In the absence of the inputs, all three G-quadruplex structures are active and produce a high-intensity signal, while in the other three states, including the presence of miR-218, the presence of miR-215, and the presence of both inputs, respectively, one, two, and zero G-quadruplex structures are active. Therefore, the designed system can identify two different biomarkers simultaneously with different signal ratios, which can easily distinguish the different states of the circuit. This strategy is very promising to identify diseases in which any combination of biomarkers leads to a particular disease. [ABSTRACT FROM AUTHOR]

- The advent in semiconductor technology paved the way for electronic industry to place in front row. The nanosheet (NS) device is a type gate all around (GAA) architecture provides an excellent gate electrostatic to suppress the short channel effects (SCEs) and scale it further below sub-7nm technology node. This paper provides a complete design insight from device to circuit of a two sheet NSFET with geometrical variations. All digital and analog/RF parameters are extracted and analyzed based on gate length (L G), sheet thickness (T N S ), sheet width (W N S ), and spacer material variations. As L G is varied from 8 nm to 12 nm, I O N / I O F F is enhanced from 0.249 × 108 to 2.86 × 108 due to improved gate control over the channel region which is also reflected in DIBL to 40.82 % whereas, at lower L G analog/RF metrics are better. The T N S play a vital role in device characteristics, as T N S decreases the chance of interaction of electric field from source to drain decreases owing to full volume conduction and thereby ameliorated performance of JL NSFET. As T N S is varied from 7 nm to 5 nm, all electrical characteristics are improved and analog/RF parameters g m , A v , f T , TFP and GTFP are improved to 10.3 %, 18.4 %, 12.1 % 18.5 % and 54.04 %, respectively. Increase in W N S from 10 nm to 20 nm results into increased effective width of a device, it leads to higher I O N current which further impacts on electrical and analog/RF parameters. The DIBL, g m , f T , GFP, TFP and GTFP are enhanced to 63.7 %, 37.9 %, 34.9 %, 9.7 %, 33.5 %, 9.1 %, respectively. The spacer materials are varying from Al 2 O 3 (k = 18), HfO 2 (k = 22), ZrO 2 (k = 25) to TiO 2 (k = 44), the electrical characteristics are better at higher-k whereas analog/RF performances are superior at lower-k. Further, digital circuit elements NOT, NAND and NOR gates are designed, simulated and the delays are examined as 4.25ps, 6.45ps and 5.12ps, respectively. The N M L and N M H of NOT gate are noticed as 295 mV and 280 mV at 0.7 V of supply voltage. Furthermore, a common source (CS) amplifier is also simulated and gain of 3.3 is noticed. The aforementioned analysis revels the JL NSFET is best suitable candidate for future nanoscale applications. [ABSTRACT FROM AUTHOR]

Compute-bound problems like matrix-matrix multiplication can be accelerated using special purpose hardware scheme such as Systolic Arrays (SAs). However, processing elements in SAs have a long critical path delay, thus limiting the performance benefits of SAs. This paper presents a scheme to achieve high-performance matrix multiplication using SAs. Two approximate matrix multiplier designs (Ax1 and Ax2) of variable accuracy/power are proposed. The proposed designs (8-bit) achieve an improvement of 32% in terms of critical path delay and for scale-up variants (32-bit) the improvement in delay and energy scale upto 64% and 51%, respectively. Moreover, Ax1 and Ax2 have a reduced power-delay product compared to previous approximate matrix multiplier designs. This leads to an improved resolution of the prior accuracy-energy Pareto front; therefore, we define a new Pareto front for approximate matrix multipliers. As a case study, the discrete cosine transform is evaluated. Ax2 achieves the best quality-power trade-off and it exhibits a 5% degradation in structural similarity index (SSIM) with a power saving of 28%. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCAs) are one of the most significant state-of-the-art technologies that have exhibited the potential to replace the complementary metal oxide semiconductor. QCA offers a variety of benefits over its conventional counterpart, including size, latency, and energy consumption. Meanwhile, multiplexers are crucial to the design of arithmetic and logic circuits, and NOT-AND (NAND) gates are universal gates that allow the design of any circuit. In this paper, we propose a new multiplexer based on three NAND gates in QCA. De Morgan's law is used to derive new equations and to design multiplexers using only NAND logics. The proposed circuit is designed and verified not only to minimize time and space complexity but also to minimize energy loss. Finally, we design an arithmetic circuit that is capable of performing various operations using the proposed multiplexer. [ABSTRACT FROM AUTHOR]

Reflective semiconductor optical amplifier (RSOA) is a versatile gain medium due to its double-pass characteristics compared to ordinary semiconductor optical amplifier. RSOA-based gain dynamics is utilized to design and analyze the NAND gate using soliton pulses for the first time. The simulation results shows that RSOA is a very good candidate for intensity encoded logic gates and processors. Extinction ratio, contrast ratio, amplitude modulation, bit error rate, and eye opening are calculated. Dependence of these performance indication parameters on control pulse energy is also investigated considering amplified spontaneous emission noise. This NAND gate can be used to design any optical logic processors in future, as it is a universal one. [ABSTRACT FROM AUTHOR]

The design of a 4‐bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue‐to‐digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one‐hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat‐Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power‐delay product of 3.335 fJ, energy‐delay product of 127.7305 Js and an intrinsic area of 4.753 mm2. [ABSTRACT FROM AUTHOR]

Memristor is a nanoscale electronic element with variable resistance that depends on the amount and direction of the charge passing through it. As a promising candidate, this memristive element opens up a new approach for the implementation of Boolean logic operations. In this study, a flexible logic unit circuit (LUC) based on a practical memristor model is proposed, which is able to perform the AND, OR, NOT, NOR, and NAND gate operations by different switch settings. Unlike existing memristor-based logic implementation, the initialisation is not necessary for the proposed method, and the total delay can be effectively reduced, especially for time-sequence inputs. Furthermore, the concept of the memristor-based logic network is developed by multiple memristor-based LUCs connected in series and parallel. The circuit simulation demonstrates that the presented logic network is capable of realising multi-input–multi-output logic operations with compact structure, high efficiency, and sufficient accuracy.