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We have successfully fabricated electronic and photonic components on the same substrate using a standard process offered by public silicon photonics foundry service. As we adopted the standard process parameters offered by A*STAR’s Institute of Microelectronics (IME), the design and fabrication of the n- and p-regions of the electronic devices are limited to the specific parameters optimized for creating optical waveguide modulators and photodetectors. In this work, we chose to fabricate and integrate Lateral Bipolar Transistors (LBJTs) and Junction Field Effect Transistors (JFETs) transimpedance amplifiers with Ge waveguide photodetectors, as well as on-chip photonic components such as grating couplers, submicron strip waveguides and PN depletion modulators. Our experimental results shows rectifying Ge photodiode characteristics and demonstrates full integration for sensing applications.

In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

Processible, predoped conducting polymer materials are now commonly formed using a polyelectrolyte backbone as a template material. This results in the conducting portion of the material being composed of a distribution of relatively short-chain oligomers with a corresponding distribution of saturated doping levels. We have investigated the effect of multiple ion doping compensation on the conduction properties of such materials by treating the individual chains as switchable conducting island sites in a percolation matrix. The results of one-, two-, and three-dimensional simulations are compared to experimental results. We show that the measured electrochemical control of material conductivity is best modelled by the simple one-dimensional case which reproduces the characteristic sigmoid-shaped curve. Our findings are consistent with quasi-1D hopping transport between sites, which is the dominant theory for conductivity in this class of materials.

We explore the monolithic integration of conventional electronics with SOI photonics using the commercial silicon photonics foundry technology offered by A*STAR&rsquo, s Institute of Microelectronics (IME). This process offers optical waveguide modulators and photodetectors, but was not intended to support transistors. We present the implementation of junction field effect transistors (JFETs) integrated with optical waveguides and photodetectors. A simple SPICE model is developed for the JFETs based on the available ion implant parameters, and the geometry feature size allowed by the technology&rsquo, s layout rules. We have demonstrated the monolithic integration of photonics and electronics circuits. This work could be useful for application in waveguide sensors and optical telecommunications.

Thin layers of nickel (Ni) and palladium (Pd) are used to form Schottky barrier photodiodes on silicon–on–insulator optical rib waveguides defined by the local oxidation of silicon technique. Optical loss and attenuation due to the metallic layers on the waveguides are estimated by simulations followed by experimental verification. Loss increases with increasing metal thickness until a plateau is reached at a thickness of approximately 50 nm. Higher optical loss is observed for the transverse magnetic mode compared to that for the transverse electric mode. The dark current density of all the devices is less than 10−6Acm−2 at 1 V reverse bias. The TM mode responsivity is 4.7 mA/W and 0.33 mA/W for 0.5 mm long Ni/nSi and Pd/nSi at 1310 nm wavelength, respectively. This work demonstrates great potential for simple sub-bandgap photodetectors for silicon photonics.

A radon monitor based on a 3 mm×3 mm alpha-detecting IC fabricated in a foundry CMOS process is reported. The alpha-detecting IC consists of a 16×16 array of pn junction diodes (sense diodes) that are precharged in reverse bias and then allowed to electrically float. Radon progeny is collected on the IC using an electrostatic concentrator. On-chip comparators detect the voltage change induced in a sense diode by an alpha particle emission from collected progeny. The comparator outputs are monitored by a microcontroller which processes the data and transmits it to a microcomputer using Bluetooth. The monitor has a sensitivity of 1.25 counts per hour per 100 Bq/m3 of radon activity. The monitor appears suitable for mass production at very low cost., 2016 IEEE Sensors Applications Symposium (SAS), April 20-22, 2016, Catania, Italy

Field-effect sensors with hafnium silicate gate insulators were fabricated following standard CMOS processes and compatible post-processes. The floating gates were functionalized with glycidoxypropyltrimethoxy silane and amine-terminated oligonucleotide probes. The pH sensitivity of the silicate surface decreased from 31.4 mV/pH to 24.6 mV/pH after functionalization due to passivation of a significant fraction of the amphoteric proton binding sites. A threshold voltage shift of 33 mV was observed as the buffer solution concentration changed from 0.015 M to 0.3 M after DNA probe molecule attachment. The hybridization caused a net increase in this shift of 3mV. With the help of a model which includes the solution of the Poisson-Boltzmann and proton site-binding at the gate, methods of achieving higher sensitivity are discussed., 214th ECS Meeting, October 12-17, 2008, Honolulu, HI

Palladium on n-type silicon Schottky barrier photodetectors have been integrated with SOI optical waveguides. The diodes gave optical responsivity of 330 nA/mW at 1310 nm. Dark current density is less than 2×10−8 Acm−2 at 1 volt reverse bias.

This paper reports on the development and testing of a direct reading radon detector assembled from consumer electronics at very low cost. An electrostatic concentrator constructed by metalizing a plastic funnel is used to focus charged radon progeny onto the exposed surface of an optical image sensor from a webcam. Alpha particles emitted by the collected progeny strike the image sensor, generating sufficient charge to completely saturate one or more pixels The high voltage required by the concentrator is generated using a simple Cockcroft-Walton charge pump. A personal computer is used to analyze the webcam data. Alpha particles were counted at a rate of 5.2 counts/ hour at a radon concentration of 159 Bq/ m3., Photonics North 2013, Monday 3 June 2013, Ottawa, Canada, Series: Proceedings of SPIE; no. 8915

The LOCOS technique for formation of SOI optical waveguides has been extended to produce low-loss photonic wire channel waveguides with deep submicron dimensions using a very simple process. © 2011 IEEE., 8th IEEE International Conference on Group IV Photonics, GFP 2011, 14 September 2011 through 16 September 2011, London

Ni/nSi and Pt/nSi Schottky barrier diodes have been integrated with SOI optical waveguides produced using the Local Oxidation of Silicon (LOCOS) technique. The smooth, nearly planar topography provided by LOCOS allows the Schottky metal to overlap the waveguide rib while still giving low leakage current densities (

The first solar cells using in-situ doped polysilicon contacts to form both emitter and back surface field (BSF) regions are reported. The use of polysilicon contacts permits extremely low thermal budget processing (maximum 850°C 5 sec for dopant activation), preserving substrate properties. The effectiveness of the BSF is best seen with backside illumination, where the photocurrent under natural sunlight is found to be over 30% of that obtained with frontside illumination, even though the substrate thickness is comparable to the minority carrier diffusion length. The applicability of the structure to bifacial operation is considered.

In this paper, we investigate athermal and low propagation loss silicon-on-insulator (SOI) rib waveguides. Propagation losses have been modeled for different dimensions of ridge waveguides achieving good agreement with experimental measurements. At certain waveguide widths, it is possible to obtain low propagation losses for both TE (transverse electric) and TM (transverse magnetic) modes. Racetrack ring resonator structures based on ridge waveguides covered by a polymer have been fabricated, aiming for an athermal design and therefore, a very small temperature dependent wavelength shift. Design guidelines for temperature insensitive and small propagation loss ridge waveguides are presented in this paper together with experimental data.

X-parameters provide a powerful and eminently practical solution for interoperable measurement, modeling, and simulation of nonlinear microwave and RF components. UsingX-parameters to do large-signal measurements has been brought into the spotlight. This paper introduces a newX-parameter application: measuring large-signal behaviour of pulse-compression nonlinear transmission lines (NLTLs). A specially configured Nonlinear Vector Network Analyzer (NVNA) was used to measure theX-parameters in the frequency-domain, and then the measured data was transformed into a nonlinear time-domain waveform. The results show both rise-time and fall-time reduction (double-edge compression) as expected and indicate that this newly developedX-parameter method implemented with an NVNA could correctly predict NLTLs' pulse-compression performance.

Rapid thermal oxidation is applied to simultaneously grow the gate and capacitor oxides in a mixed analog/digital metal oxide semiconductor (MOS) process with polysilicon-polysilicon capacitors. This technique allows the use of a high temperature for polysilicon oxidation, which provides increased dielectric strength while avoiding diffusion of the active device boron threshold adjust implant and associated short-channel effects in p-channel transistors

This paper investigates an evanescent field refractive index sensor based on a planar waveguide silicon-on-insulator (SOI) unbalanced Mach-Zehnder interferometer structure. The key element used for enhancing the sensitivity of the device is a waveguide structure that contains perforations through its core guiding layer. Three-dimensional numerical solution of the wave equation was used to determine optimal device dimensions and model device behavior. Devices were then fabricated in 3.4 μm thick SOI material and optically characterized. It was found that the perforations in the waveguide increased its sensitivity to refractive index changes in the cladding by a factor of two. The sensitivity of the device, which contained a 100 μm long sensing region, was estimated to be 2.2 nm shift in the interferometer output spectrum per unit refractive index change of the cladding. It is expected that further optimization of the perforated waveguide structure will result in a significant increase in sensitivity.

The Local Oxidation of Silicon (LOCOS) technique is used to define optical rib waveguides in silicon-on-insulator (SOI) material. This process, commonly used for device isolation in purely microelectronic CMOS processes, results in a nearly planar surface suitable for integrating optical and electronic components on the same chip. Optical mode simulation was used to determine rib geometries suitable for single-mode propagation and minimizing birefringence in the 1550 nm optical telecommunications band. Test devices were then fabricated in SOI material with a Si film thickness near 3 microns. Growth of a 1 micron field oxide by wet oxidation yielded a 0.5 micron rib height. As-drawn rib widths ranged from 3 microns to 5 microns, giving final rib widths ranging from 2 microns to 4 microns after oxidation. Cutback optical testing of 3 microns drawn width ribs showed the loss to be less than 1 dB/cm at 1555 nm. Unbalanced Mach-Zehnder interferometers with Y-splitter junctions were also fabricated and tested with input wavelength swept from 1470 to 1580 nm and showed an extinction of 6-10 dB, demonstrating the ability of the LOCOS rib technique to produce more complex waveguide devices.

This paper presents coplanar waveguide structures with low attenuation and slow-wave reduction implemented in standard silicon technologies and suitable for frequencies of up to 40 GHz. Optimization and modelling of slow-wave coplanar waveguides (SW-CPW) is provided here and compared to standard CPW models. An on-chip SW-CPW attenuation of 0.25 dB/mm at 40 GHz is obtained, compared with 2.8 dB/mm for a standard CPW. As an application, a non-linear transmission line (NLTL) was designed using SW-CPW sections. This NLTL can sharpen the pulse rise time by 75%. This work demonstrates the feasibility and advantage of using SW-CPW techniques to build all-silicon pulse-compression NLTLs using commercial silicon foundry processes.

Interdigitated metal-semiconductor-metal (MSM) photodetectors operating at 1550 nm were fabricated by depositing metal contacts on top of polycrystalline silicon (polysilicon), which was deposited by a variety of techniques. The highest responsivity was 0.66 mA/W, corresponding to an external quantum efficiency of 0.16%, obtained from a 2 μm thick polysilicon sample. Using Raman spectroscopy, it was found that polysilicon with grain sizes between 6 nm and 13 nm provides the best photoresponse at 1550nm.

The current trend towards integrating CMOS circuitry and photonic devices on silicon-on-insulator (SOI) wafers into monolithic optoelectronic circuits requires modification of the traditional rib waveguide to provide a planar surface. One possible modification involves creating a trench on either side of the rib and then filling this trench with a planarizing oxide. The resulting planar surface is much more compatible with the photolithographic systems required to print the small dimensions found in state-of-the-art CMOS. We report the fabrication of prototype trench-isolated waveguides, measurement of optical performance and comparison with simulation. 2.5 μm thick Si film was utilized with 0.5 μm deep trenches ranging from 1 to several microns in width. Rib widths ranged from 2 μm to 3 μm (the maximum value providing single mode propagation). Allowed modes were determined with FEMLAB, while beam propagation was studied using Optiwave BPM. Simulation indicated mode confinement would be lost for trench widths less than 1.5 μm. The narrowest trench width which could be fabricated was 2.0 μm, and qualitative optical testing shows good mode confinement to the central rib for a trench geometry greater than 3.0 μm.

We show that stress engineering can be used to adjust the SOI waveguide birefringence to the stringent polarization tolerances expected of commercial devices, using only standard silicon processes. With decreasing device dimensions and high index contrast the waveguide birefringence becomes increasingly sensitive to device geometry. As a result, it is almost impossible to eliminate waveguide birefringence by adjusting waveguide profile alone. This paper presents, for the first time, a systematic study of the stress-induced birefringence of SOI waveguides. Through full-vectorial finite-element simulations, we investigate the variation of stress-induced birefringence with waveguide core and cladding geometries. It is found that the stress-induced birefringence is determined by the waveguide cross-section, the upper cladding layer thickness, and film stress levels. We develop a waveguide model that predicts the total waveguide birefringence and guides the post-fabrication processing steps. An experimental demonstration of a polarization insensitive SOI arrayed waveguide grating (AWG) demultiplexer is presented. The polarization dependent wavelength shifts measured experimentally agree well with the simulations.

Rapid thermal annealing of in situ phosphorus-doped polysilicon emitter transistors in the temperature range 850–1000 °C greatly reduces the emitter resistance RE at the cost of a slight increase in hole back injection, seen as a decrease in emitter Gummel number GE. Annealing at 1000 °C for 5 s gives low emitter resistance (RE ≈ 100 Ω μm2) while maintaining good suppression of back injection (GE ≥ 1014 scm−4). Annealing at temperatures below 1000 °C fails to reduce RE sufficiently for use in high-speed devices.

A new lightly doped drain (LDD) metal oxide semiconductor field effect transistor structure is presented that provides substantial overlap of the gate over the n− region independent of the n− junction depth. This structure uses polysilicon spacers to replace the oxide sidewall spacers used in a conventional LDD device. The structure has been given the acronym "AGAIN," for added gate after implantation of n−.

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Active polymer materials allow the construction of cheap, flexible circuitry using simple printing techniques. A process and devices capable of performing a variety of circuit functions using electrolytic technology have been developed. The process is based on a simple screen printing system that allows the formation of multilayer circuitry with no active layer-to-layer alignment. Using this system, it has been possible to build a number of circuits utilizing transistor-like electrolytic devices and other active devices with novel topologies. Models have been developed that provide the ability to simulate arbitrary device geometries using a standard-cell approach for the basic elements required. These have allowed accurate simulation of the dynamic response of a number of device structures to be performed.

We present the implementation of a novel wavelength independent polarization splitter on a silicon-on-insulator platform. The waveguide splitter is based on a zero-order arrayed waveguide grating (AWG) configuration. The splitting function is realized by employing cladding stress-induced birefringence. The device demonstrated a TE to TM splitting ratio better than -15 dB over a 20 nm tuning range centered around lambda=1550 nm and better than -10 dB over our entire accessible wavelength range from lambda=1465 nm to 1580 nm. The highest splitting extinction ratio achieved was -20 dB. To our knowledge, this is the first reported passive broadband polarization splitter based on AWG.

High quality broadband passive components are needed for MMIC/MIC in silicon. Coplanar waveguides (CPW) provide an effective way to implement passives in microwave ICs. Silver “fat” wires in the back end interconnects, used for CPW fabrication, will reduce the bulk resistive loss in metallization to the lowest possible level, which is vital to minimize noise. Electromigration, electrochemical migration, and agglomeration issues are not a problem for silver microwave passive components, because of their coarse dimensions and the low current densities encountered in these structures. In this work Ag and Cu CPWs were designed, fabricated, and tested. Silver CPWs showed a 2–3Ω∕cm improvement in resistance over copper devices at 20GHz.

The fabrication of junctions with very low minority-carrier injection ratios and reasonably good diode characteristics on p-type silicon is reported. These junctions were formed by growing an ultrathin oxide layer on a monocrystalline substrate, depositing polysilicon heavily doped in situ with phosphorus over the oxide, overlaying the polysilicon with aluminum, and then annealing the resulting sandwich structure at temperatures in the range 400–450 °C. The junctions can exhibit leakage current densities below 10−6 A∙cm−2 at moderate reverse bias and reverse breakdown voltages in excess of 20 V. The absence of minority-carrier injection has been demonstrated by diode reverse recovery transient measurements and by the fabrication of bipolar transistors employing these junctions as emitters.