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This contribution describes developments in the use of numerical optimization techniques as part of a package whose function is to generate silicon-level layout for general analog functional modules from high-level specifications. The investigation is using switched-capacitor filters as a case study that is representative, in terms of its associated physical layout problems, of many classes of analog circuits.

The Electronic Design Education Consortium (EDEC) is funded under the Teaching and Learning Technology Programme (TLTP). The objective of EDEC is to develop computer based learning (CBL) material to support electronic design. This paper describes the philosophy adopted by the team at the University of Essex in developing courseware for analogue and digital design. In order for CBL courseware to provide an effective method for student learning, the authors believe that the student must be involved interactively and that care should be taken to avoid producing just an electronic form of textbook. >