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A 58-nm 2-Gb multi-level cell (MLC) B4-Flash memory with flexible multisector architecture has been developed, which can be realized by unique features of B4-Flash with P-channel cell; large-data programming with small cell current thanks to back bias-assisted band-to-band tunneling-induced hot electron (B4-HE) injection mechanism, simple erase sequence without over-erase problem. In this architecture, each program and erase unit size can be extended from 256 B to 4 KB and from 256 KB to 4 MB, respectively, by utilizing 8 sectors & 2 banks simultaneous operation, and consequently 10 times faster 3.7 MB/s rewrite speed than that of conventional NOR flash can be realized by 4 KB / 980 $\mu \text{s}$ programming and 4 MB / 80 ms erasing. A fast 110-ns random access with enough read margin has been achieved by simultaneous parallel sensing at 3 op-amps with cell-bias compensation scheme. This paper proves that B4-Flash can be a candidate for various applications which need both fast rewrite speed and fast random access as a fast rewritable NOR-type flash with MLC capability and scalability.

This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabricated using a 90 nm flash process, and single-pulse program and erasure cycling has been confirmed up to one million, with keeping programming time of 10 us and erase time of 1 ms. It is demonstrated that the excellent capability of more than 10 years data retention at 150 C. In addition, a fully designed 90 nm B4-EEPROM macro specification has been investigated, and the unit cell size can be designed 57F2, which is a half those of conventional EEPROM cell size of 80-100F2.

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed, where a bipolar transistor embedded in the source region of the cell amplifies cell-read-current and acts as a select transistor. With this cell, not only a very low 1.5 V non-word-line-boosting read operation, but also a sector-erase operation are successfully achieved with only a small cell-size increase over the conventional NOR cell. Moreover, this cell technology maintains all the advantages of the P-channel DIvided-bit-line NOR (DINOR) flash memory.

A 256-Mb flash memory is fabricated with a 0.25-/spl mu/m AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm/sup 2/ die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell V/sub th/. The effect of adjacent memory cell's V/sub th/ is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell V/sub th/. In the -5-75/spl deg/C range, memory threshold V/sub th/ deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector.

The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-/spl mu/m-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 /spl mu/s/512 byte) and a low current consumption of less than 250 /spl mu/A were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 10/sup 6/ program/erase cycles, and window narrowing and G/sub m/ degradation were found to be very small even after 10/sup 6/ cycles. It is thought that the BBHE injection point contributes to the G/sub m/ stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories.

It is found, even at room temperature, that hole fluence to breakdown Q/sub p/ of wet oxides is not a constant value for different oxide fields, but has a strong stress-electric-field dependence. Based on the neutral trap-generation characteristics related to SILC, this oxide-breakdown behavior dependent on the stress-electric field is analyzed. A novel model is proposed in which oxide breakdown is triggered when the current level of steady-state SILC via electron tunneling between traps reaches a critical value. From the spatial distribution of traps, we have concentrated on the critical trap pair whose electron-tunneling probability has the smallest value in the middle of the SiO/sub 2/ films. To verify this model, the convoluted trap density which is related to the electron-tunneling probability between the critical trap pair is investigated. As a result, it is found that this convoluted trap density remains constant regardless of stress-electric field and oxide thickness. This means that this convoluted trap density is a universal parameter for oxide breakdown.

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the-current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components.

In the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress, three reproducible stress-induced leakage current (SILC) components have been found for the repeated unipolar gate-voltage scans in 9.2 nm wet oxides. To clarify the mechanisms of these current components, a quantitative analysis has been developed. By precisely modeling the phonon assisted tunneling process, it has been shown that the E-J and t-J characteristics of the reproducible current components can be completely simulated as electron tunneling processes into the neutral traps, each with a single trap level. From this analysis, the physical parameters of the traps have been estimated with a reasonable degree of accuracy. Furthermore, the increase in distribution of the neutral trap density toward both the SiO/sub 2/ interfaces has also been estimated.

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components.

Using a newly proposed method for estimating the neutral trap density, generation characteristics of the neutral trap during various stress types have been investigated. From the analysis of the trap-generation kinetics, two types of trap generation closely related to holes have been identified. At the first stage of stress application, holes interact with the pre-existing structural origins of the neutral traps, then the neutral traps are generated. Influence of hole energy on this type of trap generation is also identified. After that, as holes pass, they also create the structural origins of the traps. The holes interact with these structural origins and the neutral traps are generated as a secondary effect. Thus, the increase in the neutral trap density shows up clearly with increase in the hole fluence. The stress-strength dependence of the increase in the neutral trap density can also be interpreted in terms of the influence of hole energy on the trap generation.

This paper describes a 58nm gate length 512Mb B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory, which is the smallest gate length NOR until now. 58nm gate length cells have been fabricated by 90nm process utilizing gate slimming technique. 58nm B4-Flash cells have been confirmed its sufficient performance compared to those of 90nm B4-Flash cells for NOR operation. B4-HE programming scheme, in which the voltage between drain and source sets to 1.8V, allows more aggressive gate length scaling than that for conventional CHE programming NOR, consequently gate length has been successfully scaled down to 58nm.

This paper describes million cycling capability of B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory with sufficient data retention characteristics, evaluated by mega bit level statistics using actual 512Mb chips. 512Mb B4-Flash chips fabricated by 90nm process have been confirmed its excellent million cycling endurance without fatal degradation of program/erase performances. Retention capability after one million-cycling has been also evaluated and confirmed that B4-Flash has achieved sufficient retention characteristics for high cycling SSD with long term data retention applications, much superior to JEDEC standard criterion. These results show its suitability and applicability of B4-Flash to high end Tier0 class SSDs (Solid State Drives).

A memory array architecture and row decoding scheme for a 3 V only DINOR (divided bit line NOR) flash memory has been designed. A new sector organization realizes one word line driver per two word lines, which is conformable to tight word line pitch. A hierarchical negative voltage switching row decoder and a compact source line driver have been developed for 1 K byte sector erase without increasing the chip size. A bit-by-bit programming control and a low threshold voltage detection circuit provide a high speed random access time at low V/sub cc/ and a narrow program threshold voltage distribution. A 4 Mb DINOR flash memory test device was fabricated from 0.5 /spl mu/m, double-layer metal, triple polysilicon, triple well CMOS process. The cell measures 1.8/spl times/1.6 /spl mu/m/sup 2/ and the chip measures 5.8/spl times/5.0 mm/sup 2/. The divided bit line structure realizes a small NOR type memory cell. >

This paper describes a 90nm Logic NVM "eCFlash", which can be embedded in standard CMOS process without any mask adder and any process modification. In the eCFlash element, the charge is stored in the side spacer region of CMOS transistor, consequently its charge loss process is not influenced by the leakage current through the gate oxide and surface leakage current on the side spacer, which is the most serious charge loss issues of the conventional single poly type floating gate NVM. It is shown that the intrinsic retention capability of 90nm eCFlash element is more than 10 years at 125C after 10k cycling.

This paper reports 90nm embedded B4-Flash technology and its superior performance and reliability. Embedded B4-Flash has been implemented to certain 90nm CMOS process and fabricated its 16Mbit test array chip. B4-Flash superiority of high speed program and erase, high reliability has been confirmed by evaluating the 16Mbit test array chip and single bit test vehicle. Direct comparison of the retention reliability between B4-Flash and conventional NOR fabricated in the same silicon has been carried out, for the first time. Superiority of B4-Flash reliability to conventional NOR, which has been pointed out in the previous paper has been confirmed, accordingly.

This paper describes a true 6F2 B4-Flash (Back Bias assisted Band-to-Band tunneling induced Hot Electron injection Flash) memory cell, which is one half of conventional NOR cell, for the first time as a floating gate NOR cell. 6F2 B4-Flash cells featuring a self-aligned STI and self aligned contact architectures have been fabricated by a 90nm process and was confirmed sufficient performance for NOR array operation. The cell size of 0.0486um2 of 90nm 6F2 is the smallest NOR cell in the 90nm generation. B4-HE programming scheme, in which the voltage between drain and source sets to 1.8V, allows more aggressive gate length scaling than for conventional CHE programming cells, consequently gate length has been scaled down to 78nm.

A 90 nm floating gate NOR B4-Flash memory with IF (F: minimum feature size) gate length cell has been investigated by using 64 Mbit test chip to evaluate the scalability of B4-Flash memory. 90 nm (=1F) gate length of memory cell is shortest in many NOR flash memories reported previously. Basic program and erase characteristics and robust program disturb immunity of B4-Flash memory utilizing NMOS select transistor in memory cell array have been demonstrated. Furthermore, to simplify the peripheral circuits and reduce a die size, a new charge pump circuit which can generate both positive and negative high voltage at a supply voltage of 1.8 V has been introduced.

This paper describes the reliability characteristics evaluation results of floating gate type B4-flash (back bias assisted band-to-band tunneling induced hot electron injection flash) with statistics. Data retention reliability of B4-flash with N+gate and P-channel memory cell utilizing B4-HE program and FN channel erase is evaluated extensively under bake temperature of -24C to 250 C up to 7000hrs after I k to 1M E/W cycles, by novel evaluation method of correlating Vt shifts and gm variations. No leaky bit failure can be seen in B4-flash with thicker than 9 nm tunnel oxide and the Vt shifts during retention bake is associated with electron detrapping and move into floating gate from tunnel oxide, which is verified by correlating Vt shifts and gm variations. Tunnel oxide thickness dependence on retention reliability is also studied and confirmed to have excellent retention characteristics under 150 C after 100 k cycling. In the case of 7 nm tunnel oxide thickness device, some leaky bits due to stress induced leakage current (SILC) can be seen even in B4-flash, nevertheless number of tail bits is remarkably reduced compared with that of conventional N+gate, N-channel NOR flash. According to all the obtained results show that B4-flash can achieve excellent retention reliability after cycling with high speed programmability.

A new logic NVM "eCFlash (embedded CMOS Flash)" has been developed without any additional process steps in a 0.25 um technology. In this architecture, a novel differential sense-latch cell with charge-trapping storage is adopted. This unique cell structure functions as a differential sense amplifier as well as a data latch, therefore mass data can be restored to each cell's latch simultaneously for static data output with high sensitivity and low power consumption. Furthermore the handling scheme of twice the breakdown voltage with novel charge pump circuit and high voltage driver is demonstrated. By utilizing these techniques, a highly reliable Logic NVM is realized; 100 K cycling endurance and data retention of 20 years at 150C.

A 1.8V 4 Mb floating-gate flash test chip utilizing back bias assisted band-to-band tunneling induced hot electron (B4-HE) injection mechanism (B4-Flash) has been fabricated. Double source line architecture (DSLA) and selective verifying method (SVM), applied to NOR arrayed B4-Flash enables to achieve 100 MB/s programming speed. The MLC capability of B4-Flash memory is also shown by realizing three levels of programmed Vth distribution with 0.8V width.

This paper demonstrates that B4-HE injection programming scheme can be easily evolved to a floating gate cell. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8 V. As a result, B4-flash can achieves high speed programming comparable to conventional NOR and high programming efficiency comparable to NAND flash at the same time. Basic operations of the floating gate B4-flash cells have been investigated. It is also confirmed that B4-HE injection programming provides very weak temperature dependency in comparison with CHE and FN injection, and does not have a negative impact to its reliability.

A p-channel SONOS flash memory cell technology, which provides excellent scalability and high programming efficiency for NOR architecture, has been developed. The cells named B4-Flash utilizing novel back bias assisted band-to-band tunneling induced hot-electron (B4-HE) injection is proposed. By applying a moderate back bias to the cell during programming, the bit-line voltage can be reduced below the supply voltage, 1.8V. Resulting that the B4-Flash, applicable to NOR architecture, achieves the gate length of 60nm, for the first time. Basic operation of the 50nm B4-Flash cell is also confirmed. Proposed B4-HE injection scheme realizes not only extreme scalability but also high programming efficiency for NOR type cell

A high-performance CMOS technology and cell structure for a megabit EEPROM are described. A novel EEPROM (electrically erasable programmable read-only memory) cell called a stacked floating gate with self-aligned tunnel region (SSTR) cell has been developed. A merged signal transistor structure has been developed to reduce the cell size. A sufficient cell threshold window is obtained in 2 ms at 16 V in both write and erase operation, using Fowler-Nordheim electron tunneling between the floating gate and the n/sup +/ region. The endurance of the cell is greater than 100000 erase/write cycles. An SSTR cell with a capacitive coupling ratio of 0.83 and a cell area of 30.4 mu m/sup 2/ has been implemented in a 1-Mb EEPROM. >

The optimum voltage scaling method is presented to achieve the low voltage operation of Channel Hot Electron type flash EEPROMs with high reliability, maintaining the constant performance and the constant tunnel oxide thickness. In this rule, the maximum electric field reduces with the constant tunnel oxide thickness for suppressing the oxide reliability problems. Moreover the electric field at tow level is fixed to keep the program and the erase time constant. Furthermore low voltage operation is achieved by increasing the coupling ratio and the p/sup 0/-pocket impurity concentration. This new rule is derived by clarifying the relation between the coupling ratio, the supply voltages and the sense levels from simple analytical equations. It is found that the flash performance is kept almost the same and the disturb characteristics is improved by following this methodology.

A high programming throughput p-channel DINOR flash memory with the BBHE injection programming method has been developed using 0.35 /spl mu/m CMOS process. This programming method realizes a high programming throughput of 8 nsec/Byte by utilizing 512 Byte parallel program operation with a low leakage current of less than 250 /spl mu/A. We have also demonstrated the good erase/write cycling endurance of 1/spl times/10/sup 5/. This process and device technology is very promising to the high performance 64 Mbit flash memories and future flash devices.

A novel EEPROM cell structure is proposed, which realizes a small cell size of 9.72 mu m/sup 2/ by using 0.8- mu m minimum feature size. The cell fabricated has sufficient cell threshold windows which extend to more than 5 V and program cell current of more than 80 mu A at a nominal program voltage of 12 V. The cell endurance is more than 10/sup 4/ erase/write cycles. A 4 Mb full-feature EEPROM can be acquired using this cell structure. The full-feature EEPROM cell has neither disturb nor overerasure problems, which are very difficult obstacles for flash EEPROM development, and can be operated by single and low-voltage external power supply. >

This paper describes a method for measuring the small current through the oxides on the order of 10/sup -20/ A or less using a floating gate MOSFET and the application results on flash memories with thin tunnel oxides. The method is based on accurate measurement of the threshold voltage of a floating gate MOSFET with no charge in the floating gate. We applied the method to flash memories to investigate the leakage current behaviour through thin tunnel oxides with very small areas (

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed and a very low 1.5 V non-WL (word line)-boosting read and sector-erase operations are successfully achieved. Moveover, this cell technology not only maintains the advantages of the P-channel DINOR (DIvided bit line NOR) flash memory, but also realizes the amplification of cell current, which is favorable for fast access operation.

Microscopic characteristics of stress-induced leakage current (mSILC) are studied by analyzing a large amount of data on the charge retention characteristic of stacked gate arrayed transistors. It is found that the SILC characteristics fluctuate in the microscopic regions, but they all fit the Fowler Nordheim (F-N) formula. Moreover, the coefficients /spl alpha/ and /spl beta/ of the F-N equation, which are conventionally constants, are obtained in this study by statistically analyzing mSILC characteristics, and are therefore distributed, with a strong exponential relation to each other. It is found that this correlation can be qualitatively explained by the analytical trap-trap transition model.

A 3.3 V only, block erasable 16 Mb divided bit-line NOR-DINOR flash memory has 47 ns random access time and 1 MB programming throughput. Power consumption in program operation is 60 mW. This memory is fabricated using a 0.5 /spl mu/m design-rule, double-layer aluminum, triple-layer polysilicon, triple-well CMOS. The effective memory cell is 1.4/spl times/1.35 /spl mu/m/sup 2/. 256B page buffer, optimized source/drain memory cell structure and efficient charge pump result in high speed, low power consumption, and low cost.

The structure of insulator layers, electrodes in capacitors, metal silicides in word and bit lines, and interfaces between these parts in a new type 4 M bit DRAM has been studied cross-sectionally by means of high resolution transmission electron microscope. The flatness of interfaces between different parts in the DRAM is from 0.3 nm to several tens of nanometers, and is related to the curvature of the interface and the materials constructing the interface. The metal silicides have been identified to be MoSi 2 in word lines and WSi 2 in bit lines. Some dislocations have been observed especially at the bottom regions of the trenches and whose Burgers vectors have been studied

A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-mm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved

An Ω-type energy filter has been fabricated in the column of a JEM-200CX 200 kV CTEM. Energy resolution of 4 eV at 200 kV, and energy dispersions of 2.6 μm/eV at 100 kV and 1.4 μm/eV at 200 kV are obtained. Also, unfiltered and energy-filtered images of aluminium-evaporated film on a carbon microgrid are shown comparatively.