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Multispectral plasmonic color filters were fabricated using nano-imprint lithography and benchmarked to similar filters fabricated with standard CMOS processing. The self-aligned process yields devices with narrow linewidths below 30nm and up to 50% transmission efficiency.

RFID tags are embedded in everyday objects providing extra functionalities and aiming to connect them to the cloud. Miniaturization of flexible RFID tags enables the integration into smaller everyday health, entertainment, food related objects, besides enhancing security and decreasing the cost. In addition, external sensor integration and readout enable new applications for the sensor tags. In this paper a miniaturized 2cm (1€ coin size) diameter antenna is combined with a flexible InGaZnO thin-film RFID chip operating at 3V and transmitting data at 7.3kHz. Moreover, the sharp threshold detection (

With the advent of the internet of things, flexible wearable devices are gaining significant research interest, as they are unobtrusive, comfortable to wear and can support continuous observation of physiological signals, helping to monitor wellness or diagnose diseases. Amorphous Indium Gallium Zinc Oxide (a-IGZO) Thin Film Transistors (TFTs) fabricated on flexible substrates are an attractive option to build such bio-signal monitoring systems due to their flexibility, conformability to the human body, and low cost. This paper presents a flexible electrocardiogram (ECG) patch implemented on foil with self-aligned IGZO TFTs, which is capable to acquire the ECG signals, amplify them and convert them to a sequence of bits. The analogue frontend has a measured input-referred noise of 8 μVrmsin the 1–100 Hz band. The system achieves experimentally 67.4 dB CMRR, 58.9 dB PSRR, and 16.5 MΩ input impedance at 50 Hz while using 1 kHz chopping. The signal from the electrodes is transformed to a 105.9-kb/s Manchester-encoded serial bit stream which could be sent wirelessly to a smart phone via Near Field Communication (NFC) for further elaboration. Power consumption is 15.4 mW for the digital and 280 μW for the analogue part. This contribution shows the fundamental steps to demonstrate intelligent plasters for biomedical applications based on flexible electronics providing an NFC-compatible digital output bit stream.

Capacitive touchscreens are increasingly widespread, featuring in mobile phones and tablets, as well as everyday objects such as cars and home appliances. As a result, the interfaces are uniquely placed to provide a means of communication in the era of the Internet of Everything. Here we show that commercial touchscreens can be used as reader interfaces for capacitive coupled data transfer. The transfer of data to the touchscreen is achieved using a 12-bit thin-film capacitive radio frequency identification tag powered by a thin-film battery or a thin-film photovoltaic cell that converts light from the screen. The thin-film integrated circuit has a 0.8 cm2 on-chip monolithic antenna, employs 439 transistors, and dissipates only 31 nW of power at a supply voltage of 600 mV. The chip has an asynchronous data rate of up to 36 bps, which is limited by the touchscreen readout electronics. ispartof: NATURE ELECTRONICS vol:2 issue:12 pages:606-611 ispartof: location:England status: published

Among the diverse and ever-expanding list of candidate technologies to serve the Internet of Everything, the rise of thin-film transistors on plastic as active components for ubiquitous ICs has been nothing short of meteoric. The stage for this explosion of interest was set by a pivotal advantage of the low manufacturing cost and ultrathin form factor, as demonstrated in recent prototypes of thin-film radio frequency identification (RFID) tags. Most RFID tags use inductive antennas, whereas, in this paper, capacitively coupled antenna is presented. Advantages of capacitive-coupled tags are the monolithic integrated antenna, the compact size, the additional security due to very short range of operation, and the localization and orientation abilities. The main circuit block of the tag, a 12-bit code generator, is demonstrated achieving only 160 nW of power dissipation at 0.3 V power supply transmitting data at 810 b/s on a 18 $\mu \text{m}$ -thick plastic substrate. The footprint of the monolithic integrated antenna is 1 cm2 and essentially defines the size of the full tag.

In this paper a capacitive coupled radio-frequency identification tag fabricated on flexible thin-film substrate is presented. The antenna of the tag is monolithic integrated “on-chip”. The footprint of the tag is defined by the size of the antenna, 1cm2. The tag operated at 24V applied reader voltage at a frequency of 1MHz. The achieved data transmission speed of the thin-film tag is 5.8kbps. The technology is a unipolar indium gallium zinc oxide (IGZO) self-aligned transistor architecture.

We present a QVGA (320x240 with 3 sub-pixel) top-emitting AMOLED display with 250ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with full barrier. The back plane process flow is based on a 7 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 80%. An integrated gate driver is shown that can be driven at operation speed equivalent to a 4k2k display at 100Hz

A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field-effect mobility of 12.0 cm2/(V.s), sub-threshold slope of 0.5 V/decade, and current ratio (I ON/OFF) of >107. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (-1.0 MV/cm) bias direction after extended stressing time of 104 s. We achieve a stage-delay of ~19.6 ns at V-DD = 20 V measured in a 41-stage ring oscillator. A top-emitting quarter-quarter-video-graphics-array active-matrix organic light-emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V-DD), the brightness of the display exceeds 150 cd/m2. A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) is presented. TFTs show field-effect mobility of 12.0 cm2/(V.s), sub-threshold slope of 0.5 V/decade, and current ratio (I ON/OFF) of over 107. In applications, a 41-stage ring oscillator with a stage-delay of ~19.6 ns (at V-DD = 20 V) and a top-emitting quarter-quarter-video-graphics-array (QQVGA) active-matrix organic light-emitting diode (AMOLED) display with 85 ppi (pixels per inch) resolution using five lithographic mask steps have been realized on a polyimide foil. Copyright 2015 Society for Information Display.

We present a QQVGA (160times120 with 3 sub-pixel) top-emitting AMOLED display with 85ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil. The back plane process flow is based on a 5 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 25%. For operation at 6 V supply voltage (VDD), the brightness of the display exceeds 150cd/m2. On the same substrate a 160 stage gate-driver was measured at FHD rate. cop. 2014 Society for Information Display.

We show an active artificial iris based on solely thin-film components, wherein several LCD elements are controlled a metal-oxide TFT and by powered by thin-film photovoltaics (TFPV). Key aspects for the driver are size and low power consumption. We demonstrate power consumption down to 25μW for the full iris.

In this study, we report high-quality amorphous indiunrv-galiium-zinc-oxide (a-IGZO) thinfilm transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back-channel-etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high-resolution backplanes and related circuits. The maximum processing temperature was limited to less than loS'C in order to ensure good overiay accuracy (

In this study, the authors report high-quality amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) fabricated using a new back-channel-etch (BCE) process flow on Polyethylene Naphthalate (PEN) foil. The BCE flow allows a better scalability of TFTs for high-resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165oC in order to ensure good overlay accuracy (< 1µm) on foil. The presented process flow differs from to previously reported by defining the Mo S/D contacts by dry etch prior to a-IGZO patterning. The TFTs show good electrical performance, including field-effect mobilities in the range of 15.0cm2/(V.s), sub-threshold slopes of 0.3V/decade and off-currents

We have developed a full color flexible top-emission AMOLED display with 80 ppi resolution using In-Ga-Zn-O TFT backplane on PEN foil under the maximum process temperature of 150 oC. Notwithstanding the low processing temperature, the TFTs with SiOx passivation layer show high reliability with VTH shift of less than 0.2 V at 10,000 seconds under bias-stress of -10 V. cop. 2013 Society for Information Display.

Poly-crystalline Silicon-Germanium is a promising structural material for post-processing Micro Electro-Mechanical Systems (MEMS) above CMOS due to its excellent mechanical and electrical properties when deposited at CMOS compatible temperatures. In this work an optimized process to deposit high quality crystalline poly-SiGe layers with low stress, low strain gradient and good within-wafer uniformity at a manufacturable throughput is developed. The process used to deposit the layers is based on a combination of CVD and PECVD SiGe depositions. Firstly, the CVD SiGe process has been extensively characterized to the extent that the influence of thickness, Ge concentration and B concentration on film stress and strain gradient is now well understood. Then the interaction between the PECVD SiGe and the underlying CVD layer has been investigated. This combined knowledge enables specific tailoring of the CVD-PECVD SiGe stack to give the desired strain gradient for a certain layer thickness.

Compared to traditional vacuum evaporation techniques for small organic molecules, organic vapor phase deposition (OVPD) possesses a extra processing parameter: the pressure of process gas Pch. Here, the influence of large Pch variations (from 0.1 mbar to atmospheric pressure) on pentacene thin film growth is explored. OVPD operation at higher Pch is characterized by lower carrier gas velocities and lower organic diffusivities. These result in an invariance of the material utilization efficiency over the entire pressure span and in an advantageous equilibrium evaporation regime in the source. An increase in Pch yields rough pentacene layers. Classical nucleation theory is applied to demonstrate how the pressure rise triggers homogeneous nucleation in the gas phase, causing the observed roughening. The use of lower deposition rates, higher dilution flow rates, and higher substrate temperatures result in the suppression of gas phase nucleation and the growth of smooth pentacene films at atmospheric pressure. Using these optimized conditions, state-of-the-art pentacene thin film transistors with saturation mobilities above 0.9 cm2/Vs are reproducibly fabricated. p-Type circuits are also made and a 19-stage ring oscillator with a stage delay of 51 μs at a supply voltage of 15 V is demonstrated. cop. 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

Short channel organic thin film transistors in bottom-gate, bottom contact configuration use typically gold metallization for the source and drain contacts because this metal can easily be cleaned from photoresist residuals by oxygen plasma or ultraviolet-ozone and allows also surface modification by self-assembled monolayers (e.g. thiols). Alternative low-cost bottom contact metallization for high performance short-channel organic thin film transistors are scarce because of the incompatibility of the bottom contact material with the cleaning step. In this work a new process flow, involving a temporary thin aluminum protection layer, is presented. Short channel (3.4 μm) pentacene transistors with lithographical defined and thiol modified silver source/drain bottom contacts (25 nm thick, on a 2 nm titanium adhesion layer) prepared according to this process achieved a saturation mobility of 0.316 cm2/(V.s), and this at a metal cost below 1% of the standard 30 nm thick gold metallization.

A poly-SiGe technology enabling a dense array of micro-cantilevers and tips on CMOS is demonstrated. Built from a dual-thickness structural layer, the cantilevers feature a very small initial bending and have a compliant torsional suspension with a stiffness of 3×10−10 Nm/rad. Sharp tips are formed in a low-temperature amorphous silicon layer by isotropic plasma etching. An electrical read/write system is formed by connecting the tip to the CMOS with a suspended platinum trace, running on top of the cantilever.

In this paper we report for the first time on the fabrication of very reliable CMOS-integrated 10 cm2 11 MPixel SiGe-based micro-mirror arrays on top of 6 level metal CMOS wafers. The array, which is to be used as Spatial Light Modulator (SLM) for optical maskless lithography [1,2,3] consists of 8 mum x 8 mum pixels which can be individually addressed by an analog voltage to enable accurate tilt angle modulation. The pixel density is almost double compared to the state-of-the-art [4]. A stable average cupping below 7 nm, an RMS roughness below 1 nm and long lifetime (>1012 cycles, no creep [5]) are demonstrated.

This work describes integrated readout electronics for on-panel fingerprint detection, focusing on two key building blocks: charge sense amplifier (CSA) and analog-to-digital converter (ADC). The CSA has been realized in a dual-gate self-aligned IGZO thin-film transistor (TFT) technology with channel length downsizing to 3µm, enabling 1.3mm bezel size for the peripheral readout electronics and 1fps readout of a 1-Mpixel 500dpi sensor array. The ADC has been realized in two different transistor technologies, IGZO and Indium-Tin-Zinc-Oxide (ITZO). The ITZO ADC achieves a sampling rate of 1kS/s, which is 7.5x faster compared to the IGZO ADC, due to the larger mobility of ITZO.

Flexible low-cost RFID/NFC tags have great potential to be embedded in everyday objects providing them a unique identifier or sensor readout facilitating the Internet-of-Everything, whereby a smartphone or tablet is the interface to the Internet-of-Things. The main challenge for flexible metal-oxide RFID tags is to fully comply with the ISO14443-A NFC standard to enable readout by standard NFC reader or handheld devices, due to the limited charge carrier mobility of the semiconductor and multiple sources of parameter variation caused by roughness, temperature and dimensional stability of the foils. Recent work by various groups [1–4] demonstrated only an incremental improvement in data rates from 50b/s to 396.5kb/s to be compatible with ISO14443 (105.9kb/s). In this work, we present a flexible metal-oxide NFC chip that is compliant with ISO14443-A, showcasing advancements on memory size, power consumption and a clock generation circuit.

The antenna of the tag is monolithic integrated ”onchip”. The footprint of the tag is defined by the size of the antenna, 1cm2. The tag operated at 24V applied reader voltageat a frequency of 1MHz. The achieved data transmission speed of the thin-film tag is 5.8kbps. The technology is a unipolar indium gallium zinc oxide (IGZO) self-aligned transistor architectur.

This paper presents an integrated, 1-transistor 1-RRAM cell based on amorphous InGaZnO flexible thin-film transistor technology. Both elements of the memory cell have been integrated side-by-side in a monolithic fashion on a flexible polyimide substrate. The thin-film transistor technology shows good uniformity figures, with a minimal channel length of 5 mu. The non-volatile memory technology is based on TaOx as material for Resistive Random Access Memory. The integratedalable memory device measures 5x5 mu2 and results in a memory window of 7.76. keywords: Thin film transistors,Logic gates,Metals,Substrates,Fabrication,memory,RRAM,metal-oxide,Layout,flexible,IGZO ispartof: pages:66-69 ispartof: 48th European Solid-State Device Research Conference (ESSDERC) vol:2018-September pages:66-69 ispartof: 48th European Solid-State Device Research Conference (ESSDERC) location:Dresden, Germany date:3 Sep - 6 Sep 2018 status: published