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° A physical vapor deposition (PVD) formed WNi thinfilm over M1 (metal level 1) after its revealing in the via-last through-Si-via (TSV) process has been investigated for its ability in protecting the M1 metal during electroless (EL) plating of barrier/seed layers or Cu electroplating (EP). The WNi protection layer was also checked for (i) its platability of Cu by both EL and EP methods (the void-free formation of Cu-TSVs by direct Cu-EPing over WNi layer), (ii) its barrier performance against Cu diffusion (from the absence of Cu singal in both WNi and Si region of Auger electron depth profile), (iii) its adhession nature (intactness of film after the tape-peel test), and (iv) its endurance during Cu-CMP (chemical mechanical polishing). All the results confimed that PVD formed WNi not only protects the M1 metal layer from the EL or EP bath, but also forms a very good barrier-cum-seed layer in the Cu-TSVs.

Si TEG chips containing Au-Sn micro-bumps (μ- bump) with various sizes (varying from 3 to 20 μm) and pitch values (between 6 μm and 30 μm) were fabricated, and the flip-chip bonded chips were characterized for micro-structure and electrical resistance of Au-Sn μ-joints. An overall μ-joint height of -1.8 μm was obtained after thermal compression bonding at 180 ’C for the 10 μm pitch μ-bumps with solder (Sn) height of 1.0-1.5 μm. The elemental analysis results showed that Au has diffused into the solder layer, and not vice-versa. The formation of seemless microstructure and the obtained resistance data reveal that the Au-Sn μ-joints with minimal height have tremendous potential for its application in the tight-pitch three- dimensional chip integration and packaging.

The electroless (EL) Ni layer conformally formed inside the high aspect ratio (AR, >10) through-Si-via (TSV) has been investigated for its role as seed layer in bottom-up Cu electroplating. From the electro-chemical adsorption monitoring data it was found that the adsorption (or accumulation) of additives onto the EL-Ni surface for bottom-up Cu electroplating was prodoundly suppressed when compared with the Ni seed layer depositied by PVD. A simple and viable two step process was proposed and demonstrated to overcome the problem, and we were able to successfully fill the TSVs (width ~10 mm, AR > 10) with by Cu-electroplating using the EL- Ni as seed as well as barrier layer. Thus, this low-cost, readily-scalable (both in wafer-size and volume) and CMOS compatible EL method for the formation of Ni barrier-cum-seed layer in the high AR TSVs for integration and packaging applications has tremendous potential to replace the high-cost PVD or CVD barrier and seed layers..

Through-silicon vias (TSVs) is one of the key technologies for 3D integration. To solve the issues induced by the high-temperature process for TSV liner formation in the multichip-to-wafer (MCtW) process, we applied the low-temperature SiO 2 deposition method called OER (Ozone-Ethylene Radical generation)-TEOS-CVD®. In this study, we fabricated the MIS capacitors with the TSV liner deposited by OER-TEOS-CVD® at 150°C and room temperature (RT), and compared both the coverage and electrical characteristics with that formed by conventional plasma-enhanced chemical vapor deposition (PE-CVD) at 200°C. Furthermore, we analyzed these SiO 2 liners by FTIR and synchrotron XPS. These results showed that the OER-TEOS-CVD® has high potentials to realize highly-reliable TSVs and to apply to various processes in 3D integration.

An advanced Directed-Self-Assembly (DSA) assisted vertical nano-scale interconnection formation has been attempted inside deep Si trench structures for ultra-high-density 3D storage memory application. Based on Flory-Huggins theory, nano-cylindrical structures with and without metal nano-particles were obtained for a nano-composite containing di-block co-polymer system and novel metal nanoparticles. The low-temperature transmission electron micros-copy was primarily used to analyze the DSA-formed vertical nano-structures inside Si deep trenches.

A feasibility study for the continuous formation of multi-layer graphene (MLG) on both through-Si-via (TSV) top surface and all through the TSV sidewall and the bottom surface of high-aspect-ratio TSV by thermal chemical vapor deposition (CVD) technique has been carried out. Both microstructural and μ-Raman studies on cross-sectional graphene-TSV samples confirmed that the continuous formation of MLG all along the TSV side wall for the CVD growth temperatures of 650°C and above, and it may be used as thermal TSVs for heat removal in the stacked tiers of 3D-LSI/IC.

A thickness value of less than 50 μm for die/wafers is a must meet criteria in 3-D large-scale silicon device integration, in order to reduce interconnect lengths and resistive-capacitive delays. The mechanical properties of such ultra-thin die/wafers, namely, Young's modulus, hardness, etc., with respect to 1) different die thinning processes (chemical mechanical polishing, plasma etching, dry polishing, kai-dry polishing, poly grinding, ultra-poly grinding, #2000, etc.); 2) various wafer thicknesses (10, 20, 30, 40, 50, 100, and 200 μm); and 3) different wafer types (P/P+, P/P-, and wafers with internal-gettering layers) were investigated by using a nano-indenter. The mechanical characteristic data obtained for the thin die/wafers were well supported by their corresponding residual stress values (obtained by laser micro-Raman spectroscopy) and the crystal mis-orientation results (obtained via electron back-scatter diffraction). The chemically-mechanically polished ultrathin dies/wafers were found to be extremely good from the perspective of both mechanical strength and residual stress when compared to their counter parts fabricated by all other die thinning methods considered in this study.

Silicon-lattice distortion in the 50- μm-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ~ 1000 MPa of tensile stress and ~ -200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

With in the process temperature limit of less than 400 °C for via last technology, a simple method to improve the barrier ability of Ti layer in through Si via (TSV) has been studied. After annealing the TSV structures in vacuum at temperatures up to 400 °C, we did observe a tremendous improvement in leak current characteristics for SiO2 dielectric. It was found that the self-formed TiSi x at the interface between Cu and SiO 2 during the sputter deposition of Ti barrier layer was converted into an amorphous TiOx and SiOx upon vacuum annealing. This simple vacuum annealing of Cu-TSVs is a promising approach for using Ti as barrier layer in via-last 3D-integration.

Suppressing leak current and blocking Cu diffusion into active Si from Cu through-silicon vias (TSVs) are important requirements for enhancing three-dimensional (3D) LSI performance and reliability. We have proposed and confirmed a cost effective means of enhancing the barrier property of sputtered Ti in high-aspect-ratio Cu-TSVs by simple vacuum annealing at 400 °C for 20 min. The self-formed amorphous TiSi2 at the interface between dielectric SiO2 (along the TSV side-wall) and barrier Ti layer is found to play a positive role in improving the leak current characteristics. As-formed TiSix was partially converted into TiO2 and SiO2 during the vacuum annealing above 200 °C, and nearly vanished after annealing at 400 °C. The immense importance of 400 °C vacuum-annealing is not only in terms of the improvement in the barrier characteristics of the Ti layer, but also it is being a prerequisite for preventing Cu popup in 3D-LSI. Both the X-ray photoelectron spectroscopy (XPS) and current–voltage (I–V) data clearly reveal that this simple vacuum annealing of Cu-TSVs at 400 °C has tremendous potential for implementation in cost-effective via-last 3D integration.

A novel approach to suppress the conventional Cu-TSV induced thermo-mechanical stress in 3D-LSI chip is proposed, fabricated and tested. In this approach, a thermal-chemical-vapor-deposition grown organic poly-imide based polymer is conformally deposited along the side wall of the TSV. As-grown polymer was tested for its physical properties and mechanical properties, and was also evaluated for their role in minimizing the thermo-mechanical stress in vicinal and via-space Si. It was found that replacing the conventional SiO 2 dielectric liner (sandwiched between the via-metal and Si) with organic polymer greatly helps in suppressing the thermo-mechanical stress, and thus the keep-out zone.

Minimization of the parasitic capacitance arising from Cu–through-Si-vias (TSVs) has been rigorously considered in order to enhance the performances of three-dimensional (3D) LSIs. We have systematically investigated the role of chemical vapor deposited (CVD) polyimide (PI) liner in Cu-TSVs in reducing the TSV capacitance. It is confirmed that CVD grown PI greatly helps to reduce the TSV capacitance as compared to the conventional PECVD-SiO2 liner. In addition to that the presence of very small hysteresis and a negligible flat-band voltage shift along the voltage axis confirms the suitability of PI liner as dielectric in the Cu-TSVs, if it were operated below the bias voltages of ±20 V. In over all, the large reduction in capacitance along with the conformal deposition of PI in the TSVs having less than 3 µm-width with aspect ratios greater than 10 reveals that CVD grown PI has the potential application in the future 3D-LSIs with highly scaled TSV.

Reliability issues such as thermo-mechanical stress, extrusion of via metal, and die-cracking caused by high density Cu-TSVs in 3D-LSI Si die/wafer after wafer thinning and bonding have been systematically investigated respectively using micro-Raman spectroscopy, laser microscopy, and optical microscopy techniques. It is inferred that (i) for the TSV pitch value of less than twice the TSV-width, the remnant stress present in the Si at the TSV space region is turned to be only compressive, i.e. in the lateral direction, the compressive stress produced by the adjacent TSVs overlapped to each other; for the TSV pitch values of greater than two times the TSV-width, the compressive stress in the Si at the vicinity of TSV is followed by the tensile stress and beyond that it becomes stress free at the TSV space region; (ii) Irrespective of the TSV shape and size, the lateral extrusion of Cu occurs at the TSV space region. The lateral extrusion becomes prominent for the larger TSV size values and the higher bonding temperatures. The lateral extrusion is larger for the 20 μm-width TSV annealed at the higher temperature (∼4 μm @ 400 °C) than for the TSV annealed at lower temperature (a maximum of only 1.5 μm @ 200 °C); (iii) Cracking of LSI die/wafer occurs at the periphery of the TSV array for very fine pitch values, and for larger pitch values cracking occurs in between TSVs.