89 results on '"Murgai R"'
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2. 'Investing in farmers--the impacts of farmer field schools in relation to integrated pest management'--a comment
3. Synovial fluid cell counts and its role in the diagnosis of paediatric septic arthritis
4. Fiscal sustainability of agricultural extension: The case of farmer field school approach
5. Accurate substrate noise analysis based on library module characterization
6. Analyzing Timing Uncertainty in Mesh-based Clock Architectures
7. On the problem of gate assignment under different rise and fall delays
8. Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.
9. An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis.
10. Fast power network analysis with multiple clock domains.
11. Clock Distribution Architectures.
12. A sliding window scheme for accurate clock mesh analysis.
13. Improved layout-driven area-constrained timing optimization by net buffering.
14. Net buffering in the presence of multiple timing views.
15. XTalkDelay: a crosstalk-aware timing analysis tool for chip-level designs.
16. PDL: a new physical synthesis methodology.
17. Design closure with cell-based synthesis
18. Productivity Growth and Sustainability in Post-Green Revolution Agriculture: The Case of the Indian and Pakistan Punjabs
19. Layout-driven timing optimization by generalized De Morgan transform.
20. Efficient global fanout optimization algorithms.
21. Complexity of minimum-delay gate.
22. An exact gate assignment algorithm for tree circuits under rise and fall delays.
23. Layout-driven area-constrained timing optimization by net buffering.
24. Efficient scheduling techniques for ROBDD construction
25. On reducing transitions through data modifications.
26. An improved synthesis algorithm for multiplexor-based PGAs.
27. Improved logic synthesis algorithms for table look up architectures.
28. Performance directed synthesis for table look up programmable gate arrays.
29. On clustering for minimum delay/ara.
30. Logic synthesis for a single large look-up table.
31. Delay estimation and optimization of logic circuits: a survey.
32. Some results on the complexity of Boolean functions for table look up architectures.
33. SLIP: a software environment for system level interactive partitioning.
34. Some recent advances in software and hardware logic simulation.
35. Sequential synthesis for table look up PGAs.
36. Sense and sustainability revisited: the limits of total factor productivity measures of sustainable agricultural systems
37. The Green Revolution and the productivity paradox: evidence from the Indian Punjab
38. Performance directed synthesis for table look up programmable gate arrays
39. Efficient global fanout optimization algorithms
40. An improved synthesis algorithm for multiplexor-based PGAs
41. An exact gate assignment algorithm for tree circuits under rise and fall delays
42. Layout-driven area-constrained timing optimization by net buffering
43. Improved logic synthesis algorithms for table look up architectures
44. Logic synthesis for a single large look-up table
45. Delay-constrained area recovery via layout-driven buffer optimization
46. Improved layout-driven area-constrained timing optimization by net buffering
47. Using complementation and resequencing to minimize transitions
48. Some recent advances in software and hardware logic simulation
49. On clustering for minimum delay/ara
50. Complexity of minimum-delay gate
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