Search

Introducing parallelism and exploring its use is still a fundamental challenge for the computer algebra community. In high-performance numerical simulation, on the other hand, transparent environments for distributed computing which follow the principle of separating coordination and computation have been a success story for many years. In this paper, we explore the potential of using this principle in the context of computer algebra. More precisely, we combine two well-established systems: The mathematics we are interested in is implemented in the computer algebra system Singular, whose focus is on polynomial computations, while the coordination is left to the workflow management system GPI-Space, which relies on Petri nets as its mathematical modeling language and has been successfully used for coordinating the parallel execution (autoparallelization) of academic codes as well as for commercial software in application areas such as seismic data processing. The result of our efforts is a major step towards a framework for massively parallel computations in the application areas of Singular, specifically in commutative algebra and algebraic geometry. As a first test case for this framework, we have modeled and implemented a hybrid smoothness test for algebraic varieties which combines ideas from Hironaka's celebrated desingularization proof with the classical Jacobian criterion. Applying our implementation to two examples originating from current research in algebraic geometry, one of which cannot be handled by other means, we illustrate the behavior of the smoothness test within our framework and investigate how the computations scale up to 256 cores., Author(s): Janko Böhm [sup.1], Wolfram Decker [sup.1], Anne Frühbis-Krüger [sup.2] [sup.4], Franz-Josef Pfreundt [sup.3], Mirko Rahn [sup.3], Lukas Ristau [sup.1] [sup.3] Author Affiliations: (1) grid.7645.0, 0000 0001 2155 0333, Department [...]

Natural spoken language carries both linguistic (e.g., phonetic) and paralinguistic (e.g., emotional) information through visual and auditory modalities. Successful communication requires the integration of audiovisual speech with embedded multidimensional cues. [...], Purpose: Spoken language is inherently multimodal and multidimensional in natural settings, but very little is known about how second language (L2) learners undertake multilayered speech signals with both phonetic and affective cues. This study investigated how late L2 learners undertake parallel processing of linguistic and affective information in the speech signal at behavioral and neurophysiological levels. Method: Behavioral and event-related potential measures were taken in a selective cross-modal priming paradigm to examine how late L2 learners (N = 24, [M.sub.age] = 25.54 years) assessed the congruency of phonetic (target vowel: /a/ or /i/) and emotional (target affect: happy or angry) information between the visual primes of facial pictures and the auditory targets of spoken syllables. Results: Behavioral accuracy data showed a significant congruency effect in affective (but not phonetic) priming. Unlike a previous report on monolingual first language (L1) users, the L2 users showed no facilitation in reaction time for congruency detection in either selective priming task. The neurophysiological results revealed a robust N400 response that was stronger in the phonetic condition but without clear lateralization and that the N400 effect was weaker in late L2 listeners than in monolingual L1 listeners. Following the N400, late L2 learners showed a weaker late positive response than the monolingual L1 users, particularly in the left central to posterior electrode regions. Conclusions: The results demonstrate distinct patterns of behavioral and neural processing of phonetic and affective information in L2 speech with reduced neural representations in both the N400 and the later processing stage, and they provide an impetus for further research on similarities and differences in L1 and L2 multisensory speech perception in bilingualism.

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.cell.2010.11.021 Byline: Sake van Wageningen (1), Patrick Kemmeren (1), Philip Lijnzaad (1)(4), Thanasis Margaritis (1), Joris J. Benschop (1), InA*s J. de Castro (1), Dik van Leenen (1), Marian J.A. Groot Koerkamp (1), Cheuk W. Ko (1), Antony J. Miles (1), Nathalie Brabers (1), Mariel O. Brok (1), Tineke L. Lenstra (1), Dorothea Fiedler (2), Like Fokkens (3), Rodrigo Aldecoa (1), Eva Apweiler (1), Virginia Taliadouros (1), Katrin Sameith (1), Loes A.L. van de Pasch (1), Sander R. van Hooff (1), Linda V. Bakker (1)(4), Nevan J. Krogan (2), Berend Snel (3), Frank C.P. Holstege (1) Keywords: CELLBIO; SIGNALING Abstract: To understand relationships between phosphorylation-based signaling pathways, we analyzed 150 deletion mutants of protein kinases and phosphatases in S. cerevisiae using DNA microarrays. Downstream changes in gene expression were treated as a phenotypic readout. Double mutants with synthetic genetic interactions were included to investigate genetic buffering relationships such as redundancy. Three types of genetic buffering relationships are identified: mixed epistasis, complete redundancy, and quantitative redundancy. In mixed epistasis, the most common buffering relationship, different gene sets respond in different epistatic ways. Mixed epistasis arises from pairs of regulators that have only partial overlap in function and that are coupled by additional regulatory links such as repression of one by the other. Such regulatory modules confer the ability to control different combinations of processes depending on condition or context. These properties likely contribute to the evolutionary maintenance of paralogs and indicate a way in which signaling pathways connect for multiprocess control. Author Affiliation: (1) Molecular Cancer Research, University Medical Centre Utrecht, Universiteitsweg 100, Utrecht, The Netherlands (2) Department of Cellular and Molecular Pharmacology, University of California, San Francisco, San Francisco, CA 94158, USA (3) Theoretical Biology and Bioinformatics, Department of Biology, Science Faculty, Utrecht University, Padualaan 8, 3584 CH Utrecht, The Netherlands (4) Netherlands Bioinformatics Centre, Geert Grooteplein 28, 6525 GA, Nijmegen, The Netherlands Article History: Received 29 January 2010; Revised 20 September 2010; Accepted 9 November 2010 Article Note: (miscellaneous) Published: December 9, 2010

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2010.07.012 Byline: M. Tomasi (a), F. Barranco (a), M. Vanegas (a)(b), J. Diaz (a), E. Ros (a) Keywords: Optical flow; Embedded and real-time systems; FPGA Abstract: Accurate motion analysis of real life sequences is a very active research field due to its multiple potential applications. Currently, new technologies offer us very fast and accurate sensors that provide a huge quantity of data per second. Processing these data streams is very expensive (in terms of computing power) for general purpose processors and therefore, is beyond processing capabilities of most current embedded devices. In this work, we present a specific hardware architecture that implements a robust optical flow algorithm able to process input video sequences at a high frame rate and high resolution, up to 160fps for VGA images. We describe a superpipelined datapath of more than 85 stages (some of them configured with superscalar units able to process several data in parallel). Therefore, we have designed an intensive parallel processing engine. System speed (frames per second) produces fine optical flow estimations (by constraining the actual motion ranges between consecutive frames) and the phase-based method confers the system robustness to image noise or illumination changes. In this work, we analyze the architecture of different frame rates and input image noise levels. We compare the results with other approaches in the state of the art and validate our implementation using several hardware platforms. Author Affiliation: (a) Department ATC ETSI Informatica y Telecomunicaciones, Universidad de Granada, C/Periodista Daniel Saucedo, sn, 18071 Granada, Spain (b) Grupo de Microelectronica, Universidad Pontificia, Bolivariana Circular 1, No. 70-01 Medellin, Colombia Article History: Received 23 October 2009; Revised 9 April 2010; Accepted 26 July 2010

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2010.09.003 Byline: Jianbo Dong (a)(b), Lei Zhang (a), Yinhe Han (a)(b), Guihai Yan (a)(b), Xiaowei Li (a)(b) Keywords: Process variation; Thread-level redundancy; Chip Multiprocessor; Scheduling Abstract: Thread-level redundancy is an efficient approach for transient fault detection and recovery in Chip Multiprocessors (CMPs), in which two adjacent cores are statically coupled to form a functional Dual Modular Redundancy (DMR). Manufacturing process variations cause core-to-core (C2C) performance asymmetry across the chip, which can be further divided into the asymmetry among core-pairs and the asymmetry within a core-pair. We call them inter- and intra-pair asymmetries, respectively, both of which should be taken into considerations in application scheduling for CMPs with static core coupling. In this paper, we first formulate the above scheduling problem as a 0-1 programming problem to maximize the system Weighted Throughput. An efficient IVF&AppSen algorithm is then proposed, which we prove to be optimal when the number of applications equals to that of core-pairs. We also adapt the Simulated Annealing technique to tackle this problem when applications are less than core-pairs on chip. Simulations on a 64-core CMP shows that the proposed algorithms achieve 2.5-9.3% improvement in Weighted Throughput when compared to prior VarF&AppIPC algorithm. Author Affiliation: (a) Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, PR China (b) Graduate University of Chinese Academy of Sciences, Beijing, PR China Article History: Received 13 January 2010; Revised 17 May 2010; Accepted 7 September 2010 Article Note: (footnote) [star] The work was supported in part by National Basic Research Program of China (973) under Grant No. 2011CB302503, in part by National Natural Science Foundation of China (NSFC) under Grant Nos. 60806014, 60831160526, 60633060, 60921002, 61076037, 60906018, and in part by Hi-Tech Research and Development Program of China (863) under Grant No. 2009AA01Z126.

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2010.06.002 Byline: Jianguo Yao (a), Xue Liu (b), Zonghua Gu (c), Xiaorui Wang (d), Jian Li (e) Keywords: Multiprocessor systems; Real-time; Adaptive; Control Abstract: Many embedded systems have stringent real-time constraints. An effective technique for meeting real-time constraints is to keep the processor utilization on each node at or below the schedulable utilization bound, even though each task's actual execution time may have large uncertainties and deviate a lot from its estimated value. Recently, researchers have proposed solutions based on Model Predictive Control (MPC) for the utilization control problem. Although these approaches can handle a limited range of execution time estimation errors, the system may suffer performance deterioration or even become unstable with large estimation errors. In this paper, we present two online adaptive optimal control techniques, one is based on Recursive Least Squares (RLS) based model identification plus Linear Quadratic (LQ) optimal controller; the other one is based on Adaptive Critic Design (ACD). Simulation experiments demonstrate both the LQ optimal controller and ACD-based controller have better performance than the MPC-based controller and the ACD-based controller has the smallest aggregate tracking errors. Author Affiliation: (a) School of Astronautics, Northwestern Polytechnical University, PR China (b) Department of Computer Science and Engineering, University of Nebraska - Lincoln, Nebraska, United States (c) College of Computer Science, Zhejiang University, PR China (d) Department of Electrical Engineering and Computer Science, The University of Tennessee, Knoxville, United States (e) School of Software, Shanghai Jiao Tong University, PR China Article History: Received 5 August 2009; Revised 8 April 2010; Accepted 1 June 2010 Article Note: (footnote) [star] Partial results of this paper has been presented in the CODES+ISSS 2008 .

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2010.05.006 Byline: Antonio Flores, Manuel E. Acacio, Juan L. Aragon Keywords: Tiled chip multiprocessor; Energy-efficient architecture; Cache-coherence protocol; Heterogeneous on-chip interconnection network Abstract: High performance processor designs have evolved toward architectures that integrate multiple processing cores on the same chip. As the number of cores inside a Chip MultiProcessor (CMP) increases, the interconnection network will have significant impact on both overall performance and energy consumption as previous studies have shown. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we show how messages can be efficiently managed in tiled CMP, from the point of view of both performance and energy, by combining both address compression with a heterogeneous interconnect. In particular, our proposal is based on applying an address compression scheme that dynamically compresses the addresses within coherence messages allowing for a significant area slack. The arising area is exploited for wire latency improvement by using a heterogeneous interconnection network comprised of a small set of very-low-latency wires for critical short-messages in addition to baseline wires. Detailed simulations of a 16-core CMP show that our proposal obtains average improvements of 10% in execution time and 38% in the energy-delay.sup.2 product of the interconnect. Additionally, the sensitivity analysis shows that our proposal performs well when either OoO cores or caches with higher latencies are considered. Author Affiliation: Departamento de Ingenieria y Tecnologia de Computadores, University of Murcia, 30100 Murcia, Spain Article History: Received 2 December 2008; Revised 27 April 2010; Accepted 7 May 2010

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.compeleceng.2009.06.003 Byline: A[degrees]pek AbasikeleA, M. Fatih Akay Keywords: Directory protocols; Distributed shared memory; Multiprocessors; Performance evaluation; Optical interconnects; Simulation Abstract: Recent advances in the development of optical technologies suggest the possible emergence of broadcast-based optical interconnects within cache-coherent distributed shared memory (DSM) multiprocessor architectures. It is well known that the cache-coherence protocol is a critical issue in designing such architectures because it directly affects memory latencies. In this paper, we evaluate via simulation the performance of three directory-based cache-coherence protocols; strict request-response, intervention forwarding and reply forwarding on the Simultaneous Optical Multiprocessor Exchange Bus (SOME-Bus), which is a low-latency and high-bandwidth broadcast-based fiber-optic interconnection network supporting DSM. The simulated system contains 64 nodes, each of which has a processor, a cache controller, a directory controller and an output channel. Simulations have been conducted for each protocol to measure average processor utilization, average network latency and average number of packets transferred over the network for varying values of the important DSM parameters such as the ratio of the mean channel service time to mean thread run time (T/R), probability of a cache block being in modified state {P(M)}, the fraction of write misses {P(W)} and home node contention rate. The results reveal that for all cases, except for low values of P(M), intervention forwarding gives the worst performance (lowest processor utilization and highest latency). The performance of strict request-response and reply forwarding is comparable for several values of the DSM parameters and contention rate. For a contention rate of 0%, the increase of P(M) makes reply forwarding perform better than strict request-response. The performance of all protocols decreases with the increase of P(W) and contention rate. However, the performance of strict request-response is the least affected among other protocols due to the negative impact of the increase of P(W) and contention rate. Therefore, for the full contention case (i.e. contention rate of 100%); for low values of P(M), or for mid values of P(M) and high values of P(W), strict request-response performs better than reply forwarding. These results are significant in the sense that they provide an insight to multiprocessor architecture designers for comparing the performance of different directory-based cache-coherence protocols on a broadcast-based interconnection network for different values of the DSM parameters and varying rates of contention. Author Affiliation: Computer Engineering Department, Aukurova University, 01330 Adana, Turkey Article History: Received 24 January 2009; Revised 7 June 2009; Accepted 25 June 2009

Graphics processors (GPUs) have recently emerged as powerful coprocessors for general purpose computation. Compared with commodity CPUs, GPUs have an order of magnitude higher computation power as well as memory bandwidth. Moreover, new-generation GPUs allow writes to random memory locations, provide efficient interprocessor communication through on-chip local memory, and support a general purpose parallel programming model. Nevertheless, many of the GPU features are specialized for graphics processing, including the massively multithreaded architecture, the Single-Instruction-Multiple-Data processing style, and the execution model of a single application at a time. Additionally, GPUs rely on a bus of limited bandwidth to transfer data to and from the CPU, do not allow dynamic memory allocation from GPU kernels, and have little hardware support for write conflicts. Therefore, a careful design and implementation is required to utilize the GPU for coprocessing database queries. In this article, we present our design, implementation, and evaluation of an in-memory relational query coprocessing system, GDB, on the GPU. Taking advantage of the GPU hardware features, we design a set of highly optimized data-parallel primitives such as split and sort, and use these primitives to implement common relational query processing algorithms. Our algorithms utilize the high parallelism as well as the high memory bandwidth of the GPU, and use parallel computation and memory optimizations to effectively reduce memory stalls. Furthermore, we propose coprocessing techniques that take into account both the computation resources and the GPU-CPU data transfer cost so that each operator in a query can utilize suitable processors--the CPU, the GPU, or both--for an optimized overall performance. We have evaluated our GDB system on a machine with an Intel quad-core CPU and an NVIDIA GeForce 8800 GTX GPU. Our workloads include microbenchmark queries on memory-resident data as well as TPC-H queries that involve complex data types and multiple query operators on data sets larger than the GPU memory. Our results show that our GPU-based algorithms are 2-27x faster than their optimized CPU-based counterparts on in-memory data. Moreover, the performance of our coprocessing scheme is similar to, or better than, both the GPU-only and the CPU-only schemes. Categories and Subject Descriptors: H.2.4 [Database Management]: Systems--Query processing, relational databases General Terms: Algorithms, Measurement, Performance Additional Key Words and Phrases: Relational database, join, sort, primitive, parallel processing, graphics processors DOI = 10.1145/1620585.1620588 http://doi.acm.org/10.1145/1620585.1620588

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2009.08.001 Byline: Ismail Assayad Keywords: Joint software and hardware modelling; Joint software and hardware synthesis; Software and hardware performance; Transactional-level modelling Abstract: We present P-Ware, a framework for joint software and hardware modelling and synthesis of multiprocessor embedded systems. The framework consists of (1) component-based annotated transaction-level models for joint modelling of parallel software and multiprocessor hardware, and (2) exploration-driven methodology for joint software and hardware synthesis. The methodology has the advantage of combining real-time requirements of software with efficient optimization of hardware performance. We describe and apply the methodology to synthesize a scheduler of a H264 video encoder on the Cake multiprocessor. Moreover, experiments show that the framework is scalable while achieving rapid and efficient designs. Author Affiliation: Verimag, Centre Equation, 2 av. de Vignate, 38610 Gieres, France Article History: Received 5 February 2009; Revised 9 August 2009; Accepted 13 August 2009

To authenticate to the full-text of this article, please visit this link: http://dx.doi.org/10.1111/j.1460-2466.2009.01418.x Byline: Nithya Muthusamy (1), Timothy R. Levine (1), Rene Weber (2) Abstract: Fear appeals are often used in public health campaigns in Africa to prevent further spread of HIV/AIDS. Based on the extended parallel processing model framework (K. Witte, 1991), this research assessed the impact of such messages in a high-fear situation. A 2 (high threat, low threat) x 2 (high efficacy, no efficacy) experiment with a no-message offset control and efficacy-only conditions tested several predictions. Participants demonstrated high preexisting fear about HIV/AIDS. As a likely consequence, statistical equivalence tests indicated that messages' threat levels had little impact on perceptions of fear or on outcome measures such as attitudes, intentions, or behaviors. It is concluded that the use of fear appeals to persuade audience with high levels of preexisting fear is ill-advised and ineffective. Author Affiliation: (1) Department of Communication, Michigan State University, East Lansing, MI 48824 (2) Department of Communication, University of California-Santa Barbara, Santa Barbara, CA 93106 Article note: Timothy R. Levine; e-mail: levinet@msu.edu

This paper proposes a simple iterated greedy (IG) heuristic to minimize makespan in a multistage hybrid flowshop with multiprocessor tasks. To validate and verify the proposed heuristic, computational experiments have been conducted on two well-known benchmark problem sets. The experiment results clearly reveal that the proposed IG heuristic is highly effective as compared to three state-of-the-art meta-heuristics on the same benchmark instances. doi: l0.1057/palgrave.jors.2602625 Keywords: hybrid flowshop; multiprocessor task scheduling; iterated greedy heuristic

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2008.10.005 Byline: Guo-Huang Hsu (a), Chieh-Feng Chiang (a), Lun-Min Shih (a), Lih-Hsing Hsu (b), Jimmy J.M. Tan (a) Keywords: Comparison model; Diagnosability; Conditional diagnosability; Hypercube Abstract: Processor fault diagnosis plays an important role in multiprocessor systems for reliable computing, and the diagnosability of many well-known networks has been explored. Lai et al. proposed a novel measure of diagnosability, called conditional diagnosability, by adding an additional condition that any faulty set cannot contain all the neighbors of any vertex in a system. We make a contribution to the evaluation of diagnosability for hypercube networks under the comparison model and prove that the conditional diagnosability of n-dimensional Hypercube Q.sub.n is 3(n -2)+1 for n [greater than or equal to]5. The conditional diagnosability of Q.sub.n is about three times larger than the classical diagnosability of Q.sub.n . Author Affiliation: (a) Department of Computer Science, National Chiao Tung University, Hsinchu 300, Taiwan, ROC (b) Department of Computer Science and Information Engineering, Providence University, Taichung 43301, Taiwan, ROC Article History: Received 15 May 2007; Revised 17 October 2008; Accepted 29 October 2008 Article Note: (footnote) [star] This research was partially supported by the National Science Council of the Republic of China under contract NSC 95-2221-E-009-134-MY3., [star][star] This research was partially supported by the Aiming for the Top University and Elite Research Center Development Plan.

A multistage interconnection network (MIN) consisting of 2 x 2 nodes constructs a nonblocking switch if the network is rearrangeable. When a [2.sup.n] x [2.sup.n] bit-permuting network is rearrangeable with the minimum depth of 2n - 1, the initial (resp. final) n stages of the network form a banyan-type network and hence the network is equivalent to the tandem connection between two banyan-type networks. Let [gamma] denote the guide permutation of a [2.sup.n] x [2.sup.n] banyan-type network and [tau] the trace permutation of another. These are permutations on numbers from 1 to n. This paper proves that, when the permutation [gamma][[tau].sup.-1] is the transposition between the number n and some number k < n, the tandem connection between the two networks is rearrangeable. This sufficient condition for rearrangeability covers a wide class of tandem connections. For example, the first network in tandem can be the omega network appended with the banyan exchange of any rank while the second is the reversed omega network. Index Terms--multistage interconnection network, banyan-type network, bit-permuting network, rearrangeability, tandem connection, trace, guide, permutation, transposition.

Multiprocessor scheduling in a shared multiprogramming environment can be structured as two-level scheduling, where a kernel-level job scheduler allots processors to jobs and a user-level thread scheduler schedules the work of a job on its allotted processors. We present a randomized work-stealing thread scheduler for fork-join multithreaded jobs that provides continual parallelism feedback to the job scheduler in the form of requests for processors. Our A-[S.sub.TEAL] algorithm is appropriate for large parallel servers where many jobs share a common multiprocessor resource and in which the number of processors available to a particular job may vary during the job's execution. Assuming that the job scheduler never allots a job more processors than requested by the job's thread scheduler, A-[S.sub.TEAL] guarantees that the job completes in near-optimal time while utilizing at least a constant fraction of the allotted processors. We model the job scheduler as the thread scheduler's adversary, challenging the thread scheduler to be robust to the operating environment as well as to the job scheduler's administrative policies. For example, the job scheduler might make a large number of processors available exactly when the job has little use for them. To analyze the performance of our adaptive thread scheduler under this stringent adversarial assumption, we introduce a new technique called trim analysis, which allows us to prove that our thread scheduler performs poorly on no more than a small number of time steps, exhibiting near-optimal behavior on the vast majority. More precisely, suppose that a job has work [T.sub.1] and span [T.sub.[infinity]]. On a machine with P processors, A-[S.sub.TEAL] completes the job in an expected duration of O([T.sub.1]/[??] + [T.sub.[infinity]] + L lg P) time steps, where L is the length of a scheduling quantum, and [??] denotes the O([T.sub.[infinity]] + L lg P)-trimmed availability. This quantity is the average of the processor availability over all time steps except the O([T.sub.[infinity]] + L lg P) time steps that have the highest processor availability. When the job's parallelism dominates the trimmed availability, that is, [??] << [T.sub.1]/[T.sub.[infinity]], the job achieves nearly perfect linear speedup. Conversely, when the trimmed mean dominates the parallelism, the asymptotic running time of the job is nearly the length of its span, which is optimal. We measured the performance of A-[S.sub.TEAL] on a simulated multiprocessor system using synthetic workloads. For jobs with sufficient parallelism, our experiments confirm that A-[S.sub.TEAL] provides almost perfect linear speedup across a variety of processor availability profiles. We compared A-[S.sub.TEAL] with the ABP algorithm, an adaptive work-stealing thread scheduler developed by Arora et al. [1998] which does not employ parallelism feedback. On moderately to heavily loaded machines with large numbers of processors, A-[S.sub.TEAL] typically completed jobs more than twice as quickly as ABP, despite being allotted the same number or fewer processors on every step, while wasting only 10% of the processor cycles wasted by ABP. Categories and Subject Descriptors: D.4.1 [Operating Systems]: Process Management; F.2 [Analysis of Algorithms and Problem Complexity] General Terms: Algorithms, Performance, Theory, Experimentation Additional Key Words and Phrases: Adaptive scheduling, adversary, span, instantaneous parallelism, job scheduling, multiprocessing, multiprogramming, parallelism feedback, parallel computation, processor allocation, randomized algorithm, thread scheduling, two-level scheduling, space sharing, trim analysis, work, work-stealing ACM Reference Format: Agrawal, K., He, Y., Hsu, W. J., and Leiserson, C. E. 2008. Adaptive work-stealing with parallelism feedback. ACM Trans. Comput. Syst. 26, 3, Article 7 (September 2008), 32 pages. DOI=10.1145/ 1394441.1394443 http://doi.acm. org/10.1145/1394441.1394443

Application of heuristics for derivation of genetic algorithms to simulate multi-attribute dispatching from muliti-layer ceramic capacitors is described.

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.ejor.2005.07.022 Byline: Aukasz Kuszner, MichaA MaAafiejski Keywords: Scheduling; Complexity theory; Multiprocessor tasks; Dedicated processors Abstract: In this paper we consider a problem of preemptive scheduling of multiprocessor tasks on dedicated processors in order to minimize the sum of completion times. Using a standard notation, our problem can be denoted as P a[pounds sterling]fix.sub.j , pmtna[pounds sterling]aC.sub.j . We give a polynomial-time algorithm to solve P a[pounds sterling]fix.sub.j , G ={P.sub.4,dart}-free, pmtna[pounds sterling]aC.sub.j problem. This result generalizes the following problems: P2a[pounds sterling]fix.sub.j , pmtna[pounds sterling]aC.sub.j , P a[pounds sterling]a[pounds sterling]fix.sub.j a[pounds sterling][member of]{1, m}, pmtna[pounds sterling]aC.sub.j and P4a[pounds sterling]fix.sub.j =2, pmtna[pounds sterling]aC.sub.j . Author Affiliation: Department of Algorithms and System Modeling, Gdansk University of Technology, Narutowicza 11/12, 80-952 Gdansk, Poland Article History: Received 10 May 2004; Accepted 6 July 2005

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2006.07.003 Byline: Dongmahn Seo, Joahyoung Lee, Yoon Kim, Chang Yeol Choi, Manbae Kim, Inbum Jung Keywords: VOD; Cluster system; Streaming media; QoS; Resource aware; Parallel processing Abstract: For Video-On-Demand (VOD) systems, it is important to provide Quality of Service (QoS) to more clients under limited resources. In this paper, the performance scalability in cluster-based VOD servers is studied with several grouping configurations of cluster nodes. To find performance bottlenecks, the monitoring functions are employed and the maximum QoS streams are measured under the various requests including VCR functions. To support more user friendly interface, an embedded set-top model is suggested for the QoS of TV clients. From our detailed experiment results, a new admission control method is proposed that is based on available system resources and the actual amount of resource consumed for QoS streams. The proposed method provides not only more scalable QoS in cluster-based VOD servers but also the enhancement of resource utilization by guaranteeing the maximum number of QoS streams. Author Affiliation: Department of Computer Science and Engineering, Kangwon National University, 192-1 Hyoja 2-Dong, Chuncheon, Kangwon Do 200-701, Republic of Korea Article History: Received 13 August 2005; Revised 21 April 2006; Accepted 3 July 2006 Article Note: (footnote) [star] This research was supported by the MIC (Ministry of Information and Communication), Korea, under the ITRC (Information Technology Research Center) support program supervised by the IITA (Institute of Information Technology Assessment) (IITA-2005-(C1090-0502-0022)). This work was partially supported by the Kangwon Institute of Telecommunications and Basic Research Program of the Korea Science Engineering Foundation (R05-2003-000-12146-0).

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.ejor.2005.02.050 Byline: W.L. Pearn (a), Chien-Wei Wu (b) Keywords: Bootstrap sampling; Lower confidence bound; MPPAC control chart; Process capability indices Abstract: Process capability indices have been widely used in the manufacturing industry providing numerical measures on process potential and process performance. Capability measure for processes with single characteristic has been investigated extensively, but is comparatively neglected for processes with multiple characteristics. In real applications, a process often has multiple characteristics with each having different specifications. Singhal [Singhal, S.C., 1990. A new chart for analyzing multiprocess performance. Quality Engineering 2 (4), 397-390] proposed a multi-process performance analysis chart (MPPAC) for analyzing the performance of multi-process product. Using the same technique, several MPPACs have been developed for monitoring processes with multiple independent characteristics. Unfortunately, those MPPACs ignore sampling errors, and consequently the resulting capability measures and groupings are unreliable. In this paper, we propose a reliable approach to convert the estimated index values to the lower confidence bounds, then plot the corresponding lower confidence bounds on the MPPAC. The lower confidence bound not only gives us a clue minimum actual performance which is tightly related to the fraction of non-conforming units, but is also useful in making decisions for capability testing. A case study of a dual-fiber tip process is presented to demonstrate how the proposed approach can be applied to in-plant applications. Author Affiliation: (a) Department of Industrial Engineering and Management, National Chiao Tung University, 1001 Ta Hsueh Road, Hsin Chu 30050, Taiwan, ROC (b) Department of Industrial Engineering and Systems Management, Feng Chia University, 100 Wenhwa Road, Taichung 40724, Taiwan, ROC Article History: Received 19 January 2004; Accepted 7 February 2005

As the community strives towards autonomous multi-robot systems, there is a need for these systems to autonomously form coalitions to complete assigned missions. Numerous coalition formation algorithms have been proposed in the software agent literature. Algorithms exist that form agent coalitions in both super additive and non-super additive environments. The algorithmic techniques vary from negotiation-based protocols in multi-agent system (MAS) environments to those based on computation in distributed problem solving (DPS) environments. Coalition formation behaviors have also been discussed in relation to game theory. Despite the plethora of MAS coalition formation literature, to the best of our knowledge none of the proposed algorithms have been demonstrated with an actual multi-robot system. There exists a discrepancy between the multi-agent algorithms and their applicability to the multi-robot domain. This paper aims to bridge that discrepancy by unearthing the issues that arise while attempting to tailor these algorithms to the multi-robot domain. A well-known multi-agent coalition formation algorithm has been studied in order to identify the necessary modifications to facilitate its application to the multi-robot domain. This paper reports multi-robot coalition formation results based upon simulation and actual robot experiments. A multi-agent coalition formation algorithm has been demonstrated on an actual robot system. Index Terms--Coalition formation, coalition imbalance, task allocation.

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2006.02.001 Byline: Boris Roussev (a), Jie Wu (b) Keywords: Networking; Distributed computing; Client-server; Concurrent programming; Java Abstract: This paper proposes a new concurrent data structure, called parallel hash table, for synchronizing the access of multiple threads to resources stored in a shared buffer. We prove theoretically the complexity of the operations and the upper limit on the thread conflict probability of the parallel hash table. To empirically evaluate the proposed concurrent data structure, we compare the performance of a TCP multi-threaded parallel hash table-based server to a conventional TCP multi-threaded shared buffer-based server implemented in Java. The experimental results on a network of 36 workstations running Windows NT, demonstrate that the parallel hash table-based server outperforms the conventional multi-threaded server. Author Affiliation: (a) Information Systems Department, University of the Virgin Islands, Box 10,000, Kingshill, VI 00850, US Virgin Islands (b) Computer Science and Engineering Department, Florida Atlantic University, Boca Raton, Fl 33431, USA Article History: Received 27 January 2003; Revised 15 February 2006; Accepted 16 February 2006

Parallel decoding is required for low density parity check (LDPC) codes to achieve high decoding throughput, but it suffers from a large set of registers and complex interconnections due to randomly located 1's in the sparse parity check matrix. This paper proposes a new LDPC decoding architecture to reduce registers and alleviate complex interconnections. To reduce the number of messages to be exchanged among processing units (PUs), two data flows that can be loosely coupled are developed by allowing duplicated operations. In addition, intermediate values are grouped and stored into local storages each of which is accessed by only one PU. In order to save area, local storages are implemented using memories instead of registers. A partially parallel architecture is proposed to promote the memory usage and an efficient algorithm that schedules the processing order of the partially parallel architecture is also proposed to reduce the overall processing time by overlapping operations. To verify the proposed architecture, a 1024 bit rate-l/2 LDPC decoder is implemented using a 0.18-[micro]m CMOS process. The decoder runs correctly at the frequency of 200 MHz, which enables almost 1 Gbps decoding throughput. Since the proposed decoder occupies an area of 10.08 [mm.sup.2], it is less than one fifth of area compared to the previous architecture. Index Terms--Channel coding, decoder, factor graph, low density parity check (LDPC) code, matrix permutation, scheduling.

To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.compeleceng.2005.08.001 Byline: Vidhyacharan Bhaskar Keywords: Synchronization and execution processors; Multi-programming; Queue lengths; Response times; Utilizations; Normalization constant; Throughput Abstract: In this paper, a closed queuing network model with both single and multiple servers has been proposed to model dataflow in a multi-threaded architecture. Multi-threading is useful in reducing the latency by switching among a set of threads in order to improve the processor utilization. Two sets of processors, synchronization and execution processors exist. Synchronization processors handle load/store operations and execution processors handle arithmetic/logic and control operations. A closed queuing network model is suitable for large number of job arrivals. The normalization constant is derived using a recursive algorithm for the given model. State diagrams are drawn from the hybrid closed queuing network model, and the steady-state balance equations are derived from it. Performance measures such as average response times and average system throughput are derived and plotted against the total number of processors in the closed queuing network model. Other important performance measures like processor utilizations, average queue lengths, average waiting times and relative utilizations are also derived. Author Affiliation: Departement Genie des Systemes, d'Information et de Telecommunication, Universite de Technologic de Troyes, 12 Rue Marie Curie, 10010 Troyes Cedex, France Article History: Received 3 May 2005; Accepted 16 August 2005

Random finite sets (RFSs) are natural representations of multi-target states and observations that allow multi-sensor multi-target filtering to fit in the unifying random set framework for data fusion. Although the foundation has been established in the form of finite set statistics (FISST), its relationship to conventional probability is not clear. Furthermore, optimal Bayesian multi-target filtering is not yet practical due to the inherent computational hurdle. Even the probability hypothesis density (PHD) filter, which propagates only the first moment (or PHD) instead of the full multi-target posterior; still involves multiple integrals with no closed forms in general. This article establishes the relationship between FISST and conventional probability that leads to the development of a sequential Monte Carlo (SMC) multi-target filter. In addition, an SMC implementation of the PHD filter is proposed and demonstrated on a number of simulated scenarios. Both of the proposed filters are suitable for problems involving nonlinear non-Gaussian dynamics. Convergence results for these filters are also established.

We consider the flow dynamics of a tandem production system formed by two failure-prone machines separated by a buffer stock. The production rates of the machines are regulated by a feedback mechanism which solves an associated optimal control problem with an average cost criterion. The cost structure penalizes both the entrance into and the sojourn on the buffer boundaries. The generic structure of the optimal control involves four buffer content thresholds. When the buffer content crosses these thresholds, the production rates are tuned to reduce the tendency to enter into the buffer boundaries. Using the fluid modelling framework, we obtain analytical results for the stationary buffer level distribution in the case where an operating machine can produce with, either a 'nominal' or a 'reduced' rate. In the stationary regime, the optimal positions of the buffer thresholds, the throughput and the average buffer content are presented., 1. Introduction The presence of a buffer stock between two failure-prone machines [M.sub.1] and [M.sub.2] enhances the global throughput of the installation and its quantitative effect is calculated for example [...]