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A compact Si-nanowire-based reflective arrayed-waveguide grating (AWG) for dense wavelength-division multiplexing is proposed. At the end of each waveguide in the array, there is an individual photonic crystal (PhC) reflector, which makes the AWG layout design very flexible. All the PhC reflectors are with the same design. With such a design, the total size of the AWG (de)multiplexer is reduced by more than a half. The reflection efficiency of the used PhC reflectors is enhanced by optimizing the taper between the arrayed waveguides and the PhC reflector. A 200 GHz AWG (de)multiplexer is designed and fabricated as an example. The total size is only about 193 [micro]m x 168 [micro]m. OCIS codes: 230.7408, 230.5298.

This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- [micro]m CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation. Index Terms--I/O, multiplexer, MUX, serdes, serializer.

This paper proposes a computational, very efficient, approach for designing a novel family of M-channel maximally decimated nearly perfect-reconstruction cosine-modulated transmultiplexers. This approach is referred to as the generalized windowing method for transmultiplexers because after knowing the transmission channel a proper weighted sum of the inter-channel and inter-symbol interferences can be properly taken into account in the optimization of the window function, unlike in other existing windowing techniques. The proposed approach has also the following two advantages. First, independent of the number of subchannels and the common order of the subchannel filters, the number of unknowns is only four. Second, the overall optimization procedure is made considerably fast by estimating the above-mentioned sum in terms of two novel measures, namely, the signal to inter-symbol and the signal to inter-channel interferences, which are very easy to evaluate. Furthermore, when the transmission channel is not considered in the design, a table is provided, which contains the parameters for designing the prototype filter directly by using the windowing method without any time-consuming optimization. When comparing the resulting transmultiplexers with the corresponding perfect-reconstruction designs (the same number of subchannels and same prototype filter order), the levels of interferences are practically the same. However, when the system is affected by a strong narrowband interference, the proposed transmultiplexers outperform their PR counterparts. Design examples are included illustrating the efficiency of the proposed design approach over other existing techniques based on the use of the windowing method. Index Terms--Filterbanks, linear phase, nearly-perfect reconstruction, optimization, transmultiplexers.

MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-[micro]m CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide. Index Terms--Current mode logic (CML), delay modeling, high-speed multiplexers, optimization, ring oscillators.

Two typical MCDD (Multi-Carrier Demultiplexer/Demodulator) architectures, M-MCD (Multistage Multicarrier Demultiplexer) and PPF (Polyphase FFT) suitable for multimedia service via the on-board processing (OBP) satellite, are analytically modeled and their error performances are numerically evaluated in the presence of five degrading factors including: narrow-band AWGN, carrier frequency offset, phase error, ISI and quantization error. Cumulative effects of these factors on the BERs of the two different MCDD structures are also assessed and compared for possible tradeoff under MF-TDMA (Multi-Frequency Time Division Multiplex Access) scheme using QPSK modulation. Results show that both architectures are commonly vulnerable to most degrading factors. However, combined effect of phase error with AWGN is more critical to M-MCD than PPF. In addition, PPF method proves to be more sensitive to quantization error than M-MCD, When all five degrading factors are considered, MCDD using PPF method exhibits better BER performance than that of M-MCD, especially when carrier phase error is significant. Index Terms--BER, frequency offset, guard-band, ISI, MCDD (Multi-Carrier Demultiplexer/Demodulator), M-MCD (Multistage Multicarrier Demultiplexer), narrow-band AWGN, OBP (On-Board Processing), phase error, PPF (Poly-Phase FFT), quantization error.

A reconfigurable optical logic unit that can execute any binary logic and arithmetic operation on the same hardware with different configurations is proposed. The design, based on cascaded terahertz optical asymmetric demultiplexer switches, introduces reconfigurability with the help of electro-optic switches. The model is simple and practicable. OCIS codes: 200.4660, 200.4560, 200.4650, 220.4830, 230.4320, 060.4510.

A design method is presented for contiguous-channel multiplexing filters with many channels covering a wide band-width. The circuit topology extends previous work on cochlea-like channelizers by introducing multiple resonator-channel filter sections. The new design provides increased stopband rejection, lower insertion loss, and improved passband shape compared with the earlier version while retaining a simple design method and a compact layout, and requires no post-fabrication tuning. Results of a three-pole ten-channel channelizer covering from 182 MHz to 1.13 GHz with 17.5% bandwidth channels and 1.1-dB insertion loss are presented, and agree well with theory. A discussion of the power handling of planar channelizers is also presented. Index Terms--Channelizer, cochlea, filter, manifold, multiplexer.

This paper introduces a multimode transmultiplexer (TMUX) structure capable of generating a large set of user-bandwidths and center frequencies. The structure utilizes fixed integer sampling rate conversion (SRC) blocks, Farrow-based variable interpolation and decimation structures, and variable frequency shifters. A main advantage of this TMUX is that it needs only one filter design before-hand. Specifically, the filters in the fixed integer SRC blocks as well as the subfilters of the Farrow structure are designed only once. Then, all possible combinations of bandwidths and center frequencies are obtained by properly adjusting the variable delay parameter of the Farrow-based filters and the variable parameters of the frequency shifters. The paper includes examples for demonstration. It also shows that, using the rational SRC equivalent of the Farrow-based filters, the TMUX can be described in terms of conventional multirate building blocks which may be useful in further analysis of the overall system. Index Terms--Muitimode communications, transmultiplexers (TMUXs), sampling rate conversion (SRC).

A small-animal positron emission tomography (PET) scanner using PS-APD (position-sensitive avalanche photodiode) detectors has been developed for simultaneous PET/MRI imaging. In this scanner, up to 16 detector modules (one PS-APD per module) are used, and each detector module produces 4 signals to be digitized with their peak values. This leads to as many as 64 analog outputs to the data acquisition (DAQ) system, requiring 64 DAQ channels. In the future, the system will be extended to 32 modules, resulting in 128 channels. It is possible to sample all channels simultaneously, but most of them do not contain useful data, since only one coincidence event (producing data on 8 channels) is identified each time. The purpose of this work was to develop a general-purpose method for reducing the number of analog inputs to the data acquisition for the sparse fast analog signals produced in a PET scanner. To achieve this, a multiplexer board was designed to sample coincidence events from the PET scanner. The effect of the multiplexer on signal quality was evaluated and the average peak-to-valley ratios in detector flood histograms with and without multiplexer were 2.97 and 3.02 respectively. On-board coincidence, pile-up rejection and multiple coincidence rejection functions were implemented and worked as expected. The dead time performance was also characterized. Index Terms--Avalanche photodiodes, data acquisition, multiplexing, positron emission tomography (PET).

Recent advances in the literature have shown that there exist systematic switched delay lines (SDL) construction methods for various types of optical buffers. A practical and challenging issue of the constructions of optical buffers that has not been addressed before is on the fault-tolerant capability of such constructions. In this paper, we focus on the constructions of fault-tolerant optical 2-to-1 first-in first out (FIFO) multiplexers. We consider a feedback system consisting of an (M + 2) x (M + 2) optical crossbar switch and M fiber delay lines with delays [d.sub.1], [d.sub.2], ..., [d.sub.M]. These M fiber delay lines are connected from M outputs of the crossbar switch back to M inputs of the switch, leaving two inputs (resp., two outputs) of the switch for the two inputs (resp., two outputs) of the 2-to-1 multiplexer. In one of our previous papers, we have shown a necessary and sufficient condition on the fiber delays [d.sub.1], [d.sub.2], ..., [d.sub.M] (specifically, the condition in (A1) given in Section I) for such a feedback system to be operated as a 2-to-1 FIFO multiplexer with buffer [[summation].sup.M.sub.i=1] [d.sub.i], under a simple packet routing policy. In this paper, we obtain another condition on the fiber delays [d.sub.1], [d.sub.2], ..., [d.sub.M] (specifically, the condition in (A2) given in Section II-A) such that the feedback system can still be operated as a 2-to-1 FIFO multiplexer with buffer [[summation].sup.M-F.sub.i=1] [d.sub.i] even after up to F of the fibers are broken, where 0 [less than or equal to] F [less than or equal to] M - 1. We show that such a choice given by (A2) is better than a straightforward choice of the fiber delays. The idea behind the choice given by (A2) is to compose fibers with larger delays by using fibers with smaller delays so that the condition in (A1) is still satisfied even after up to F of the fibers are broken. Furthermore, we obtain the optimal choice (in the sense of maximizing the buffer size) among all of the choices given by (A2). In order to compare various choices of the fiber delays, we introduce the construction efficiency for a construction of a 2-to-1 FIFO multiplexer. By specifying a special choice of the fiber delays that satisfy the condition in (A2), we are able to derive a lower bound on the asymptotic construction efficiency for the optimal choice of the fiber delays. Our results show that the (asymptotic) construction efficiency for the optimal choice is much better than that for the straightforward choice of the fiber delays. Index Terms--Fault-tolerant capability, first-in first-out (FIFO) multiplexers, optical buffers, optical queues, optical switches, survivability, switched delay lines.

This paper presents a high-speed 1:2 demultiplexer (DEMUX) implemented in a 0.18-[micro]m CMOS process. By employing a capacitive-splitting architecture for the current-mode-logic latches, a significant speed improvement is achieved in the proposed DEMUX. Provided a [2.sup.23]--1 pseudorandom bit sequence from the pattern generator, the fabricated circuit operates at an input data rate up to 20 Gb/s. The fully integrated DEMUX consumes a dc power of 150 mW from a 2-V supply voltage. Index Terms--Bandwidth enhancement, capacitive-splitting latches, current-mode-logic (CML), demultiplexers (DEMUX), high-speed flip-flops, inductive peaking, optical-fiber communications.

A systematic method for multiplier matching which is based on the simple model of a bulk acoustic wave (BAW) or surface acoustic wave (SAW) resonator at frequencies far away from their resonance/antiresonance regime is presented. It is shown that this simple network has sufficient degrees of freedom to produce excellent results.

The design and demonstration of a holographic optical demultiplexer based on cascaded volume holographic gratings are presented. By serially adding a second holographic grating, which has a different grating period, slant angle, and center wavelength compared with those of the first grating, the operating wavelength range of the optical demultiplexer could be expanded, and, therefore, the number of channels of the holographic demultiplexer is doubled. As a result of the experiment, a 0.4 nm spaced 130-channel demultiplexer with a channel uniformity of 3.5 dB, a 3 dB bandwidth of 0.12 nm, and channel cross talk of -20 dB is experimentally achieved. OCIS codes: 090.7330, 062.4230.

In this paper, we prove a necessary and sufficient condition for the construction of 2-to-1 optical buffered first-in-first-out (FIFO) multiplexers by a single crossbar switch and fiber delay lines. We consider a feedback system consisting of an (M + 2) x (M + 2) crossbar switch and M fiber delay lines with delays [d.sub.1], [d.sub.2], ... ,[d.sub.M]. These M fiber delay lines are connected from M outputs of the crossbar switch back to M inputs of the switch, leaving two inputs (respectively, two outputs) of the switch for the two inputs (respectively, two outputs) of the 2-to-1 multiplexer. The main contribution of this paper is the formal proof that [d.sub.1] = 1 and [d.sub.1] [less than or equal to] [d.sub.1] + 1 [less than or equal to] 2[d.sub.1], ... ,M - 1, is a necessary and sufficient condition on the delays [d.sub.1], [d.sub.2], ... ,[d.sub.M] for such a feedback system to be operated as a 2-to-1 FIFO multiplexer with buffer [[SIGMA].sup.M.sub.i]=1 [d.sub.i] under a simple packet routing policy. Specifically, the routing of a packet is according to a specific decomposition of the packet delay, called the C-transform in this paper. Our result shows that under such a feedback architecture a 2-to-1 FIFO multiplexer can be constructed with M = (O(log B), where B is the buffer size. Therefore, our construction improves on a more complicated construction recently proposed by Sarwate and Anantbaram that requires M = O([square root of(B)]) under the same feedback architecture (we note that their design is more general and works for priority queues). Index Terms--Exact emulation, first-in-first-out (FIFO) queues, optical multiplexers, switched delay lines.

The theory of periodic structures, full-wave electromagnetic, and microwave circuit simulations were used to explain the resonant modes that propagate in metallic grids having rectangular unit cells constructed over a ground plane. The results suggested that these metallic grids could support two types of resonant modes that have rectangular and hyperbolic isofrequency dispersion contours.

Frequency-domain readout multiplexer for transition-edge sensor (TES) bolometers is described and measurements of an eight-channel multiplexer are presented. The demodulated noise spectra from multiplexed sensors are found to show the expected white noise levels at frequencdcies above 200 mHz.

Complexity of integrated circuits has led to millions of contacts and vias on every chip. To allow accurate yield evaluation, it is required to determine fail rates of < 10 faults per billion, which requires test structures with huge chains of 1 million or more contacts and vias. At the same time, contacts and vias are getting smaller, and thus their resistance is increasing for every new technology node. Consequently, the resistance of such chains becomes impossible to measure. To overcome this limit without increasing the number of measurement pads, we are proposing a passive multiplexer array of via chains, which breaks up a huge contact-via chain in many individually measurable subchains. Accuracy of fail rates will be increased since the fail rate can be determined based on many subchains, instead of being determined based on only one huge chain. Furthermore, this test structure better supports failure analysis since it is faster to locate a faulty contact or via. No additional devices or process steps are required which allows implementation as short flows for fast process problem debugging. Index Terms--Multiplexing, testing, test structure, yield.

A compact configuration for a coarse wavelength-division multiplexer (CWDM) and a coarse wavelength-division demultiplexer (CWDDM) that are based on reflection volume phase gratings is formed. The design and calculated results for four-channel CWDM and CWDDM configurations in the region near 800 nm are presented. Theoretical predictions are experimentally verified with a four-channel CWDDM whose channels are centered at 775, 800, 825, and 850 nm. OCIS codes: 050.7330, 060.4230.

In this paper, coded transmission over time-variant multipath Rayleigh-fading channels employing direct-sequence code division multiple access (DS-CDMA) is considered. Assuming ideal knowledge of the actual channel state and randomly chosen spreading sequences, we show that iterative multi-user interference suppression based on adapted minimum mean-squared error (MMSE) filters combined with serial successive cancellation and single user decoding can reach near optimum performance within a few iteration cycles. This holds even for doubly loaded systems, i.e., when the number of users K in the system is two times as large as the spreading factor N. Further, we evidence that for sufficiently reliable symbol estimates soft decision feedback can be replaced by hard decision feedback without any performance degradation but with significant savings in complexity. Index Terms--Direct-sequence code division multiple access (DS-CDMA), multiple access, multi-user detection.

The design of multichannel nonuniform-band transmultiplexers is considered.

The advances achieved in the design and development of high temperature superconducting 40 MHz bandwidth four-pole bandpass filters are reported. The power filters feature elliptic frequency response for 3.4 to 4.2 GHz extended C-band intended for output multiplexers of satellite communications. The use of the 'edge-current-free' disk concept and ring resonators allows the device to handle 60 W with low insertion loss and intermodulation despite its small size.

An 8:1 Rapid Single Flux Quantum (RSFQ) multiplexer (MUX) and an 1:8 RSFQ demultiplexer (DEMUX) operating at about 20 gigahertz were designed. The MUX receives lower data rate single-rail inputs and sequentially combines them into a single output. On the other hand, the DEMUX's inputs and outputs are both received as complementary dual-rail signals. The latter also features a 2-bit, self-clocked dual rail T flip-flop module.

Hierarchical layout methods were used in designing complex devices such as 2-to-1 and 4-to-1 multiplexers and an eight-function bit-slice arithmetic logic unit (ALU) that are based on quantum-dot cellular automata (QCA) devices. Hierarchical methods rely on the local nature of the Coulombic interaction between QCA cells. The QCA devices are made up of an array of cells that are in turn made up of a small number of quantum dots. The ALU is implemented using 1245 cells, which is the largest QCA device ever designed and simulated.

The general equations for parameters of concave grating mounts that provide stationary and superstationary astigmatism at the wavelength of correction are derived for the first time, to the best of our knowledge. These can be used to design grating multi/demultiplexers for wavelength-division multiplexed optical communication systems and high-resolution, narrow-band spectrographs. Important special cases of stationary anastigmatic mounts and their performance are presented. Key words: Diffraction gratings, astigmatism, spectrographs, multi/demultiplexers.

In code-division multiple access (CDMA) systems, the optimal multiuser detection is equivalent to an unconstrained quadratic bivalent optimization problem, and its computational complexity increases exponentially with the number of users. In this paper, we propose several new suboptimal detectors with a greatly reduced computational complexity based on a local minimization algorithm for a synchronous CDMA system. The performances of these detectors are compared with those of the conventional, optimal, and several other suboptimal detectors.

Many filters, power deviders and non reciprocal circuits such as a lumped element circulators used for broadcasting, communications and CATV, are using the parallel coupled lines together with the high dielectric constant ceramics and ferrite. It is important to design such a devices, that the capacities and inductances per unit length of the multi-distributed lines are determined by simple ways. This paper shows the method of the simple method to determine the values of the multi-lines sometimes in anisotropic medium by proposed methods using the two dimensional resistive sheet or equivalent computer method. The values is used for obtaining the effective dielectric constant and the effective permeability which is required for the estimations of the qusi-TEM mode in the case of the small sectional dimension comparing the wave length. The method to obtain the inductance was introduced by Babinet' principle.

Optical properties and taper profiles of 1.31/1.55-[[micro]meter] wavelength-division-multiplexing (WDM) fiber couplers have been experimentally analyzed. A newly developed microheater was used for the fabrication in air. The elongation lengths were controlled so that the fourth coupling peak would reach the 1.55-[[micro]meter] wavelength. The wavelength difference [Delta][Lambda] between the peak coupling wavelength of 1.55 [[micro]meter] and that around 1.31 [[micro]meter] decreased linearly at each fusion temperature with the fusion time. At each fusion temperature, the [Delta][Lambda] value decreased linearly with the elongation length and decreased exponentially with the neck width. The [Delta][Lambda] value and the taper shape at the minimum limit of the degree of fusion were estimated. The fabrication condition and the taper shape for 1.31-[[micro]meter] and 1.55-[[micro]meter] WDM coupling were also analyzed. Key words: Fiber coupler, microheater, wavelength-division-multiplexing coupler, taper.

This work addresses the problem of the fundamental limitations to the optimum performance of diplexers employing three-port junctions and preassigned branching filters. In this situation it is a common misconception that optimum results are achieved by utilizing a good power divider closed by two good branching filters. From the properties of the S-matrix of a three-port junction, we show this not to be the case and derive a set of necessary conditions to be satisfied in order that the junction be successfully employed in the realization of diplexers. We derive explicit expressions for the positions at which the filters must be placed in the junction arms for optimum diplexer performance, resulting in considerable simplification of the difficult diplexer synthesis problem. A theorem on the maximum achievable bandwidth is proved and validated by means of two practical examples.

The objective of this short paper is twofold: 1) to present experimental and computer-simulated results for a number of singlemode and dual-mode high-temperature superconductor (HTS) filters; and 2) to present the measured performance of an integrated 3-channel circulator-coupled multiplexer employing dual-mode HTS thin film filters. The CAD algorithm used to design the HTS filters is also described. The results presented demonstrate the feasibility of building C-band compactsize superconductive multiplexers.

A new computer-aided procedure of designing waveguide manifold multiplexers, which combines a rigorous numerical analysis of electromagnetic characteristics of the key elements of the structure and a simple circuit engineering design technique, is proposed. This procedure enables one to obtain the required multiplexer characteristics without any experimental corrections at the minimum computer time expense. Typical design results are given to demonstrate the efficiency of the method.

Frequency multiplexers of the manifold type, in which individual channel filters connect to a main trunk line without the use of isolating directional circuit components, are noted for their compactness, achieved through controlled signal interactions among channel circuits. A major drawback often associated with manifold designs is the potentially large number of network variables that must be handled simultaneously. The new multiplexer design approach being presented utilizes infinite-array prototype circuits based on logarithmic-periodic principles which, in turn, allow a significant reduction in the simultaneous-variable count. The technique is not confined to manifold architectures and can accommodate both contiguous and noncontiguous channels with a wide variety of frequency band allocations. The versatility of the approach is illustrated by two experimental contiguous-band five-channel multiplexer circuits that operate at C- and X-band frequencies, with one circuit designed for equal fractional bandwidths of 20%, and the other for constant absolute bandwidths of 800 MHz. These examples are believed to represent the first practical and successful utilizations of logarithmic periodicity in microwave multiport network design.

The design of microwave filters and multiplexers requires a common step before actual hardware implementation, namely, the identification of a number of specific ideal electrical components with actual waveguide discontinuities. In the past, this step was accomplished semi-analytically using approximate single-mode discontinuity models. The complete filter or multiplexer could then be assembled, but additional final tuning or optimization with a large number of parameters was generally required. In this paper, we propose an alternative technique for the design of microwave filters or multiplexers that directly uses a full-wave electromagnetic simulator and that effectively decomposes the complex design task into a series of simple subtasks with clearly identified objectives. The procedure described only involves a limited number of actual physical parameters at each step so that it is computationally very efficient and rapidly convergent.

A new circuit structure for microwave frequency doublers is presented, which features effective suppression of fundamental and odd harmonics (> 50 dB), conversion gain (> 3 dB), and simplicity of the circuit itself. Furthermore, it can be used in both balanced and unbalanced output configurations, without requiring baluns or transformers. A novel differential amplifier developed as part of the doubler circuit is also described in detail. It used an inductor to replace the active current source in conventional differential amplifiers, which simplified the circuit and, more importantly, enabled the amplifier to operate at high microwave frequencies. Experimental results are given in the paper.

This paper presents a design method for phase-locked devices such as frequency dividers or injection-locked oscillators. The method requires a full nonlinear analysis of the circuit. This analysis relies upon Harmonic Balance techniques and is suitable for monolithic circuits simulation. First, a modified formulation of the general harmonic balance equation is proposed which includes the presence of probes. These probes allow us to suppress the degenerated solution of the HB equation in autonomous cases. Moreover, a global stability analysis of phase-locked regimes is carried out. It provides invaluable information on the nonlinear behavior of the device. In particular, synchronization bandwidths as well as power ranges for which the circuit can be synchronized are obtained from the stability loci drawn in the parameter space. All these features have been used to design a broadband monolithic frequency divider, and the simulated and experimental results have been compared with very good accuracy. Therefore, the method proposed is a very useful tool for the design of potentially unstable circuits.

A hybrid procedure is introduced for computer-aided design (CAD) of manifold multiplexers without tuning elements. The procedure is based on: 1) a standard initial design with a simple network prototype; 2) a hybrid optimization with the multiplexer manifold rigorously described by a full-wave model and filters still described in terms of their network prototype; and 3) a final full-wave optimization of the entire structure. The proposed approach drastically reduce computer time while making it feasible to perform a very accurate full-wave optimization which in turn allows the avoidance of using tuning elements. An example illustrates and validates the CAD procedure. Index Terms--Filters, modal analysis, multiplexers, optimization.