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Modern software application development imposes standards regarding high performance, scalability, and minimal system latency. Multi-threading asynchronous programming is one of the standard solutions proposed by the industry for achieving such objectives. However, the recent introduction of the reactive programming interface in Java presents a potential alternative approach for addressing such challenges, promising performance improvements while minimizing resource utilization. The research examines the migration process from the asynchronous paradigm to the reactive paradigm, highlighting the implications, benefits, and challenges resulting from this transition. To this end, the architecture, technologies, and design of a support application are presented, outlining the practical aspects of this experimental process while closely monitoring the phased migration. The results are examined in terms of functional equivalence, testing, and comparative analysis of response times, resource utilization, and throughput, as well as the cases where the reactive paradigm proves to be a solution worth considering. Across multiple scenarios, the reactive paradigm demonstrated advantages such as up to 12% reduction in memory usage, 56% faster 90th percentile response times, and a 33% increase in throughput under high-concurrency conditions. However, the results also reveal cases, such as data-intensive scenarios, where asynchronous programming outperforms reactive approaches. Additionally, possible directions for further research and development are presented. This paper not only investigates the design and implementation process but also sets a foundation for future research and innovation in dependable systems, collaborative technologies, sustainable solutions, and distributed system architecture. [ABSTRACT FROM AUTHOR]

The numba-mpi package offers access to the Message Passing Interface (MPI) routines from Python code that uses the Numba just-in-time (JIT) compiler. As a result, high-performance and multi-threaded Python code may utilize MPI communication facilities without leaving the JIT-compiled code blocks, which is not possible with the mpi4py package, a higher-level Python interface to MPI. For debugging or code-coverage analysis purposes, numba-mpi retains full functionality of the code even if the JIT compilation is disabled. The numba-mpi API constitutes a thin wrapper around the C API of MPI and is built around Numpy arrays including handling of non-contiguous views over array slices. Project development is hosted at GitHub leveraging the mpi4py/setup-mpi workflow enabling continuous integration tests on Linux (MPICH, OpenMPI & Intel MPI), macOS (MPICH & OpenMPI) and Windows (MS MPI). The paper covers an overview of the package features, architecture and performance. As of v1.0, the following MPI routines are exposed and covered by unit tests: size/rank, [i]send/[i]recv, wait[all|any], test[all|any], allreduce, bcast, barrier, scatter/[all]gather & wtime. The package is implemented in pure Python and depends on numpy, numba and mpi4py (the latter used at initialization and as a source of utility routines only). The performance advantage of using numba-mpi compared to mpi4py is depicted with a simple example, with entirety of the code included in listings discussed in the text. Application of numba-mpi for handling domain decomposition in numerical solvers for partial differential equations is presented using two external packages that depend on numba-mpi: py-pde and PyMPDATA-MPI.

The development vector of modern central processing units, which increasingly involves using a more significant number of cores and prioritizing parallelism over the high power of a single computational unit, presents new challenges for the existing software design. This work investigates and addresses the problem of access to shared memory in multithreaded environments, such as operating systems, interactive distributed computing systems, and high-performance simulation systems. Thus, the object of study is a non-blocking approach to organizing access to memory and performing basic operations with it through non-blocking synchronization. The research methods include developing an approach to organizing access to shared memory using the doubleword compare-and-swap algorithm, followed by a theoretical and practical comparison of the resulting outcome with the standard blocking access algorithm to shared memory for different configurations of the number of threads and the number of simultaneous memory access attempts. Additionally, testing was conducted within the framework of an unnamed closed-source project by integrating the solution into it, followed by A/B testing. The results showed that using non-blocking approaches is advisable, especially in comparison with locking approaches, which demonstrated a performance degradation relative to the standard allocation algorithm by more than 300 %, while non-blocking approaches provided an improvement of 40–90 %. It was also found that using hybrid approaches to the organization of shared memory systems at the software level can lead to more stable results and mitigate application performance degradation compared to classical approaches such as buddy algorithms or free lists. Despite the results obtained, the author remains cautious about the idea of memory management and pool organization at the software level and does not recommend using specialized allocation algorithms without an urgent need to speed up memory allocation itself. The purpose of these structures is still not to improve software performance directly but to enhance and speed up access to the data stored in them. [ABSTRACT FROM AUTHOR]

Simultaneous Multi-Threading (SMT) processors provide improvement over the traditional out-of-order superscalar architecture by allowing instructions from several independent threads to execute out-of-order concurrently. Maintaining the accuracy of values read from and written to memory is a great bottleneck for processor performance, as loads must stall execution until all prior store addresses are known or risk reading invalid data. Prior research in this area has mainly focused on superscalar architecture, as such, it is only natural to extend memory dependence speculation techniques to an SMT architecture. In this paper, we allow for loads among threads to execute as soon as their addresses are resolved without checking for prior memory address conflicts. Stores also perform a check on all later loads to see if any read was too early due to an address match, if so, the processor state is recovered, and the load re-issued. This aggressive technique allows for the greatest potential instructions per clock cycle gains over predictive techniques as the pipeline is never stalled for loads. Our simulations show that an overall IPC gain up to 12% and 10% is possible for both 4-threaded and 8-threaded workloads respectively. Conversely, a maximum overall IPC loss of at least 2.3% and 2% for 4-threaded and 8-threaded workloads respectively was also observed. [ABSTRACT FROM AUTHOR]

In recent times, there has been a noticeable surge in the inclination towards the implementation of network automation solutions. This trend is driven by the objective of optimizing network availability within the context of hybrid data center networks, which are becoming increasingly prevalent. Reliability, performance, scalability, and minimal resource overhead are crucial solution design characteristics that significantly impact the decisionmaking process regarding adoption. Recent research has shown that 90% of network outages happen because of human factors and 69% of respondents manage their network with manual method. That high human error of up to 90%, occurs when configuring network devices using manual method. These problems had a negative impact on the functioning of the organization and were harmful to the user. In this research, we investigate solutions to reduce network outage that caused human error using network automation using the Python programming language and multi-threading method. This network automation will reduce configuration time, eliminate human error, and significantly increase efficiency. The aim of this research is to investigate the efficacy of network automation using Python and multi-threading to reduce network outages.The method used in this research is a parallel or multi-tread execution process method using GNS3 as network simulator. Based on experimental results, the multithread automation approach is significantly faster than both the serial automation method (67 seconds) and the manual method (248 seconds), this method requiring only 41 seconds to configure all Cisco router devices. If you're looking for speed, look no farther than the multithread automation approach, which is 6 times quicker than the manual method and 3.7 times quicker than the serial automation approach. The findings of this study have substantial and immediate implications for the ability of network engineers to speed up the configuration of networks and lower the rate of human error in doing so. [ABSTRACT FROM AUTHOR]

Modern software application development imposes standards regarding high performance, scalability, and minimal system latency. Multi-threading asynchronous programming is one of the standard solutions proposed by the industry for achieving such objectives. However, the recent introduction of the reactive programming interface in Java presents a potential alternative approach for addressing such challenges, promising performance improvements while minimizing resource utilization. The research examines the migration process from the asynchronous paradigm to the reactive paradigm, highlighting the implications, benefits, and challenges resulting from this transition. To this end, the architecture, technologies, and design of a support application are presented, outlining the practical aspects of this experimental process while closely monitoring the phased migration. The results are examined in terms of functional equivalence, testing, and comparative analysis of response times, resource utilization, and throughput, as well as the cases where the reactive paradigm proves to be a solution worth considering. Across multiple scenarios, the reactive paradigm demonstrated advantages such as up to 12% reduction in memory usage, 56% faster 90th percentile response times, and a 33% increase in throughput under high-concurrency conditions. However, the results also reveal cases, such as data-intensive scenarios, where asynchronous programming outperforms reactive approaches. Additionally, possible directions for further research and development are presented. This paper not only investigates the design and implementation process but also sets a foundation for future research and innovation in dependable systems, collaborative technologies, sustainable solutions, and distributed system architecture.

In the ship information big data system, aiming at the problems such as long time consuming, distortion of thermal map effect and poor tracking or lag in the roaming of map software when the client requests a large amount of historical data from the server and draws heat map in real time, this paper proposes an improved real-time generation strategy of map map of ship history activity. Based on the thermal map generation method with the idea of pixel clustering, this strategy uses the image enhancement algorithm based on nonlinear transformation and pixel complement method to correct and optimize the display distortion problems existing in the head map. On this basis, the dynamic loading and drawing strategy and multi-thread real-time mapping strategy are proposed to generate the heat map of the ship’s historical activities. Experiments show that the strategy proposed in this paper has been improved in the efficiency of heat map drawing, mapping effect and interactive experience of map software.

Cryptocurrency markets exhibit high volatility, necessitating accurate forecasting methods for effective decision-making. This paper presents an innovative approach that integrates web scraping from cryptocurrency websites with various deep-learning networks to predict cryptocurrency values for the following day. Our web scraping technique integrated with concept like multi-threading focuses exclusively on cryptocurrency websites, extracting essential data such as live price records making use of crucial computer technology concepts like multi-threading. Combined with a suite of deep learning models including LSTM, GRU, and XgBoost, this data facilitates the modelling of temporal dependencies crucial for understanding cryptocurrency price dynamics. Through empirical evaluation, we determine the model that outperforms others and integrate it into a dashboard for real-time prediction. By leveraging real-time insights from web scraping, our model aims to enhance prediction accuracy. This research contributes to the advancement of predictive analytics in cryptocurrency trading, providing actionable insights for investors and analysts amidst fluctuating market conditions.

Copyright of Command Control & Simulation / Zhihui Kongzhi yu Fangzhen is the property of Command Control & Simulation Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

High performance computing (HPC) clusters are increasingly handling workloads where working data sets cannot be easily partitioned or are too large to fit into local node memory. In order to enable HPC workloads to access memory external to the node, HPE has defined a programming API (OpenFAM) for developing applications that use large‐scale disaggregated memory. In this paper we describe an open‐source reference implementation of OpenFAM that can be used on scale‐up machines, traditional HPC clusters, as well as emerging disaggregated memory architectures. We demonstrate the efficiency of the implementation using micro‐benchmarks on InfiniBand and Slingshot‐based clusters. [ABSTRACT FROM AUTHOR]

In view of the fact that most industrial and mining enterprises are in digital transformation at present, the digitized safety production monitoring data has the characteristics of strong real-time and huge data volume. The data volume of some systems, such as steel wire rope flaw detection system, is up to several hundred thousand pieces per second. The commonly used SQL database has been unable to cope with such a huge data storage and analysis task. A high-density data acquisition system with high concurrency and high density data processing capability based on NoSQL is constructed through NoSQL database, load balancing, multithreading, SOCKET and other technical systems. The system realizes the high-density access of safety production related data of industrial and mining enterprises, and meets the hard demand of high-density data sampling cycle.

The rapid development of information technology has made the amount of information in massive texts far exceed human intuitive cognition, and dependency parsing can effectively deal with information overload. In the background of domain specialization, the migration and application of syntactic treebanks and the speed improvement in syntactic analysis models become the key to the efficiency of syntactic analysis. To realize domain migration of syntactic tree library and improve the speed of text parsing, this paper proposes a novel approach—the Double-Array Trie and Multi-threading (DAT-MT) accelerated graph fusion dependency parsing model. It effectively combines the specialized syntactic features from small-scale professional field corpus with the generalized syntactic features from large-scale news corpus, which improves the accuracy of syntactic relation recognition. Aiming at the problem of high space and time complexity brought by the graph fusion model, the DAT-MT method is proposed. It realizes the rapid mapping of massive Chinese character features to the model's prior parameters and the parallel processing of calculation, thereby improving the parsing speed. The experimental results show that the unlabeled attachment score (UAS) and the labeled attachment score (LAS) of the model are improved by 13.34% and 14.82% compared with the model with only the professional field corpus and improved by 3.14% and 3.40% compared with the model only with news corpus; both indicators are better than DDParser and LTP 4 methods based on deep learning. Additionally, the method in this paper achieves a speedup of about 3.7 times compared to the method with a red-black tree index and a single thread. Efficient and accurate syntactic analysis methods will benefit the real-time processing of massive texts in professional fields, such as multi-dimensional semantic correlation, professional feature extraction, and domain knowledge graph construction. [ABSTRACT FROM AUTHOR]

In this work, we have prepared and analyzed three case studies comparing CPU and GPGPU calculations. After briefly introducing the topic of parallel programming by means of contemporary CPU and GPGPU technologies, we provide an overview of selected existing works closely related to the topic of the paper. For each of the case studies, a set of programs has been implemented using the following technologies: pure CPU, CPU SIMD, CPU multi-threaded, CPU multi-threaded with SIMD instructions, and GPU - Cuda. We also illustrate the basic idea of the operation of selected algorithms using code snippets. Subsequently, the particular implementations are compared, and obtained results are evaluated and discussed.

Nowadays, convolutional neural networks are among the most widely used types of deep learning networks thanks to their usefulness in many application domains. There are many efforts to find methods to increase their training and inference performance and efficiency. One of the most widely used technique to implement convolution consists of flattening tensors into 2D matrices and carrying out the operation through a matrix-matrix multiplication routine, which has highly optimized implementations in high-performance libraries. However, this kind of approach uses extra time and memory to transform and store the tensors involved. For this reason, direct convolution is becoming increasingly popular. Direct convolution can be implemented as a series of nested loops iterating over tensor dimensions and it does not require extra memory. In this work, we evaluate on various multi-core CPUs the performance and scalability effects deriving from different parallelization strategies, loop organizations, and SIMD-vectorization approaches with different compilers in relation with architectural aspects. We discuss each parameter thoroughly and distill our findings in a set of heuristics that can be used to quickly achieve a high-performance implementation in accordance to the underlying hardware and the characteristics of the convolutional layer at hand. By adopting a per-layer approach, we increase performance up to 60-70% compared to a static implementation for all the layers. Moreover, our results are comparable, or even better (up to $1.67\times $ speedup) than matrix-matrix multiplication-based convolution in a multi-core system.

Abstract This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics.

In fake news detection, intelligent optimization seems to be a more effective and explainable solution methodology than the black-box methods that have been extensively used in the literature. This study takes the optimization-based method one step further and proposes a novel, multi-thread hybrid metaheuristic approach for fake news detection in social media. The most innovative feature of the proposed method is that it uses a supervisor thread mechanism, which simultaneously monitors and improves the performance and search patterns of metaheuristic algorithms running parallel. With the supervisor thread mechanism, it is possible to analyse different key attribute combinations in the search space. In addition, this study develops a software framework that allows this model to be implemented easily. It tests the performance of the proposed model on three different data sets, respectively containing news about Covid-19, the Syrian War, and daily politics. The proposed method is evaluated in comparison to the results of fifteen different well-known deep models and classification algorithms. Experimental results prove the success of the proposed model and that it can produce competitive results. [ABSTRACT FROM AUTHOR]

In detection-free tracking, after users freely designate the location of the object to be tracked in the first frame of the video sequence, the location of the object is continuously found in the following video frame sequence. Recently, technologies using a Siamese network and transformer based on DNN modules have been evaluated as very excellent in terms of tracking accuracy. The high computational complexity due to the usage of the DNN module is not a preferred feature in terms of execution speed, and when tracking two or more objects, a bottleneck effect occurs in the DNN accelerator such as the GPU, which inevitably results in a larger delay. To address this problem, we propose a tracker scheduling framework. First, the computation structures of representative trackers are analyzed, and the scheduling unit suitable for the execution characteristics of each tracker is derived. Based on this analysis, the decomposed workloads of trackers are multi-threaded under the control of the scheduling framework. CPU-side multi-threading leads the GPU to a work-conserving state while enabling parallel processing as much as possible even within a single GPU depending on the resource availability of the internal hardware. The proposed framework is a general-purpose system-level software solution that can be applied not only to GPUs but also to other hardware accelerators. As a result of confirmation through various experiments, when tracking two objects, the execution speed was improved by up to 55% while maintaining almost the same accuracy as the existing method. [ABSTRACT FROM AUTHOR]

With the rapid development of mobile internet, Android applications have become an indispensable part of people's daily lives. However, as the functionality of applications continues to increase, complexity also rises, making it one of the major challenges to efficiently and stably run applications with limited system resources. Multi-threading and concurrency handling techniques provide effective means to address this issue. This paper first analyzes the current status and challenges of applying multi-threading and concurrency handling techniques in Android application development, proposes targeted performance optimization improvements, validates their effectiveness through experiments, and finally summarizes the research results and looks ahead to future research directions.

Coincidence processing in positron emission tomography (PET) is typically done during acquisition of the data. However, on the EXPLORER total-body PET scanner we plan, in addition, to store unpaired single events (i.e. singles) for post-acquisition coincidence processing. A software-based coincidence processor was developed for EXPLORER and its performance was assessed. Our results showed that the performance of the coincidence processor could be significantly impacted by the type of data storage (Peripheral Component Interconnect Express (PCIe)-attached solid state drive (SSD) versus RAID 6 hard disk drives (HDDs)) especially when multiple data files were processed in parallel. We showed that a 48-thread computer node with dual Intel Xeon E5-2650 v4 central processing units (CPUs) and a PCIe SSD was sufficient to process approximately 120 M singles s-1 at an incoming singles rate of approximately 150 Mcps. With two computer nodes, near real-time coincidence processing became possible at this incoming singles rate.

This paper introduces an event‐based computing paradigm, where workers only perform computation in response to external stimuli (events). This approach is best employed on hardware with many thousands of smaller compute cores with a fast, low‐latency interconnect, as opposed to traditional computers with fewer and faster cores. Event‐based computing is timely because it provides an alternative to traditional big computing, which suffers from immense infrastructural and power costs. This paper presents four case study applications, where an event‐based computing approach finds solutions to orders of magnitude more quickly than the equivalent traditional big compute approach, including problems in computational chemistry and condensed matter physics. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

In high-performance computing, selecting the appropriate thread count has a significant impact on execution time and energy consumption. On multi-core processor systems, it is widely believed that for maximal speedup, the total number of threads should match the number of cores. Thread migration rate, cache miss rate, thread synchronisation, and context switching rate are all impacted by changes in thread count at the hardware and OS levels. As a result, it is extremely difficult to analyse these factors for relatively complex multi-threaded programs and determine the optimal number of threads. The method put forward in this study is an enhancement of the conventional Manta-Ray Foraging Optimization, a bio-inspired approach that has been applied to a number of numerical engineering problems. The proposed approach makes use of three foraging steps: chain, cyclone, and somersault. Using the well-known benchmark suite PARSEC (The Princeton Application Repository for Shared-Memory Computers), the suggested work is simulated on an NVIDIA-DGX Intel Xeon-E5 2698-v4 processor. The findings demonstrate that the new modified AMRFO-based prediction model can choose the appropriate number of threads with fairly minimal overheads when compared to the current method. [ABSTRACT FROM AUTHOR]

As technology scales, transistors become smaller and aggressive power optimization techniques combined with high operation frequencies and performance-enhancing microarchitectural techniques are employed to achieve increasingly higher performance and power efficiencies. Unfortunately, these developments make the modern systems more vulnerable to soft errors, which are becoming a critical issues in both hardware and software domains. Motivated by this observation, in this work, we propose, implement, and evaluate two error propagation metrics in order to characterize error propagation at both software and hardware levels. The first metric aims to measure error propagation on program data structures, whereas the second one measures the fraction of corrupted locations in the cache memory structure for a given period of time. We evaluate our proposed metrics by performing an empirical study of two application programs using both single-threaded and multi-threaded executions, and varying various experimental parameters such as thread count, error rate, location of errors, and architectural parameters. Our extensive experimental analysis reveals that error propagation over program data structures is highly dependent on application behavior.Further, depending on the cache parameters used, propagation of errors on cache can exhibit different patterns. This paper also discusses how our observed error propagation trends in program data structures and data caches are correlated with each other, focusing in particular on the differences in error propagation speeds in application data structures and data caches. [ABSTRACT FROM AUTHOR]

The numerical simulation of dendritic crystal growth with melt convection in complex domains is of great significance in academic research and industrial application. However, the processing of complex boundaries, huge computational costs of three-dimensional problems and strong nonlinear coupling of multiple equations make the numerical simulation of dendritic crystal growth face great challenges. In this study, a new dendritic crystal growth phase field model with melt convection in complex domains is firstly established. The new model avoids the difficulty of dealing with complex boundaries and can be computed on the rectangle or parallelepiped. The modeling process adopts the idea of the multi-component Allen–Cahn equation modeling idea, weight factor and Lagrange multiplier. Secondly, for the efficient computation, a second-order dimension splitting numerical scheme is developed for the new model. It decomposes the high-dimensional problem into a series of one-dimensional problems which can be computed by multi-threading. Finally, to achieve decoupling, the nonlinear and coupled terms are explicitly computed, and stabilization terms are added to enhance the long-time computational stability. The accuracy and efficiency of the dimension splitting method are verified by numerical experiments. The numerical simulations of fourfold, fivefold and sixfold anisotropic single dendritic crystal growth and multiple dendritic crystal growth show that complex domains and melt convection greatly affect the normal growth pattern of dendritic crystal growth. In addition, the numerical experiments also show that when the dendritic crystal growth rate is slow, the melt convection can promote the growth rate under the same conditions. • A new dendritic crystal growth model with melt convection in complex domains is established for multi-threading simulation. • A dimension splitting scheme is proposed for the new model which can be computed by multi-threading. • A large number of dendritic crystal growth in complex domains is numerically simulated. [ABSTRACT FROM AUTHOR]

The evolution of simulation and implementation of P systems has been intense since the theoretical model of computation was created. In the field of software simulation of P systems, the proposals made so far have taken advantage mainly of the parallelism of GPUs, but not of the parallelism of existing multi-core processors. This paper proposes a new model for simulating P systems using a multi-threaded approach in a multi-core processor. This simulation approach establishes a new paradigm that is entirely in line with the philosophy of P-systems: since objects must react in parallel, asynchronously and autonomously with other objects, simulation using multiple synchronized threads completely mimics the behavior of objects within a membrane. This proposal has been implemented and tested using a simulator programmed in C#, and its correct operation has been tested for confluent and non-confluent systems. The experimental results confirm that the simulator scales well with the number of hardware threads of a multiprocessor. The obtained results show that the new model is correct and that it can be extended to other more complex types of P systems, in order to discover which are the limit of this multi-threaded approach when running it in multi-core processors. • A pioneering approach for membrane simulation based on CPU multi-threading. • The approach can be straightforwardly used to simulate generic transitive P systems. • A multi-threaded implementation of the P system simulator has been tested. • Performance speedup results directly proportional to the number of hardware threads. [ABSTRACT FROM AUTHOR]

Scalability is one of the most important quality attribute of softwareintensive systems, because it maintains an effective performance parallel to the large fluctuating and sometimes unpredictable workload. In order to achieve scalability, thread pool system (TPS) (which is also known as executor service) has been used extensively as a middleware service in software-intensive systems. TPS optimization is a challenging problem that determines the optimal size of thread pool dynamically on runtime. In case of distributed-TPS (DTPS), another issue is the load balancing b/w available set of TPSs running at backend servers. Existing DTPSs are overloaded either due to an inappropriate TPS optimization strategy at backend servers or improper load balancing scheme that cannot quickly recover an overload. Consequently, the performance of software-intensive system is suffered. Thus, in this paper, we propose a new DTPS that follows the collaborative round robin load balancing that has the effect of a double-edge sword. On the one hand, it effectively performs the load balancing (in case of overload situation) among available TPSs by a fast overload recovery procedure that decelerates the load on the overloaded TPSs up to their capacities and shifts the remaining load towards other gracefully running TPSs. And on the other hand, its robust load deceleration technique which is applied to an overloaded TPS sets an appropriate upper bound of thread pool size, because the pool size in each TPS is kept equal to the request rate on it, hence dynamically optimizes TPS. We evaluated the results of the proposed system against state of the art DTPSs by a clientserver based simulator and found that our system outperformed by sustaining smaller response times. [ABSTRACT FROM AUTHOR]

Modern-day graph workloads operate on huge graphs through pointer chasing which leads to high last-level cache (LLC) miss rates and limited memory-level parallelism (MLP). Simultaneous Multi-Threading (SMT) effectively hides the memory access latencies for multi-threaded graph workloads provided that sufficient threads are supported in hardware. Unfortunately, providing a sufficiently large number of physical threads incurs an unjustifiably high hardware cost for commodity SMT processors which typically implement only two physical hardware threads. Ideally, we would like to achieve aggressive-SMT performance when running graph workloads on modest commodity processors. In this paper, we propose Virtualized Multi-Threading (VMT), a low-overhead multi-threading paradigm for accelerating graph workloads on commodity processors. Unlike prior multi-threading paradigms, VMT virtualizes both the physical hardware threads and the architecture state: VMT maps a large number of logical software threads to a small number of physical hardware threads, while maintaining the architecture state of the logical threads in the processor's cache hierarchy. Implemented on top of a quad-core 2-way SMT processor, VMT achieves an average speedup of 1.74× for a set of representative graph workloads, while incurring minimal hardware cost (195 bytes per core to support up to 32 logical threads). VMT's low hardware cost paves the way for implementation in commodity processors. [ABSTRACT FROM AUTHOR]

Mining frequent itemsets is an area of data mining that has beguiled several researchers in recent years. Varied data structures such as Nodesets, DiffNodesets, NegNodesets, N-lists, and Diffsets are among a few that were employed to extract frequent items. However, most of these approaches fell short either in respect of run time or memory. Hybrid frameworks were formulated to repress these issues that encompass the deployment of two or more data structures to facilitate effective mining of frequent itemsets. Such an approach aims to exploit the advantages of either of the data structures while mitigating the problems of relying on either of them alone. However, limited efforts have been made to reinforce the efficiency of such frameworks. To address these issues this paper proposes a novel multithreaded hybrid framework comprising of NegNodesets and N-list structure that uses the multicore feature of today's processors. While NegNodesets offer a concise representation of itemsets, N-lists rely on List intersection thereby speeding up the mining process. To optimize the extraction of frequent items a hash-based algorithm has been designed here to extract the resultant set of frequent items which further enhances the novelty of the framework. [ABSTRACT FROM AUTHOR]

The internet of things (IoT) concept has been extremely investigated in many modern smart applications, which enable a set of sensors to either process the collected data locally or send them to the cloud for remote processing. Unfortunately, cloud datacenters are located far away from IoT devices, and consequently, the transmission of IoT data may be delayed. In this paper, we investigate fog computing, which is a new paradigm that overcomes many issues of cloud computing. More importantly, dynamic task offloading in fog computing is a challenging problem that requires an optimal decision for processing the tasks that are generated in each time slot. Thus, exact optimization methods based on Lyapunov function have been widely used for solving dynamic offloading which represents an NP hard problem. To overcome the scalability issue of exact optimization techniques, we have explored famous population based meta-heuristics for optimizing the offloading process of a set of dynamic tasks using Orthogonal Frequency Division Multiplexing (OFDM) communication. Hence, a parallel multi-threading framework is proposed for generating the optimal offloading solution while selecting the best sub-carrier for each offloaded task. More importantly, our contribution associates a thread for each IoT device and generates a population of random solutions. Next, each population is updated and evaluated according to the proposed fitness function that considers a tradeoff between the delay and energy consumption. Upon the arrival of new tasks at each time slot, an evaluation is performed for maintaining some individuals of the previous population while generating new individuals based on some criteria. Our results have been compared to the results achieved using Lyapunov optimization. They demonstrate the convergence of the fitness function, the scalability of the parallel Particle Swarm Optimization (PSO) approach, and the performance in terms of the offline error and the execution cost. [ABSTRACT FROM AUTHOR]

Graph analytics are an emerging class of irregular applications. Operating on very large datasets, they present unique behaviors, such as fine-grained, unpredictable memory accesses, and highly unbalanced task level parallelism, that make existing high-performance general-purpose processors or accelerators (e.g., GPUs) suboptimal. To address these issues, research and industry are developing a variety of custom accelerator designs for this application area, including solutions based on reconfigurable devices (Field Programmable Gate Arrays). These new approaches often employ High-Level Synthesis (HLS) to Speed up the development of the accelerators. In this paper, we propose a novel architecture template for the automatic generation of accelerators for graph analytics and irregular applications. The architecture template includes a dynamic task scheduling mechanism, a parallel array of accelerators that enables supporting task-level parallelism with context switching, and a related multi-channel memory interface that decouples communication from computation and provides support for fine-grained atomic memory operations. We discuss the integration of the architectural template in an HLS flow, presenting the necessary modifications to enable automatic generation of the custom architectures starting from OpenMP annotated code. We evaluate our approach first by synthesizing and exploring triangle counting, a common graph algorithm, and then by synthesizing custom designs for a set of graph database benchmark queries, representing series of graph pattern matching routines. We compare the synthesized accelerators with previous state-of-the-art methodologies for the synthesis of parallel architectures, showing that the proposed approach allows reducing resource usage by optimizing the number of accelerators replicas without any performance penalty. [ABSTRACT FROM AUTHOR]

The last decade witnessed rapid increase in multimedia and other applications that require transmitting and protecting huge amount of data streams simultaneously. For such applications, a high-performance cryptosystem is compulsory to provide necessary security services. Elliptic curve cryptosystem (ECC) has been introduced as a considerable option. However, the usual sequential implementation of ECC and the standard elliptic curve (EC) form cannot achieve required performance level. Moreover, the widely used Hardware implementation of ECC is costly option and may be not affordable. This research aims to develop a high-performance parallel software implementation for ECC. To achieve this, many experiments were performed to examine several factors affecting ECC performance including the projective coordinates, the scalar multiplication algorithm, the elliptic curve (EC) form, and the parallel implementation. The ECC performance was analyzed using the different factors to tune-up them and select the best choices to increase the speed of the cryptosystem. Experimental results illustrated that parallel Montgomery ECC implementation using homogenous projection achieves the highest performance level, since it scored the shortest time delay for ECC computations. In addition, results showed that NAF algorithm consumes less time to perform encryption and scalar multiplication operations in comparison with Montgomery ladder and binary methods. Java multi-threading technique was adopted to implement ECC computations in parallel. The proposed multithreaded Montgomery ECC implementation significantly improves the performance level compared to previously presented parallel and sequential implementations. [ABSTRACT FROM AUTHOR]