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Terabit capacity optical engines for data center and access networks are gaining momentum supported by a pool of technological innovations that are promising low cost and simple design for a wide range of application use cases.

Widespread adoption of silicon photonics into datacenters requires that the integration of the driving electronics with the photonics be an essential component of transceiver development. In this article, we describe our silicon photonic transceiver design: a 2.5D integrated multi-chip module (MCM) for 4-channel wavelength division multiplexed (WDM) microdisk modulation targeting 10 Gbps per channel. A silicon interposer is used to provide connectivity between the photonic integrated circuit (PIC) and the commercial transimpedance amplifiers (TIAs). Error free modulation is demonstrated at 10 Gbps with -16 dBm received power for the photonic bare die and at 6 Gbps with -15 dBm received power for the first iteration of the MCM transceiver. In this context, we outline the different integration approaches currently being employed to interface between electronics and photonics - monolithic, 2D, 3D, and 2.5D - and discuss their tradeoffs. Notable demonstrations of the various integration architectures are highlighted. Finally, we address the scalability of the architecture and highlight a subsequent prototype employing custom electronic integrated circuits (EICs).

Custom accelerators improve the energy efficiency, area efficiency, and performance of deep neural network (DNN) inference. This article presents a scalable DNN accelerator consisting of 36 chips connected in a mesh network on a multi-chip-module (MCM) using ground-referenced signaling (GRS). While previous accelerators fabricated on a single monolithic chip are optimal for specific network sizes, the proposed architecture enables flexible scaling for efficient inference on a wide range of DNNs, from mobile to data center domains. Communication energy is minimized with large on-chip distributed weight storage and a hierarchical network-on-chip and network-on-package, and inference energy is minimized through extensive data reuse. The 16-nm prototype achieves 1.29-TOPS/mm2 area efficiency, 0.11 pJ/op (9.5 TOPS/W) energy efficiency, 4.01-TOPS peak performance for a one-chip system, and 127.8 peak TOPS and 1903 images/s ResNet-50 batch-1 inference for a 36-chip system.

Digital transceiver architectures offer the potential for achieving wireless hardware flexibility to frequency and modulation scheme for future-generation communications systems. Additionally, digital transmitters lend themselves to the use of switch-mode power amplifiers, which can have significantly higher efficiency than their linear counterparts. Two proposed architectures for realizing digital transmitters will be described in this work, both of which employ a hybrid combination of silicon integrated circuits (IC) and a power technology (e.g. GaN). This hybrid architecture takes advantage of the silicon to implement the high-complexity signal processing required for wireless communications, and uses power devices with high power density and low parasitic capacitance to sufficiently amplify the RF signals for transmission. Unfortunately, interfacing the low-power RF switching signals with off-chip high-power devices poses numerous design challenges, including: generation of integrated silicon power drivers with sufficient voltage swing for controlling power devices such as GaN, mitigation of on-chip current transients, wideband assembly interface from the silicon IC to the power device, and full system design verification using multiple process technologies. This work presents two CMOS driver architectures that can be used to interface low-power CMOS processing circuits with off-chip high-power devices. This work also details the performance limitations when assembling and interfacing multiple process technologies that are not co-located on the same IC. The main function of the driver circuitry within the digital transceiver system is to interface the low-power digital modulator to a large, high capacitance, off-chip power device. The driver must provide adequate transient current to charge/discharge the off-chip power devices' input capacitance through parasitic routing. Furthermore, the driver is designed to exhibit rise/fall times of less than 5% of the switching period and low jitter to meet RF signal quality requirements. Since silicon process technologies typically have much lower voltage breakdowns than those required to drive a power devie (e.g. GaN device), special driver architectures must be implemented to ensure the CMOS devices never exceed their breakdown voltages. Two architectures were implemented within this work to simultaneously achieve RF switching speeds and 5V signal swing from a 0.9V silicon CMOS process technology. The two architectures are: 1) a House-of-Cards configuration, and 2) a Cascode topology. These architectures will be detailed and compared with respect to performance in this presentation. Two of the most common techniques to assemble and connect a silicon IC, which includes the driver circuitry, and a (GaN) power device are: 1) direct wire bonding or flip-chip connection from the IC to the GaN, and 2) connection through a board or package interface circuit. Since most high-performance RF power devices such as GaN have negative threshold voltage, the driver (CMOS) IC must either: 1) have a supply and ground that are shifted to negative voltage values, or 2) decouple the IC's output from the GaN device's input in order to properly control the GaN. Off-chip decoupling is more easily implemented, but may limit maximum operating frequencies due to the added interface network and board/module parasitics. This work shall detail the interface models and compare the assembly procedures and potential performance limits when using both of these most common assembly techniques.

Simulation and experimental results of a time-delay photonic reservoir computer based on VCSEL and photodiode chips with multi-mode waveguide splitter and combiner is presented. The design is based on technology developed for a high bandwidth density optical mulit-chip module with polymer waveguides for optical interconnect applications. The number of virtual nodes in the reservoir can be adjusted by varying the feedback delay time and the input signal rate. Results on distorted signal recovery and non-linear waveform generation tasks are presented and are promising for the development of a platform for board-integrated photonic neural network architecture.

Emerging multi-chip module GPUs (MCM-GPUs) expend over 17% of the total power budget on chip interconnects and this fraction is expected to increase as chip size increases. Towards proactively managing the power consumption of these interconnects, we propose approximate pattern matching to predict future interconnect traffic from past observations. Compared to past prediction techniques such as Markov model (MM) and history table (HT), our proposed technique reduces average prediction error to 2.66% from 7.11% and 3.83% for MM and HT, respectively.

Performance and energy figures of Deep Neural Network (DNN) accelerators are profoundly affected by the communication and memory sub-system. In this paper, we make the case of a state-of-the-art multi-chip-module-based architecture for DNN inference acceleration. We propose a hybrid wired/wireless network-in-package interconnection fabric and a compression technique for drastically improving the communication efficiency and reducing the memory and communication traffic with a consequent improvement of performance and energy metrics. We assess the inference performance and energy improvement vs. accuracy degradation for different CNNs showing that up to 77% and 68% of inference latency reduction and inference energy reduction, respectively, can be obtained while keeping the accuracy degradation below 5% as respect to the original uncompressed CNN.

We demonstrate the first 2.5D integrated, wavelength division multiplexing, silicon photonic receiver. The multi-chip module utilizes a silicon interposer to integrate the four-channel photonic cascaded microdisk receiver with four electronic transimpedance amplifiers.

D-Band Radio-on-Glass (RoG) modules combining two highly integrated SiGe BiCMOS transceivers (TRX) with a record low-loss glass interposer technology are presented. The ICs operate at 115-155 GHz (Low-Band) and 135-170 GHz (High-Band). In this frequency range, a transmitter P sat up to 13 dBm and an average receiver NF of 8.5 dB is achieved. The integrated module supports TX constellations up to 512-QAM (2.2% EVM at 2 dBm output, 145 GHz) and data-rates up to 42 Gb/s (128-QAM). Measurements mimicking a 250-meter wireless-link demonstrate a maximum data-rate of 36 Gb/s using 64-QAM. The RoG modules represent the first low-cost and highly integrated solution for spectrally efficient backhaul systems in D-Band.

Currently, the miniaturization technology of wiring in Fan-Out Wafer Level Packaging (FO-WLP) is needful to multi chip module system fabrication using the re-distribution layer (RDL) wiring technologies. In addition, Fan-Out Package on Package (FO-PoP), in which a memory package is mounted on an application processor (AP) package, is adopted to suppress signal loss with the distance of long signal writing. In this paper, we report the dry etching technique for high-density FO-PoPThe first is the fabrication of polyimide (PI) vertical via to form in RDL. In the current mass production, the technique of photo-lithography and descum is widely used for the fabrication of PI via. The shape of typical via is the diameter of approximately 10um and aspect ratio (A.R) of approximately 1.5. To increase the writing density, it is necessary not only to reduce the L/S but also to form fine via. However, it would be difficult to form fine via with high A.R using the existing technology. Thus, dry etching technology is recommended as the method to fabricate fine PI via with vertical shape, and high A.R. As the result, a PI vertical via with A.R of 4 and a diameter of 3um is formed. The profile of PI vertical via can be demonstrate by dry etching.Secondary, we introduce the dry desmear technique. Currently, the technology of laser dill via in epoxy mold compound (EMC) is focused as micro via formation and cost reduction technology. The laser drill via is manufactured through the steps of laser drill, desmear, seed layer formation, and plating. These vias are formed in the substrate of EMC by femtosecond-laser. Then, the shape of these vias is the dimeter of 40um, the depth of 200um and A.R of 4. On other hands, the side wall of laser drill via is rough under the effect of SiO 2 filler in EMC. Before the formation of the seed layer, it is necessary desmear technique with smoothing of via side wall. Our experiment shows the estimated average roughness (Ra) by laser microscope is decreased from 0.57um to 0.23um. By the desmear treatment, the consecutive Cu/Ti layer can be form on side-wall of laser via.

As silicon scaling closer to physical limit, future reduction of the gate oxide does not lower down the cost per transistor. But the demand of higher functionality and lower cost of electronic devices do not slow down. Development of electronic devices metaphor to high-density package integration. What the electronic industries do is to break down a large die to a chiplet-based devices for improving yield and lower the total cost. Chiplet package become a key technology to continue Moore’s law. With the intensive researches, multiple chiplet packages are evolved such as multi chips on Si interposer using TSV (2.5D), die to die stack on each other (3D), Fan-Out Multi Chip Module (FOMCM), and EMIB (Embedded Multi-Die Interconnect Bridge). These packages are developed for the server, high performance computing, router, and switcher markets.But, the integration of high bandwidth memory devices and multiple ASIC dies together requires very high I/O counts and signal transmitting. Thus, a much higher RDL (Redistribution Layer) layer counts, finer bump pitch and smaller line- space (L/S) are designed. Each of these chiplets has its limitations. Large 2.5D package has its cost concerns on large Si interposer and mismatch of the Si interposer with substrate on reliability test. Whereas, large FO-MCM technology is limited by finer L/S and higher layers count of RDL. Presently, the package is heading the bottleneck at 1/1 μm L/S, 5 layers RDL and 2 reticle size chip module. As for EMIB technology, it is constrained by L/S that could only down to 5/5 μm.In this paper, we have successfully developed a scalable chiplet package technology, namely Fan-Out Embedded Bridge (FOEB). This chiplet package enables near monolithic short reach BEOL connections between dies. FOEB can have multiple RDL layers and Si bridge that has much finer L/S for interconnection. In addition to, multiple dies can be bridged together into one single chip module. In this paper, the demonstration of FOEB test vehicle, which integrate chips by 1 ASIC die and 4 memory dies (1+4) with 4 embedded bridge dies on mold-based interposer, 3 layers of RDL are presented. By comparing packages using FOMCM and 2.5D to fabricate. FOEB package has much lower warpage and 2 x lower stress value as compare to 2.5D. But similar to FOMCM. Owing to this reason, the FOEB chiplet package were tested 2x longer temperature cycle with condition-G without single failure as compared to 2.5D. The assembly yield of FOEB is comparable to FOMCM. And much higher than that of EMIB.Assembly of FOEB chiplet package adopts organic interposer. The wafer warpage changes from concave to convex shape after die attachment on the molded interposer. This limits some of the machines handling and induces wafer cracking. By properly select the right molding compound, and glass carrier CTE, we have successfully developed this FOEB chiplet and validated through reliability test. This chiplet allows us to scale the package to much higher I/O density, finer L/S, higher RDL layers, and number of dies that can be integrated into one single chip module.

We present our development of 2.5D integrated multi chip module silicon photonic transceivers for disaggregated applications, such as big data and machine learning algorithms. Disaggregation of data center resources to improve application efficiency and performance can be achieved through photonic switching networks. Our four-channel transceiver provides the electro-optic interface between electrical data generation and photonic switching to enable disaggregation within data centers.

This paper will present the design of a Current Sense Module (CSM) used to measure motor phase currents that is capable of surviving the harsh ambient environment of ocean worlds, such as Europa and Enceladus. The CSM module is fabricated by i3 Electronics using their Multi-Chip Module (MCM) technology with techniques developed by JPL to allow this module to survive temperatures down to −184°C. This module greatly improves the ability to measure phase and bridge current which can be problematic in extreme environments. In addition, by packaging these electronics at the die level, we achieve significant weight and size savings. This module is one of several modules that employ similar techniques that are integrated into a distributed or centralized motor controller. This paper will discuss the module's design along with a summary of our test results.

High bandwidth density silicon photonic interconnects offer the potential to address the massive increase in bandwidth demands for data center traffic and high performance computing. One of the major challenges in realizing silicon photonics transceivers is the integration and packing of photonic ICs (PIC) with electronic ICs (EIC). This paper presents our version one, 2.5D integrated multi-chip module (MCM) transceiver for 4 channel wavelength division multiplexing (WDM) operation, targeting 10 Gbps per channel. We identify five key areas critical to successful integration of MCM transceivers, which we have used in developing our version two MCM transceiver: integration architecture, equivalent circuit model development, PIC to EIC interface modelling, MCM I/O design, and design for assembly.

In the context of high performance computing (HPC), energy efficiency and computing density are key for targeting exascale architectures. Close integration of chiplets, active interposer and field programmable gate arrays (FPGA) paves the way for dense, efficient and modular compute nodes. In this paper, we detail the ExaNoDe multi-chip-module (MCM) combining the integration of a substrate, an active interposer, some chiplets and bare dice. The reported MCM demonstrates that the multi-level integration flow enables tight integration of hardware accelerators in a heterogeneous HPC compute node.

With the drastically development of the power electronics in the new energy industry, the compact Multi Chip Module packages for the high power density devices became the future tendency. The wick structures inside the flat plate heat pipe, as the key element, have to be fully investigated. The flat plate heat pipe research was toward visualization, micro scaling, multi heat sources, and so on. In here, a thin silicon based plate heat pipe (0.85 mm thick) was constructed with the integrated 250 μm height square micropillar array wick structure. The wick structure was fabricated directly in the silicon substrate (0.35 mm thick) by the dry etching process. Since only 100 μm silicon substrate between the heat resource and the cooling structures, the heat dissipation efficiency could be remarkable strengthen. The silicon microfabrication process is compatible with the standard IC process. This integrated cooling structure could be suitable for many high-power transistor packages. Facilitated with the glass cover transparency, not only the vapor-liquid interfaces could be distinguished, but also the water liquid phase temperature could be measured by the Raman spectral shifting. The Volume of Fluid two-phase flow transient model was established to evaluate the self-adaptability of the micropillar array wick structure. The structure showed a good response for the two heat resources’ power fluctuation. By the nature logarithm linear fitting of the heating power and the heating frequency, the maximum heat dissipation power (21 ± 2 W) of the heat pipe under the stable operation state could be estimated.

The thermal-flow-stress coupling model of multi-chip module with uniform heat generation under natural convection condition is established. Taking the chip aspect ratio and edge distance as design variables, a comprehensive performance indicator considering the maximum temperature, maximum thermal stress and maximum deformation is constructed to optimize the layout of chips with the constraints of the total occupied areas of printed circuit board and chips according to constructal theory. The results show that the comprehensive performance indicator decreases monotonically with the increase of the chip aspect ratio under the constraints of equal spacing, hence the chips should be designed as thin as possible according to the design requirements. Releasing the constraint of equal spacing, the comprehensive performance indicator increases monotonically with the increase of the edge distance when the chip aspect ratio is constant; the comprehensive performance indicator first decreases and then increases with the increase of chip aspect ratio when the edge distance is constant. The comprehensive performance indicator of the multi-chip module can be reduced by 0.65, the maximum temperature, the maximum thermal stress and the maximum deformation can be reduced by 6.28%, 9.44% and 9.66%, respectively. The methods and results herein could provide theoretical guidance for the thermal design of layout of multi-chip module.

Very small RF modules can be realized through heterogenous integration of GaAs MMIC (monolithic microwave integrated circuit) onto a low loss Si sub-mount, with high density routing lines realized by advanced patterning. In this paper we investigate how to integrate MMIC active devices on GaAs with the RF passives produced on an interposer, using Si wafer process technology. High resistive Silicon substrates are required to minimize RF losses. The interposer is thinned below 100 μm to reveal Cu TSVs from the back of the interposer, while the front side is covered entirely with a silicon capping wafer for shielding the device. We compare different wafer level packaging approaches for producing the low RF-loss interposers, and populating them using die-to-die (D2D) or die-to-wafer (D2W) bonding of the MMIC components, followed by wafer level encapsulation. Two D2W approaches are compared, in the first approach the D2W mounting and the encapsulation happens before the Si interposer is thinned for TSV reveal. To avoid damage during thinning of the wafer, thicker substrates with deeper TSV of 150 μm or more are required. In a second approach, the thinning of the interposer is done prior to the mounting. Initial electrical data showed that the approach yielded proper RF performance, but further yield optimization is required.

This paper discusses an improved design flow for hybrid Multi-Chip Modules comprising of MMICs and other components. A full 3D electromagnetic co-simulation flow is proposed. Application of such a flow is demonstrated with an MCM receiver module which has a bulk acoustic wave pre-filter, a Low Noise Amplifier with a digital bypass function, and a classical 6th order filter implemented with discrete components. Detailed simulation data is provided on each component of the system and the final MCM module, that demonstrates the use of the design flow. Finally, simulation results are compared to measured data from fabricated modules to prove the validity of our design approach

this paper details a multi-chip module (MCM) suitable for GaAs monolithic microwave integrated circuit common control high gain block MCM package design, 3D EM simulation of the package, package fabrication and end module level execution, which includes assembly and testing under various environmental test conditions as per the space standards. This MCM package designed using three internally separated cavities for individual cavity isolation, 4-RF Ports, 10mil thin film microstrip line and optimized wire bonding interconnects, and the same package is EM simulated using a CST microwave studio. This package modelled and fabricated using kovar material. This MCM package proposed to house a chain of four amplifiers with a common gain of 69dB, 2 SPDT switches with insertion loss of 3.6dB, a digital attenuator with initial attenuation of 2.5dB with TTL driver and 2 thermopads of 3dB individual attenuation. This package resonating frequency is 7.484GHz. The packaged MCM measurements are carried out over a frequency of 1.1GHz-1.4GHz and resulted with S21 of 60dB, S11&S22 of better than 15dB and P1dB out of 15dBm.

Package-level integration using multi-chip-modules (MCMs) is a promising approach for building large-scale systems. Compared to a large monolithic die, an MCM combines many smaller chiplets into a larger system, substantially reducing fabrication and design costs. Current MCMs typically only contain a handful of coarse-grained large chiplets due to the high area, performance, and energy overheads associated with inter-chiplet communication. This work investigates and quantifies the costs and benefits of using MCMs with fine-grained chiplets for deep learning inference, an application area with large compute and on-chip storage requirements. To evaluate the approach, we architected, implemented, fabricated, and tested Simba, a 36-chiplet prototype MCM system for deep-learning inference. Each chiplet achieves 4 TOPS peak performance, and the 36-chiplet MCM package achieves up to 128 TOPS and up to 6.1 TOPS/W. The MCM is configurable to support a flexible mapping of DNN layers to the distributed compute and storage units. To mitigate inter-chiplet communication overheads, we introduce three tiling optimizations that improve data locality. These optimizations achieve up to 16% speedup compared to the baseline layer mapping. Our evaluation shows that Simba can process 1988 images/s running ResNet-50 with batch size of one, delivering inference latency of 0.50 ms.

Many of the Integrated Circuit (IC) solutions generated by GCI involve multi-chip module (MCM) types of layouts within the package cavity to emulate the original monolithic device (single die in package cavity), ultimately providing a form, ’it, and functional drop-in replacement. These MCM architectures provide the greatest degree of flexibility when ensuring that the obsolete component’s electrical requirements are met1). This paper will address the design, development, and manufacture of inter-cavity silicon interposer substrates, by GCI and the University of Colorado at Colorado Springs Electrical and Computer Engineering department (UCCS-ECE), that provide signal routing of the passive and active devices within the cavity to meet the functional requirements of older obsolete devices. In this manner, a wide array of newer generation components can be configured within the package cavity on these silicon interposer substrates to architect obsolescence solutions while also meeting the high-temperature requirements of the Au-Sn (gold/tin) lid solder seal processes (∼340°C). Silicon substrates can also replace ceramic interposer versions2, while meeting or exceeding performance requirements, decreasing lead times, and manufactured with more competitive costs.

Multi-chip modules contain a large number of bare chips, which are sensitive to moisture in the packaging atmosphere. In order to ensure the long-term reliability of this kind of modules, it is necessary to seal the module package. Low-frequency connector is an indispensable part of multi-chip module, which is used to transmit internal and external electrical signals of modules. During the screening test, the phenomenon of unqualified hermeticity of some sealed modules appeared. Modules exhibit a leak rate greater than 1.0×10-3 Pa•m3/s during the tracer gas helium (He) fine leak test. Further inspection of the low-frequency connector body reveals that there are slender cracks in the connector glass body. The analysis shows that the reason of glass cracking is the thermal stress level of the module during welding heating exceeds the tensile strength of the glass, which leads to failure. Temperature difference exists in different positions of the connector during laser welding of cover plate, and cannot be eliminated by welding process optimization. After eliminating the internal defects of the glass body, the problem of glass body cracking did not occur in the process of multi-round step-by-step screening test, and the sealing test of module products was qualified after each test.

In this paper design of ceramic package and modelling of the package to meet the demands of low-cost and lower parasitic interconnect technology for wideband is presented. This proposed package suitability for high gain GaAs MMIC packaging in wideband frequency range with lower parasitic effects on MMIC performance is also presented. It is a 7 × 7 ceramic package with 48-pins. This proposed structure is embedded with GaAs MMICs working before the resonance frequency of the packaging. For proper grounding the package base is metal selected with sufficient number of filled via holes. The package base metal and the package pins are gold plated to suit for die bonding and also for wire bonding. This package pins are with 0.3 mm width and 0.2 mm spacing between the pins distributed four sides equally without leads. This no leads pin packaging structure gives very good benefits at microwave frequency due to lower inductance and higher isolation between pins. This package structure also shows with lower electromagnetic interference and electromagnetic coupling between pins and die. For MMICs functionality test a separate test structure is designed for RF lines and DC lines and fabricated on FR4 substrate with properly modelled transmission lines at input and output. This proposed package is EM simulated in CST microwave studio. The fabricated ceramic package contains 50 ohm lines fabricated with the thin film technology as well as IO RF connector working in wideband frequency range and their corresponding S11, S22, S21 and NF are recorded. This package resulted with typical S21 of 23 dB, S11 and S22 of better than 10 dB and typical NF of 2.5 dB which are in line with MMIC simulation data. Gain flatness over the frequency is less than ± 0.3 dB and a NF of less than ± 0.05.

This work presents a scalable deep neural network (DNN) accelerator consisting of 36 chips connected in a mesh network on a multi-chip-module (MCM) using ground-referenced signaling (GRS). While previous accelerators fabricated on a single monolithic die are limited to specific network sizes, the proposed architecture enables flexible scaling for efficient inference on a wide range of DNNs, from mobile to data center domains. The 16nm prototype achieves 1.29 TOPS/mm2, 0.11 pJ/op energy efficiency, 4.01 TOPS peak performance for a 1chip system, and 127.8 peak TOPS and 2615 images/s ResNet50 inference for a 36-chip system.

Silicon interposers are providing interesting alternatives to organic packages for the fabrication of complex system in package (SIP) modules in particular for RF application. Among the advantages of this technology are the capability to fabricate fine pitch redistribution layers and to embed inside the interposer some high quality passive elements very close to the active chips resulting in a highly integrated solution. To keep the technology at a reasonable cost these last add-on features need to be fabricated with no or minor additional process steps that the ones needed for the fabrication of the interposer itself. In this work we present the design and the fabrication of a high resistive silicon interposer conceived for hosting a functional RF SIP transceiver including a Front End Module (FEM), a Dual Band Dual Mode Power Amplifier working at 400 and 900 MHz and some embedded planar and 3D inductors. The interposer consists in symmetrical stack with one thick level of copper RDL on each side of the 200 µm thin HR silicon substrate and connected with through silicon via-last (TSV-last). The inductors are built with no additional metallization level. For the inductors development, a dedicated test vehicle was first designed to study different designs including planar spirals and 3D solenoids and torus. Simulation work was first carried out for dimensioning the structures to target inductance values in the range of 0.5 to 10 nH and high quality factor greater than 20. We present the process used for the fabrication, in particular the realization of the thick copper RDL layers on both sides of the interposer and the of the TSV-last module. Physical characterization are presented showing the integrity and the good control of the technology. DC and RF electrical measurements assess the performances achieved for the different inductor variants exhibiting low resistance, constant inductance up to 5 GHz and factor of quality higher than 30. The functional RF transceiver SIP module will be then presented. The architecture is an extremely compact multi chip module composed of four actives CMOS chips (VGA, VCO, modulator and the PA) stacked by flip chip with Cu/SnAg µbumps on the HR silicon interposer and surrounded by a hundred of passive SMD components. With this technology the footprint of the module is reduced by a factor of 2 in comparison with the same module made on a µPCB substrate. The signals and ground are fed through the thick copper RDL lines and the TSVs from LGA pads present on the backside of the interposer for assembly on a test board. Different design configurations are made on the same wafer that include some version using only SMD inductors and some using 2.5 and 3D inductors in order to compare the corresponding performances. Other test structures are also present like filters and individual inductors for DC and RF characterization. We will finally present the resulting performances obtained from this SIP integration.

Silicon interposer (Si-IP) technology has been used in accelerated processing units such as graphic processing units in high-performance computing because it can package a system-on-chip and high bandwidth memories. However, the conventional Si-IP has difficulty developing larger packages because of the mismatch in the coefficient thermal expansions (CTE) of the Si-IP and the organic substrate. Therefore, the Si-IP has limited capacity for improving computing performance by the application which requires more chips. We developed a multilayer glass substrate (Glass-ST) that features a stacked glass core and propose to apply this Glass-ST to a computer board. The proposed structure has no CTE mismatch and can use high density wiring. Thus, the Glass-ST enables the assembly of more large chips than is possible using the conventional Si-IP. In this study, we prepared a 100X100 mm Glass-ST with a 5/5 µm line/space and 20 µmΦ vias. We mounted nine 21X21 mm chips with 40 µm pitch micro bumps. The results revealed that conformal plated through glass vias and a fine wiring pattern had been fabricated in the Glass-ST, and that the nine chips and Glass-ST were connected by micro bumps. The maximum warpage of the nine chips was 23 µm between temperatures of 30°C and 250°C. This means that the Glass-ST can mount chips with micro bumps due to the very slight resulting warpage. In addition, we performed thermomechanical simulation to investigate the stress experienced by the micro bumps. The results show that the maximum stresses of micro bumps with pitches ranging between 10 µm and 55 um are very similar to that of 40 µm pitch micro bumps with which the real sample was packaged. We believe the improvements in the computing performance are significant by the Glass-ST technology compared to that of the conventional Si-IP technology.

Graphics Processing Unit (GPU) performance has relied heavily on our ability to scale of number of transistors on chip, in order to satisfy the ever-increasing demands for more computation. However, transistor scaling has become extremely challenging, limiting the number of transistors that can be crammed onto a single die. Manufacturing large, fast and energy-efficient monolithic GPUs, while growing the number of stream processing units on-chip, is no longer a viable solution to scale performance. GPU vendors are aiming to exploit multi-GPU solutions, interconnecting multiple GPUs in the single node with a high bandwidth network (such as NVLink), or exploiting Multi-Chip-Module (MCM) packaging, where multiple GPU modules are integrated in a single package. The inter-GPU bandwidth is an expensive and critical resource for designing multi-GPU systems. The design of the inter-GPU network can impact performance significantly. To address this challenge, in this paper we explore the potential of hardware-based memory compression algorithms to save bandwidth and improve energy efficiency in multi-GPU systems. Specifically, we propose an adaptive inter-GPU data compression scheme to efficiently improve both performance and energy efficiency. Our evaluation shows that the proposed optimization on multi-GPU architectures can reduce the inter-GPU traffic up to 62%, improve system performance by up to 33%, and save energy spent powering the communication fabric by 45%, on average.

Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as}Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. High-density Packaging technologies such as 3D, 2.5D packaging scheme basing on TSV (through-Si via) technology and PWB (printed wiring board) packaging as high-density interposer are among key technologies to satisfy the requirements from the both smart semiconductor devices for AI (artificial intelligence), and smart functional devices for “Edge-computing”. Meanwhile MEMS/Sensors are required as multi-functionalities of stand-alone smart devices for wearable devices including smart phone, an important part of smart-systems. Thus, the demand of high density FO-SiP (fan-out system in packaging) is growing. In order to accomplish high-density packaging as homogeneous and heterogeneous integration, miniaturization of wiring in organic package is needful to MCM (multi chip module) system fabrication on the PWB. To obtain vias in a build-up film, the laser drilling process is widely used but there are three major restricting difficulties. The first is that it is difficult to make fine vias and line / space because of laser wave length limitation. The second is that wet desmear process to remove smear for each generation’s build-up films is also will be issue by swelling and silica-residue problem. And finally, such kind of technologies cannot intentionally control of surface roughness for build-up film. In this study, a fine via and line and space patterns processing below $10 \mu \mathrm{m}$ with low surface-roughness in a low-CTE (coefficient of thermal expansion) Build-up film was achieved by using a plasma dry process. That technology applications are dry desmear and dry etching for fan-out wiring fabrication.

In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard multi-chip module (MCM) package with a System-on-Chip (SoC), thermals, and fiber attach will be reviewed.