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SiC is a promising substrate for Si-on-insulator (SOI) wafers for efficient thermal management owing to its high thermal conductivity and large bandgap. However, fabricating a Si device layer on a SiC substrate with a high and uniform thermal-boundary conductance (TBC) at the wafer scale is challenging. In this study, a 4-inch Si-on-SiC wafer was fabricated using a room-temperature surface-activated bonding method, and the TBC was measured using the time-domain thermoreflectance (TDTR) method. The obtained TBC was 109 MW/m2K in the as-bonded sample, improving to 293 MW/m2K after annealing at 750 oC, representing a 78% increase compared to previously reported values for a Si-SiC interface formed by bonding methods. Such enhancement is attributed to the absence of an oxide layer at the interface. Furthermore, we assessed the actual spatial distribution of the TBC in the SOI system by combining the TDTR mapping with a mathematical model to remove the influence of random errors in the experiment. The spatial distributions before and after annealing were 7% and 17%, respectively. Such variation highlights the need to consider the TBC distribution when designing thermal management systems.

Thermal boundary resistance (TBR) in semiconductor-on-diamond structure bottlenecks efficient heat dissipation in electronic devices. In this study, to reduce the TBR between GaN and diamond, surface-activated bonding with a hybrid SiOx-Ar ion source was applied to achieve an ultrathin interfacial layer. The simultaneous surface activation and slow deposition of the SiOx binder layer enabled precise control over layer thickness (2.5-5.3 nm) and formation of an amorphous heterogeneous nanostructure comprising a SiOx region between two inter-diffusion regions. Crucially, the 2.5-nm-thick interfacial layer achieved a TBR of 8.3 m2-W/GW, a record low for direct-bonded GaN/diamond interface. A remarkable feature is that the TBR is extremely sensitive to the interfacial thickness; rapidly increasing to 34 m2-K/GW on doubling the thickness to 5.3 nm. Theoretical analysis revealed the origin of this increase: a diamond/SiOx interdiffusion layer extend the vibrational frequency, far-exceeding that of crystalline diamond, which increases the lattice vibrational mismatch and suppresses phonon transmission.

To achieve high device performance and high reliability for the gallium nitride (GaN)-based high electron mobility transistors (HEMTs), efficient heat dissipation is important but remains challenging. Enormous efforts have been made to transfer a GaN device layer onto a diamond substrate with a high thermal conductivity by bonding. In this work, two GaN-diamond bonded composites are prepared via modified surface activated bonding (SAB) at room temperature with silicon interlayers of different thicknesses (15 nm and 22 nm). Before and after post-annealing process at 800 oC, thermal boundary conductance (TBC) across the bonded interface including the interlayer and the stress of GaN layer are investigated by time-domain thermoreflectance and Raman spectroscopy, respectively. After bonding, the 15 nm Si interlayer achieved a higher TBC. The post-annealing significantly increased the TBC of both interfaces, while the TBC of 22 nm silicon interlayer increased greater and became higher than that of 15 nm. Detailed investigation of the microstructure and composition of the interfaces were carried out to understand the difference in interfacial thermal conduction. The obtained stress was no more than 230 MPa for both before and after the annealing, and this high thermal stability of the bonded composites indicates that the room temperature bonding can realize a GaN-on-diamond template suitable for further epitaxial growth or device process. This work brings a novel strategy of SAB followed by high-temperature annealing to fabricate a GaN-on-diamond device with a high TBC.

Thermal resistances from interfaces impede heat dissipation in micro/nanoscale electronics, especially for high-power electronics. Despite the growing importance of understanding interfacial thermal transport, advanced thermal characterization techniques which can visualize thermal conductance across buried interfaces, especially for nonmetal-nonmetal interfaces, are still under development. This work reports a dual-modulation-frequency TDTR mapping technique to visualize the thermal conduction across buried semiconductor interfaces for beta-Ga2O3-SiC samples. Both the beta-Ga2O3 thermal conductivity and the buried beta-Ga2O3-SiC thermal boundary conductance (TBC) are visualized for an area of 200 um x 200 um. Areas with low TBC values ( smaller than 20 MW/m2-K) are successfully identified on the TBC map, which correspond to weakly bonded interfaces caused by high-temperature annealing. The steady-state temperature rise (detector voltage), usually ignored in TDTR measurements, is found to be able to probe TBC variations of the buried interfaces without the limit of thermal penetration depth. This technique can be applied to detect defects/voids in deeply buried heterogeneous interfaces non-destructively, and also opens a door for the visualization of thermal conductance in nanoscale nonhomogeneous structures.

The ultra-wide bandgap, high breakdown electric field, and large-area affordable substrates make \b{eta}-Ga2O3 promising for applications of next-generation power electronics while its thermal conductivity is at least one order of magnitude lower than other wide/ultrawide bandgap semiconductors. To avoid the degradation of device performance and reliability induced by the localized Joule-heating, aggressive thermal management strategies are essential, especially for high-power high-frequency applications. This work reports a scalable thermal management strategy to heterogeneously integrate wafer-scale monocrystalline \b{eta}-Ga2O3 thin films on high thermal conductivity SiC substrates by ion-cutting technique. The thermal boundary conductance (TBC) of the \b{eta}-Ga2O3-SiC interfaces and thermal conductivity of the \b{eta}-Ga2O3 thin films were measured by Time-domain Thermoreflectance (TDTR) to evaluate the effects of interlayer thickness and thermal annealing. Materials characterizations were performed to understand the mechanisms of thermal transport in these structures. The results show that the \b{eta}-Ga2O3-SiC TBC values increase with decreasing interlayer thickness and the \b{eta}-Ga2O3 thermal conductivity increases more than twice after annealing at 800 oC due to the removal of implantation-induced strain in the films. A Callaway model is built to understand the measured thermal conductivity. Small spot-to-spot variations of both TBC and Ga2O3 thermal conductivity confirm the uniformity and high-quality of the bonding and exfoliation. Our work paves the way for thermal management of power electronics and \b{eta}-Ga2O3 related semiconductor devices.

The wide bandgap, high-breakdown electric field, and high carrier mobility makes GaN an ideal material for high-power and high-frequency electronics applications such as wireless communication and radar systems. However, the performance and reliability of GaN-based HEMTs are limited by the high channel temperature induced by Joule-heating in the device channel. High thermal conductivity substrates integrated with GaN can improve the extraction of heat from GaN based HEMTs and lower the device operating temperature. However, heterogeneous integration of GaN with diamond substrates is not trivial and presents technical challenges to maximize the heat dissipation potential brought by the diamond substrate. In this work, two modified room temperature surface activated bonding techniques are used to bond GaN and single crystal diamond with different interlayer thicknesses. TDTR is used to measure the thermal properties from room temperature to 480 K. A relatively large TBC of the GaN-diamond interfaces with a 4nm interlayer was observed and material characterization was performed to link the structure of the interface to the TBC. Device modeling shows that the measured GaN-diamond TBC values obtained from bonding can enable high power GaN devices by taking the full advantage of the high thermal conductivity of single crystal diamond and achieve excellent cooling effect. Furthermore, the room-temperature bonding process in this work do not induce stress problem due to different coefficient of thermal expansion in other high temperature integration processes in previous studies. Our work sheds light on the potential for room-temperature heterogeneous integration of semiconductors with diamond for applications of electronics cooling especially for GaN-on-diamond devices.

GaN-based HEMTs have the potential to be widely used in high-power and high-frequency electronics while their maximum output powers are limited by high channel temperature induced by near-junction Joule-heating, which degrades device performance and reliability. Increasing the TBC between GaN and SiC will aid in the heat dissipation of GaN-on-SiC power devices, taking advantage of the high thermal conductivity of the SiC substrate. However, a good understanding of the TBC of this technically important interface is still lacking due to the complicated nature of interfacial heat transport. In this work, a lattice-mismatch-insensitive surface activated bonding method is used to bond GaN directly to SiC and thus eliminating the AlN layer altogether. This allows for the direct integration of high quality GaN layers with SiC to create a high thermal boundary conductance interface. TDTR is used to measure the thermal properties of the GaN thermal conductivity and GaN-SiC TBC. The measured GaN thermal conductivity is larger than that of GaN grown by MBE on SiC, showing the impact of reducing the dislocations in the GaN near the interface. High GaN-SiC TBC is observed for the bonded GaN-SiC interfaces, especially for the annealed interface whose TBC (230 MW/m2-K) is close to the highest values ever reported. To understand the structure-thermal property relation, STEM and EELS are used to characterize the interface structure. The results show that, for the as-bonded sample, there exists an amorphous layer near the interface for the as bonded samples. This amorphous layer is crystallized upon annealing, leading to the high TBC found in our work. Our work paves the way for thermal transport across bonded interfaces, which will impact real-world applications of semiconductor integration and packaging.

This work reports the strain effect on the electrical properties of highly doped n-type single crystalline cubic silicon carbide (3C-SiC) transferred onto a 6-inch glass substrate employing an anodic bonding technique. The experimental data shows high gauge factors of -8.6 in longitudinal direction and 10.5 in transverse direction along the [100] orientation. The piezoresistive effect in the highly doped 3C-SiC film also exhibits an excellent linearity and consistent reproducibility after several bending cycles. The experimental result was in good agreement with the theoretical analysis based on the phenomenon of electron transfer between many valleys in the conduction band of n-type 3C-SiC. Our finding for the large gauge factor in n-type 3C- SiC coupled with the elimination of the current leak to the insulated substrate could pave the way for the development of single crystal SiC-on-glass based MEMS applications.