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Photonic integrated circuits are paving the way for novel on-chip functionalities with diverse applications in communication, computing, and beyond. The integration of on-chip light sources, especially single-mode lasers, is crucial for advancing those photonic chips to their full potential. Recently, novel concepts involving topological designs introduced a variety of options for tuning device properties, such as the desired single-mode emission. Here, we introduce a novel cavity design that allows amplification of the topological interface mode by deterministic placement of gain material within a topological lattice. The proposed design is experimentally implemented by a selective epitaxy process to achieve closely spaced Si and InGaAs nanorods embedded within the same layer. This results in the first demonstration of a single-mode laser in the telecom band using the concept of amplified topological modes without introducing artificial losses., Competing Interests: The authors declare no competing financial interest., (© 2024 The Authors. Published by American Chemical Society.)

There is a general trend of downscaling laser cavities, but with high integration and energy densities of nanocavity lasers, significant thermal issues affect their operation. The complexity of geometrical parameters and the various materials involved hinder the extraction of clear design guidelines and operation strategies. Here, we present a systematic thermal analysis of InP-on-Si micro- and nanocavity lasers based on steady-state and transient thermal simulations and experimental analysis. In particular, we investigate the use of metal cavities for improving the thermal properties of InP-on-Si micro- and nanocavity lasers. Heating of lasers is studied by using Raman thermometry and the results agree well with simulation results, both revealing a temperature reduction of hundreds of kelvins for the metal-clad cavity. Transient simulations are carried out to improve our understanding of the dynamic temperature variation under pulsed and continuous wave pumping conditions. The results show that the presence of a metal cladding not only increases the overall efficiency in heat dissipation but also causes a much faster temperature response. Together with optical experimental results under pulsed pumping, we conclude that a pulse width of 10 ns and a repetition rate of 100 kHz is the optimal pumping condition for a 2 μm wide square cavity., Competing Interests: The authors declare no competing financial interest., (© 2022 The Authors. Published by American Chemical Society.)

An important building block for on-chip photonic applications is a scaled emitter. Whispering gallery mode cavities based on III-Vs on Si allow for small device footprints and lasing with low thresholds. However, multimodal emission and wavelength stability over a wider range of temperature can be challenging. Here, we explore the use of Au nanorod antennae on InP whispering gallery mode lasers on Si for single-mode emission. We show that by proper choice of the antenna size and positioning, we can suppress the side modes of a cavity and achieve single-mode emission over a wide excitation range. We establish emission trends by varying the size of the antenna and show that the far-field radiation pattern differs significantly for devices with and without antenna. Furthermore, the antenna-induced single-mode emission is dominant from room temperature (300 K) down to 200 K, whereas the cavity without an antenna is multimodal and its dominant emission wavelength is highly temperature-dependent., Competing Interests: The authors declare no competing financial interest., (© 2022 The Authors. Published by American Chemical Society.)

The seamless integration of III-V nanostructures on silicon is a long-standing goal and an important step towards integrated optical links. In the present work, we demonstrate scaled and waveguide coupled III-V photodiodes monolithically integrated on Si, implemented as InP/In 0.5 Ga 0.5 As/InP p-i-n heterostructures. The waveguide coupled devices show a dark current down to 0.048 A/cm 2 at -1 V and a responsivity up to 0.2 A/W at -2 V. Using grating couplers centered around 1320 nm, we demonstrate high-speed detection with a cutoff frequency f 3dB exceeding 70 GHz and data reception at 50 GBd with OOK and 4PAM. When operated in forward bias as a light emitting diode, the devices emit light centered at 1550 nm. Furthermore, we also investigate the self-heating of the devices using scanning thermal microscopy and find a temperature increase of only ~15 K during the device operation as emitter, in accordance with thermal simulation results., (© 2022. The Author(s).)

Metastable wurtzite crystal phases of conventional semiconductors comprise enormous potential for high-performance electro-optical devices, owed to their extended tunable direct band gap range. However, synthesizing these materials in good quality and beyond nanowire size constraints has remained elusive. In this work, the epitaxy of wurtzite InP microdisks and related geometries on insulator for advanced optical applications is explored. This is achieved by an elaborate combination of selective area growth of fins and a zipper-induced epitaxial lateral overgrowth, which enables co-integration of diversely shaped crystals at precise position. The grown material possesses high phase purity and excellent optical quality characterized by STEM and µ-PL. Optically pumped lasing at room temperature is achieved in microdisks with a lasing threshold of 365 µJ cm -2 . Our platform could provide novel geometries for photonic applications.

In this work we present an in-memory computing platform based on coupled VO 2 oscillators fabricated in a crossbar configuration on silicon. Compared to existing platforms, the crossbar configuration promises significant improvements in terms of area density and oscillation frequency. Further, the crossbar devices exhibit low variability and extended reliability, hence, enabling experiments on 4-coupled oscillator. We demonstrate the neuromorphic computing capabilities using the phase relation of the oscillators. As an application, we propose to replace digital filtering operation in a convolutional neural network with oscillating circuits. The concept is tested with a VGG13 architecture on the MNIST dataset, achieving performances of 95% in the recognition task., Competing Interests: EC, JC, KM, BG, and SK were employed by IBM. The remaining authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest., (Copyright © 2021 Corti, Cornejo Jimenez, Niang, Robertson, Moselund, Gotsmann, Ionescu and Karg.)

A key component for optical on-chip communication is an efficient light source. However, to enable low energy per bit communication and local integration with Si CMOS, devices need to be further scaled down. In this work, we fabricate micro- and nanolasers of different shapes in InP by direct wafer bonding on Si. Metal-clad cavities have been proposed as means to scale dimensions beyond the diffraction limit of light by exploiting hybrid photonic-plasmonic modes. Here, we explore the size scalability of whispering-gallery mode light sources by cladding the sidewalls of the device with Au. We demonstrate room temperature lasing upon optical excitation for Au-clad devices with InP diameters down to 300 nm, while the purely photonic counterparts show lasing only down to 500 nm. Numerical thermal simulations support the experimental findings and confirm an improved heat-sinking capability of the Au-clad devices, suggesting a reduction in device temperature of 450 - 500 K for the metal-clad InP nanodisk laser, compared to the one without Au. This would provide substantial performance benefits even in the absence of a plasmonic mode. These results give an insight into the benefits of metal-clad designs to downscale integrated lasers on Si.

Photonic crystal (PhC) cavities are promising candidates for Si photonics integrated circuits due to their ultrahigh quality ( Q )-factors and small mode volumes. Here, we demonstrate a novel concept of a one-dimensional hybrid III-V/Si PhC cavity which exploits a combination of standard silicon-on-insulator technology and active III-V materials. Using template-assisted selective epitaxy, the central part of a Si PhC lattice is locally replaced with III-V gain material. The III-V material is placed to overlap with the maximum of the cavity mode field profile, while keeping the major part of the PhC in Si. The selective epitaxy process enables growth parallel to the substrate, and hence in-plane integration with Si, and in-situ in-plane homo- and heterojunctions. The fabricated hybrid III-V/Si PhCs show emission over the entire telecommunication band from 1.2 to 1.6 μm at room temperature validating the device concept and its potential towards fully integrated light sources on silicon.

Direct epitaxial growth of III-Vs on silicon for optical emitters and detectors is an elusive goal. Nanowires enable the local integration of high-quality III-V material, but advanced devices are hampered by their high-aspect ratio vertical geometry. Here, we demonstrate the in-plane monolithic integration of an InGaAs nanostructure p-i-n photodetector on Si. Using free space coupling, photodetectors demonstrate a spectral response from 1200-1700 nm. The 60 nm thin devices, with footprints as low as ~0.06 μm 2 , provide an ultra-low capacitance which is key for high-speed operation. We demonstrate high-speed optical data reception with a nanostructure photodetector at 32 Gb s -1 , enabled by a 3 dB bandwidth exceeding ~25 GHz. When operated as light emitting diode, the p-i-n devices emit around 1600 nm, paving the way for future fully integrated optical links.

Metastable crystal phases of abundant semiconductors such as III-Vs, Si, or Ge comprise enormous potential to address current limitations in green light-emitting electrical diodes (LEDs) and group IV photonics. At the same time, these nonconventional polytypes benefit from the chemical similarity to their stable counterparts, which enables the reuse of established processing technology. One of the main challenges is the very limited availability and the small crystal sizes that have been obtained so far. In this work, we explore the limitations of wurtzite (WZ) film epitaxy on the example of InP. We develop a novel method to switch and maintain a metastable phase during a metal-organic vapor phase epitaxy process based on epitaxial lateral overgrowth and compare it with standard selective area epitaxy techniques. We achieve unprecedented large WZ layer dimensions exceeding 100 μm 2 and prove their phase purity both by optical as well as structural characterization. On the basis of our observations, we further develop a nucleation-based model and argue on a fundamental size limitation of WZ film growth. Our findings may pave the way toward crystal phase engineered LEDs for highly efficient lighting and display applications.

InGaAs is a potential candidate for Si replacement in upcoming advanced technological nodes because of its excellent electron transport properties and relatively low interface defect density in dielectric gate stacks. Therefore, integrating InGaAs devices with the established Si platforms is highly important. Using template-assisted selective epitaxy (TASE), InGaAs nanowires can be monolithically integrated with high crystal quality, although the mechanisms of group III incorporation in this ternary material have not been thoroughly investigated. Here we present a detailed study of the compositional variations of InGaAs nanostructures epitaxially grown on Si(111) and Silicon-on-insulator substrates by TASE. We present a combination of XRD data and detailed EELS maps and find that the final Ga/In chemical composition depends strongly on both growth parameters and the growth facet type, leading to complex compositional sub-structures throughout the crystals. We can further conclude that the composition is governed by the facet-dependent chemical reaction rates at low temperature and low V/III ratio, while at higher temperature and V/III ratio, the incorporation is transport limited. In this case we see indications that the transport is a competition between Knudsen flow and surface diffusion.

Recent research on nanowires (NWs) demonstrated the ability of III-V semiconductors to adopt a different crystallographic phase when they are grown as nanostructures, giving rise to a novel class of materials with unique properties. Controlling the crystal structure however remains difficult and the geometrical constraints of NWs cause integration challenges for advanced devices. Here, we report for the first time on the phase-controlled growth of micron-sized planar InP films by selecting confined growth planes during template-assisted selective epitaxy. We demonstrate this by varying the orientation of predefined templates, which results in concurrent formation of zinc-blende (ZB) and wurtzite (WZ) material exhibiting phase purities of 100% and 97%, respectively. Optical characterization revealed a 70 meV higher band gap and a 2.5× lower lifetime for WZ InP in comparison to its natural ZB phase. Further, a model for the transition of the crystal structure is presented based on the observed growth facets and the bonding configuration of InP surfaces.

Today, silicon is the most used material in photovoltaics, with the maximum conversion efficiency getting very close to the Shockley-Queisser limit for single-junction devices. Integrating silicon with higher band-gap ternary III-V absorbers is the path to increase the conversion efficiency. Here, we report on the first monolithic integration of Ga x In (1- x) P vertical nanowires, and the associated p-n junctions, on silicon by the Au-free template-assisted selective epitaxy (TASE) method. We demonstrate that TASE allows for a high chemical homogeneity of ternary alloys through the nanowires. We then show the influence of doping on the chemical composition and crystal phase, the latter previously attributed to the role of the contact angle in the liquid phase in the vapor-liquid-solid technique. Finally, the emission of the p-n junction is investigated, revealing a shift in the energy of the intraband levels due to the incorporation of dopants. These results clarify some open questions on the effects of doping on ternary III-V nanowire growth and provide the path toward their integration on the silicon platform in order to apply them in next-generation photovoltaic and optoelectronic devices.

The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III-V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.

Additional functionalities on semiconductor microchips are progressively important in order to keep up with the ever-increasing demand for more powerful computational systems. Monolithic III-V integration on Si promises to merge mature Si CMOS processing technology with III-V semiconductors possessing superior material properties, e. g., in terms of carrier mobility or band structure (direct band gap). In particular, Si photonics would strongly benefit from an integration scheme for active III-V optoelectronic devices in order to enable low-cost and power-efficient electronic-photonic integrated circuits. We report on room-temperature lasing from AlGaAs/GaAs microdisk cavities monolithically integrated on Si(001) using a selective epitaxial growth technique called template-assisted selective epitaxy. The grown gain material possesses high optical quality without indication of threading dislocations, antiphase boundaries, or twin defects. The devices exhibit single-mode lasing at T < 250 K and lasing thresholds between 2 and 18 pJ/pulse depending on the cavity size (1-3 μm in diameter).

GaSb nanostructures integrated on Si substrates are of high interest for p-type transistors and mid-IR photodetectors. Here, we investigate the metalorganic chemical vapor deposition and properties of GaSb nanostructures monolithically integrated onto silicon-on-insulator wafers using template-assisted selective epitaxy. A high degree of morphological control allows for GaSb nanostructures with critical dimensions down to 20 nm. Detailed investigation of growth parameters reveals that the GaSb growth rate is governed by the desorption processes of an Sb surface layer and, in turn, is insensitive to changes in material transport efficiency. The GaSb crystal structure is typically zinc-blende with a low density of rotational twin defects, and even occasional twin-free structures are observed. Hall/van der Pauw measurements are conducted on 20 nm-thick GaSb nanostructures, revealing high hole mobility of 760 cm 2 /(V s), which matches literature values for high-quality bulk GaSb crystals. Finally, we demonstrate a process that enables cointegration of GaSb and InAs nanostructures in close vicinity on Si, a preferred material combination ideally suited for high-performance complementary III-V metal-oxide-semiconductor technology.

We report complementary metal-oxide-semiconductor (CMOS)-compatible integration of compound semiconductors on Si substrates. InAs and GaAs nanowires are selectively grown in vertical SiO2 nanotube templates fabricated on Si substrates of varying crystallographic orientations, including nanocrystalline Si. The nanowires investigated are epitaxially grown, single-crystalline, free from threading dislocations, and with an orientation and dimension directly given by the shape of the template. GaAs nanowires exhibit stable photoluminescence at room temperature, with a higher measured intensity when still surrounded by the template. Si-InAs heterojunction nanowire tunnel diodes were fabricated on Si(100) and are electrically characterized. The results indicate a high uniformity and scalability in the fabrication process.

We report on in situ doping of InAs nanowires grown by metal-organic vapor-phase epitaxy without any catalyst particles. The effects of various dopant precursors (Si(2)H(6), H(2)S, DETe, CBr(4)) on the nanowire morphology and the axial and radial growth rates are investigated to select dopants that enable control of the conductivity in a broad range and that concomitantly lead to favorable nanowire growth. In addition, the resistivity of individual wires was measured for different gas-phase concentrations of the dopants selected, and the doping density and mobility were extracted. We find that by using Si(2)H(6) axially and radially uniform doping densities up to 7 × 10(19) cm(-3) can be obtained without affecting the morphology or growth rates. For sulfur-doped InAs nanowires, we find that the distribution coefficient depends on the growth conditions, making S doping more difficult to control than Si doping. Moreover, above a critical sulfur gas-phase concentration, compensation takes place, limiting the maximum doping level to 2 × 10(19) cm(-3). Finally, we extract the specific contact resistivity as a function of doping concentration for Ti and Ni contacts.

In this work we investigate doping by solid-state diffusion from a doped oxide layer, obtained by plasma-enhanced chemical vapor deposition (PECVD), as a means for selectively doping silicon nanowires (NWs). We demonstrate both n-type (phosphorous) and p-type (boron) doping up to concentrations of 10(20) cm(-3), and find that this doping mechanism is more efficient for NWs as opposed to planar substrates. We observe no diameter dependence in the range of 25 to 80 nm, which signifies that the NWs are uniformly doped. The drive-in temperature (800-950 °C) can be used to adjust the actual doping concentration in the range 2 × 10(18) to 10(20) cm(-3). Furthermore, we have fabricated NMOS and PMOS devices to show the versatility of this approach and the possibility of achieving segmented doping of NWs. The devices show high I(on)/I(off) ratios of around 10(7) and, especially for the PMOS, good saturation behavior and low hysteresis.