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1. Hibikino-Musashi@Home 2024 Team Description Paper

2. Hibikino-Musashi@Home 2023 Team Description Paper

4. Learning Reservoir Dynamics with Temporal Self-Modulation

5. Hibikino-Musashi@Home 2022 Team Description Paper

6. Hibikino-Musashi@Home 2018 Team Description Paper

7. A Neural Network Model of the Entorhinal Cortex and Hippocampus for Event-order Memory Processing

8. Effects of VLSI Circuit Constraints on Temporal-Coding Multilayer Spiking Neural Networks

9. Hibikino-Musashi@Home 2019 Team Description Paper

10. Hibikino-Musashi@Home 2020 Team Description Paper

11. A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design

12. An Efficient Hardware-Oriented Dropout Algorithm

13. An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach

14. A Time-domain Analog Weighted-sum Calculation Model for Extremely Low Power VLSI Implementation of Multi-layer Neural Networks

15. Hibikino-Musashi@Home 2017 Team Description Paper

16. Depth-Based Visual Servoing Using Low-Accurate Arm

17. A Hardware-Oriented Dropout Algorithm for Efficient FPGA Implementation

20. Restricted Boltzmann Machines Without Random Number Generators for Efficient Digital Hardware Implementation

21. FPGA Implementation of Autoencoders Having Shared Synapse Architecture

22. A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines

23. Time-Domain Weighted-Sum Calculation for Ultimately Low Power VLSI Neural Networks

24. Morphological Associative Memory Employing a Split Store Method

26. Learning Reservoir Dynamics with Temporal Self-Modulation

27. Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing

28. Obstacles Extraction Using a Moving Camera

29. A Motion Detection Model Inspired by Hippocampal Function and Its FPGA Implementation

30. A VLSI Spiking Neural Network with Symmetric STDP and Associative Memory Operation

36. Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach

38. A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations

39. A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition

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