50 results on '"Moreira, Matheus T."'
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2. Testing the blade resilient asynchronous template
3. A processor for IoT applications: An assessment of design space and trade-offs
4. A new local clock generator for globally asynchronous locally synchronous MPSoCs
5. SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping
6. Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison
7. A TensorFlow and System Simulator Integration Approach to Estimate Hardware Metrics of Convolution Accelerators
8. Leveraging QDI Robustness to Simplify the Design of IoT Circuits
9. Test Oriented Design and Layout Generation of an Asynchronous Controller for the Blade Template
10. A Frontend using Traditional EDA Tools for the Pulsar QDI Design Flow
11. Testing the blade resilient asynchronous template
12. Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools
13. Libra: An Automatic Design Methodology for CMOS Complex Gates
14. Testable Error Detection Logic Design Applied to an Asynchronous Timing Resilient Template
15. A DfT Insertion Methodology to Scannable Q-Flop Elements
16. NCL Synthesis With Conventional EDA Tools: Technology Mapping and Optimization
17. An LSSD Compliant Scan Cell for Flip-Flops
18. Hardening C-elements against metastability
19. Estimation methods for static noise margins in CMOS subthreshold logic circuits
20. Sleep convention logic isochronic fork
21. Transistor placement strategies for non-series-parallel cells
22. A comparison of asynchronous QDI templates using static logic
23. ASCEnD-FreePDK45: An open source standard cell library for asynchronous design
24. A Fine-Grain, Uniform, Energy-Efficient Delay Element for 2-Phase Bundled-Data Circuits
25. Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding
26. A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI
27. Testable MUTEX Design
28. Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications
29. The HF-RISC processor: Performance assessment
30. Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool
31. SDDS-NCL Design
32. A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies
33. Design and Analysis of Testable Mutual Exclusion Elements
34. TDTB error detecting latches: Timing violation sensitivity analysis and optimization
35. A digitally controlled oscillator for fine-grained local clock generators in MPSoCs
36. Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits
37. Advances on the state of the art in QDI design
38. A design flow for physical synthesis of digital cells with ASTRAN
39. Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design
40. Automatic layout synthesis with ASTRAN applied to asynchronous cells
41. BaBaNoC: An asynchronous network-on-chip described in Balsa
42. Charge sharing aware NCL gates design
43. SDDS-NCL design: Analysis of supply voltage scaling.
44. NCL+: Return-to-one Null Convention Logic
45. Return-to-One DIMS logic on 4-phase m-of-n asynchronous circuits
46. Electrical characterization of a C-Element with LiChEn
47. Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes
48. Hermes-AA: A 65nm asynchronous NoC router with adaptive routing
49. Design of NCL gates with the ASCEnD flow.
50. A Fine-Grained, Uniform, Energy-Efficient Delay Element for FD-SOI Technologies.
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