Search

Your search keyword '"Moraes, Fernando G."' showing total 145 results
Start Over Author "Moraes, Fernando G."
145 results on '"Moraes, Fernando G."'

1. Assessment of Radiation-Induced Soft Error on Unmanned Surface Vehicles

Author

Fleck, Marcos A., primary, Pereira, Elisa G., additional, Gava, Jonas F., additional, Silva, Henrique B., additional, Moraes, Fernando G., additional, Calazans, Ney L. V., additional, Meneguzzi, Felipe, additional, Bastos, Rodrigo P., additional, Reis, Ricardo A. L., additional, Ost, Luciano, additional, and Garibotti, Rafael, additional

Published
2024
Full Text
View/download PDF

3. Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture

Author

Amory, Alexandre M., Lubaszewski, Marcelo, Moraes, Fernando G., and Moreno, Edson I.

Subjects
Computer Science - Hardware Architecture
Abstract

The increasing complexity and the short life cycles of embedded systems are pushing the current system-on-chip designs towards a rapid increasing on the number of programmable processing units, while decreasing the gate count for custom logic. Considering this trend, this work proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the test access mechanism. Experimental results are based on ITC'02 benchmarks and on two open core processors compliant with MIPS and SPARC instruction set. The results show that the cooperative use of both the on-chip network and the embedded processors can increase the test parallelism and reduce the test time without additional cost in area and pins., Comment: Submitted on behalf of EDAA (http://www.edaa.com/)

Published
2007

11. Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry

Author

Palma, José C. S., Indrusiak, Leandro Soares, Moraes, Fernando G., Ortiz, Alberto Garcia, Glesner, Manfred, Reis, Ricardo A. L., Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Dough, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Vounckx, Johan, editor, Azemard, Nadine, editor, and Maurine, Philippe, editor

Published
2006
Full Text
View/download PDF

15. A Comprehensive Evaluation of Convolutional Hardware Accelerators

Author

Juracy, Leonardo R., Amory, Alexandre M., and Moraes, Fernando G.

Abstract

Industry increasingly adopts Convolutional Neural Networks (CNNs) in applications ranging from IoT to autonomous driving. Convolutional hardware accelerators for the inference phase are an option for CPUs and GPUs due to the smaller power consumption and improved performance. The literature presents hardware accelerators using different 2D architectures, including weight stationary (WS), input stationary (IS), and output stationary (OS). The main differentiation between these architectures is how accelerators access data (input feature map and weight tensors) and compute the output (output feature map tensor). There is a gap in the literature related to a comprehensive evaluation of such architectures. This brief aims to answer the following question: “which accelerator type should I use according to my design constraints and memory type (SRAM or DRAM)”. Experiments show that when using SRAM as external memory to the accelerator, WS presents the smallest area and energy consumption, while IS presents the best performance. On the other hand, the IS accelerator stands out when using DRAM because it has a reduced performance sensitivity to memory latency.

Published
2023
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results