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The acoustic and vibrational properties of Mn-doped (Na1/2Bi1/2)TiO3-xBaTiO3 with x = 0.05 were investigated by using Brillouin and Raman spectroscopies and compared with those of undoped crystals. The mode frequency and the half width of the Brillouin doublet of the longitudinal acoustic mode showed more drastic changes near the dielectric maximum temperature compared to the broad and diffused changes of the undoped crystals, which indicates that Mn-doping induces polar domains larger than the typical polar nanoregions formed in undoped counterpart. The acoustic anomalies were most pronounced along the direction suggesting that the polarization fluctuations are anisotropic and largest along this direction. Temperature dependence of Raman spectra showed that there are two characteristics temperatures where mode splitting occurs due to local symmetry changes. The high-temperature anomaly was associated with the changes in the acoustic properties, while the low-temperature mode splitting was related to the dielectric anomaly near depolarization temperature.

In this work, the temperature/impedance integrated sensor is manufactured using a semiconductor process for the simultaneous monitoring of the temperature and impedance variations. Temperature Coefficient of Resistance (TCR) value of the manufactured Platinum temperature sensor on the slide glass is evaluated as 2003.65 ppm/℃, giving the temperature inaccuracy less than ±0.05 ℃. HeLa cancer cells are grown on the temperature/impedance integrated biosensors and the reactions between HeLa cancer cell and cisplatin are monitored as a function of time. The impedance rapidly increased at the early stage and gradually decreased with time. However, there are no noticeable variations in temperature. The results are compared with those by the biological cell viability test on the conventional culture plates.

In this study, to improve the performance of a temperature sensor, a thin oxide film was deposited on the silicon substrate in addition to controlling the substrate thickness of the sensor. We investigated the effect of the oxide film on the sensitivity and reaction time of the sensor by preventing the heat conduction to the lower silicon substrate. The deposition characteristics of the oxide films were observed at 900°C, and either 1 Torr or 10 torr in the furnace using the dry oxidation method. The reaction time of the temperature sensor was calculated using the heat diffusion rule Fick’s second law. The sensitivity was determined by measuring the temperature variation according to the applied power; the heat response time was about 5 times faster and the sensitivity was improved about 2 times compared with the bulk silicon substrate.

We investigate the thermoelectric properties of Ni/Ge-multilayer-laminated silicon thermoelectric devices based on the number of Ni/Ge layers from single layer to 50 layers. For the Ni/Ge-multilayer lamination, Ni and Ge thin layers are alternately deposited on a bulk silicon substrate using RF sputtering at room temperature. The Seebeck coefficient improves and the thermal conductivity decreases compared with the bulk silicon thermoelectric device as the number of Ni/Ge layers increases. A seven Ni/Ge-multilayer-laminated thermoelectric device indicates a Seebeck coefficient of – 260 μV/K and a thermal conductivity of 56 W/m∙K at 510 K without electrical conductivity deterioration; subsequently, a thermoelectric power factor of 5.6 mW/m∙K2 and zT of 0.05 are achieved at 510 K. The improvement in the Seebeck coefficient in the multilayer devices is attributed to the electron filtering effect due to the Schottky barriers at the Ni/Ge interfaces. It is speculated that the acoustic phonon impedance mismatch at the Si(Al)/Ni interface reduces/saturates the thermal conductivity. The thermoelectric results indicate the potential of using a Ni/Ge-multilayer structure for silicon-based thermoelectric devices.

Reduced graphene oxide (rGO) has wide application as a nanofiller in the fabrication of electroconductive biocomposites due to its exceptional properties. However, the hydrophobicity and chemical stability of rGO limit its ability to be incorporated into precursor polymers for physical mixing during biocomposite fabrication. Moreover, until now, no suitable rGO-combining biomaterials that are stable, soluble, biocompatible, and 3D printable have been developed. In this study, we fabricated digital light processing (DLP) printable bioink (SGOB1), through covalent reduction of graphene oxide (GO) by glycidyl methacrylated silk fibroin (SB). Compositional analyses showed that SGOB1 contains approximately 8.42% GO in its reduced state. Our results also showed that the rGO content of SGOB1 became more thermally stable and highly soluble. SGOB1 hydrogels demonstrated superior mechanical, electroconductive, and neurogenic properties than (SB). Furthermore, the photocurable bioink supported Neuro2a cell proliferation and viability. Therefore, SGOB1 could be a suitable biocomposite for neural tissue engineering.

The acoustic behaviors of oxygen-reduced barium titanate (BaTiO3-δ) single crystals with δ∼0.04 were investigated as a function of temperature by using Brillouin spectroscopy. The longitudinal acoustic mode of the moderately-reduced BaTiO3 (BTO) showed two pronounced anomalies at approximately 112 °C and −11 °C, which correspond to the cubic-tetragonal and tetragonal-orthorhombic phase transition temperature, respectively. These temperatures were lower by more than 10 °C compared to those of the pure BaTiO3 suggesting that the disorder introduced by oxygen vacancies lowers the phase transition temperatures. The paraelectric phase of the reduced BaTiO3 were characterized by substantial softening of the longitudinal acoustic mode and the growth of central peaks centered at zero frequency. These anomalies were observed in a certain temperature range above the Curie temperature, indicating that pretransitional precursor polar clusters exist in the cubic phase and that their dynamics are responsible for the acoustic anomalies caused by electrostrictive coupling between the strain and the polarization. The relaxation time of the precursor polar clusters derived from the central peak exhibited a critical slowing-down behavior showing that their dynamics becomes more sluggish as temperature approaches the Curie point.

The synthesis of hybrid nanoparticles with multiple functions from the economical and scalable perspective is an important issue in nanoparticle engineering. Herein, we report a representative example of multi-functional nanosystems simultaneously possessing fluorescence and magnetism as well as the excellent structural properties of nanosilica. Highly fluorescent multiple Fe3O4 nanoparticles core-silica shell nanoparticles (FL multi-Fe3O4@SiO2 NPs) are successfully synthesized and fully characterized. The multiple Fe3O4 nanoparticles can be uniformly and collectively encapsulated within a silica matrix using a reverse microemulsion (RM) method. Fluorescent dyes are successfully functionalized through the sequential hydrolysis and condensation of tetraethylorthosilicate (TEOS) and 3-(aminopropyl) triethoxysilane (APTES). Both organic (fluorescein) and inorganic (Rubpy) dyes can be used to generate the FL multi-Fe3O4@SiO2 NPs. These synthetic paradigms for multi-functional nanoparticles can significantly facilitate the fabrications of unique nanomaterials widely applied in a variety of areas.

To study the electric and the thermoelectric properties of silicon thin films (SiTFs), we fabricated devices having SiTFs by using conventional complementary metal-oxide-semiconductor (CMOS)-compatible processes for mass production and extendibility. The conductivities and the Seebeck coefficients of SiTFs for dose concentrations of 5 × 1014 cm -2, 1 × 1015 cm -2 and 5 × 1015 cm -2 and for temperatures in the range of 310 to 430 K were measured by using homemade setup. The measured power factors of the SiTFs showed a slight increasing tendency with increasing measurement temperature and were maximum at a dose concentration of 1 × 1015 cm -2 for both n- and p-type films at 330 K.

Hole mobility characteristics were investigated with surface roughness and silicon-on-insulator (SOI) thickness variations to investigate the influence of surface roughness to mobility. The root mean square roughness varied between 0.16, 0.85 and 10.6 nm in 220, 100 and 40 nm thick SOI samples. Hole mobility was measured and analyzed as a function of effective field and temperature with the variations of surface roughness. The hole mobility, determined by transconductance, greatly decreased with the increase of effective field due to the increased surface roughness scattering in 40 nm thick SOI samples. On the other hand, phonon scattering was a dominant mechanism with the increase of temperature, irrespective of surface roughness and SOI thickness. The induced surface roughness of the devices increases the phonon scattering, thereby reducing the electron and hole mobility. The hole mobility decreases with the roughening of the samples, with the increase of temperature due to increased phonon scattering. Therefore, for enhanced mobility, surface scattering and phonon scattering should be controlled even in atomic scale roughened samples.

Microscale-pyramidal-structure-arrayed patterned silicon membranes are manufactured using semiconductor processes and potassium hydroxide (KOH) etching techniques for filter applications. The silicon nitride on silicon on the insulator wafer functions as a masking layer, and the roughness of the silicon (100) plane strongly depends on the etching temperature and KOH concentration. To fabricate the membrane filter, a series of dry and wet etching using 45 wt% KOH solutions at the constant temperature of 70 °C was performed. With the dry and wet etching, micro-pyramidal arrays with 300 μm top and 16-20 μm bottom opening sizes were created. The morphological structures were analyzed using scanning electron microscopy. The manufactured membranes were tested as optical directional filters and particle filters.

We fabricated silicide/silicon hetero-junction structured thermoelectric device by CMOS process for the reduction of thermal conductivity with the scatterings of phonons at silicide/silicon interfaces. Electrical conductivities, Seebeck coefficients, power factors, and temperature differences are evaluated using the steady state analysis method. Platinum silicide/silicon multilayered structure showed an enhanced Seebeck coefficient and power factor characteristics, which was considered for p-leg element. Also, erbium silicide/silicon structure showed an enhanced Seebeck coefficient, which was considered for an n-leg element. Silicide/silicon multilayered structure is promising for thermoelectric applications by reducing thermal conductivity with an enhanced Seebeck coefficient. However, because of the high thermal conductivity of the silicon packing during thermal gradient is not a problem any temperature difference. Therefore, requires more testing and analysis in order to overcome this problem. Thermoelectric generators are devices that based on the Seebeck effect, convert temperature differences into electrical energy. Although thermoelectric phenomena have been used for heating and cooling applications quite extensively, it is only in recent years that interest has increased in energy generation.

For the evaluation of thermoelectric properties in silicon nanowires (SiNWs), thermoelectric test structures are manufactured, including 50-nm-wide n- and p-type SiNWs, micro-heater and temperature sensors using a conventional lithography method on 8 in. silicon wafer. For the optimization of thermoelectric properties in SiNWs, we have evaluated Seebeck coefficients and power factors of n- and p-type SiNWs by varying the nanowire length 10, 40 μm and temperature (from 310 to 450 K). The results show that the maximum Seebeck coefficients and power factors are $$146.37 \,{\upmu} \hbox {V/K}, 1.15\,\times \,10^{3}\, \hbox {W}\,\hbox {m}^{-1}\,\hbox {K}^{-2}, 113.83\; {\upmu} \hbox {V/K}, 0.67\,\times \,10^{3}\, \hbox {W}\,\hbox {m}^{-1}\,\hbox {K}^{-2}$$ and $$-113.25\; {\upmu} \hbox {V/K}, 0.59\,\times \,10^{3}\,\hbox {W}\,\hbox {m}^{-1}\,\hbox {K}^{-2}$$ for $$10, 40\; {\upmu} \hbox {m}$$ long p-type and $$40\; {\upmu}\hbox {m}$$ long n-type SiNWs, respectively. The contribution of phonon-drag effect to thermoelectric power is discussed in the highly doped SiNWs.

The electric and the thermoelectric properties of 50-nm n- and p-type silicon nanowires (SiNWs) obtained by doping with boron di-fluoride and phosphorus, respectively, were investigated by varying the doping concentration from 1.0 × 1020 to 2.5 × 1021 cm -3. The SiNWs were manufactured using conventional semiconductor processing techniques. The values of the optimized maximum power factor values were 1.59 and 2.43 mW·m -1K-2 for the n- and the p-type SiNWs at a doping concentration of 4.0 × 1020 cm-3. For doping concentrations higher than over 4.0 × 1020 cm-3, the electrical resistivity was larger and the Seebeck coefficient was sharply lower due to imperfections in the crystal structure. For lower doping concentrations below 4.0 × 1020 cm-3, the increased resistivity had a dominant impact on the power factor.

Electric and thermoelectric properties of silicide/silicon multi-layer structured devices were investigated with the variation of silicide/silicon heterojunction numbers from 3 to 12 layers. For the fabrication of silicide/silicon multi-layered structure, platinum and silicon layers are repeatedly sputtered on the (100) silicon bulk substrate and rapid thermal annealing is carried out for the silicidation. The manufactured devices show ohmic current–voltage (I–V) characteristics. The Seebeck coefficient of bulk Si is evaluated as 195.8 ± 15.3 μV/K at 300 K, whereas the 12 layered silicide/silicon multi-layer structured device is evaluated as 201.8 ± 9.1 μV/K. As the temperature increases to 400 K, the Seebeck coefficient increases to 237.2 ± 4.7 μV/K and 277.0 ± 1.1 μV/K for bulk and 12 layered devices, respectively. The increase of Seebeck coefficient in multi-layered structure is mainly attributed to the electron filtering effect due to the Schottky barrier at Pt-silicide/silicon interface. At 400 K, the thermal conductivity is reduced by about half of magnitude compared to bulk in multi-layered device which shows the efficient suppression of phonon propagation by using Pt-silicide/silicon hetero-junctions.

A silicon nanowire one-dimensional thermoelectric device is presented as a solution to enhance thermoelectric performance. A top-down process is adopted for the definition of 50 nm silicon nanowires (SiNWs) and the fabrication of the nano-structured thermoelectric devices on silicon on insulator (SOl) wafer. To measure the Seebeck coefficients of 50 nm width n- and p-type SiNWs, a thermoelectric test structure, containing SiNWs, micro-heaters and temperature sensors is fabricated. Doping concentration is 1.0 x 10(20) cm(-3) for both for n- and p-type SiNWs. To determine the temperature gradient, a temperature coefficient of resistance (TCR) analysis is done and the extracted TCR value is 1750-1800 PPM x K(-1). The measured Seebeck coefficients are -127.583 microV x K(-1) and 141.758 microV x K(-1) for n- and p-type SiNWs, respectively, at room temperature. Consequently, power factor values are 1.46 mW x m(-1) x K(-2) and 1.66 mW x m(-1) x K(-2) for n- and p-type SiNWs, respectively. Our results indicate that SiNWs based thermoelectric devices have a great potential for applications in future energy conversion systems.

25-nm-gate-length Schottky barrier metal–oxide-semiconductor field-effect transistors (SB-MOSFETs) with platinum silicide (PtSi) was fabricated using silicidation through oxide technique coupled with two-step annealing process. The manufactured SB-MOSFET showed a large on/off current ratio (>10 7 ) with excellent short-channel characteristics such as low values of subthreshold swing (83 mV/dec.) and drain induced barrier lowering (23 mV). A controlled Pt flux caused by the densification of SiO x during low temperature 1st step annealing leads to the homogeneous growth of PtSi films at high temperature 2nd step annealing, which was responsible for the superior device performance of nanometer scale SB-MOSFET.

Current-voltage (I-V) characteristics for various silicon wires of different length-to-width ratios were numerically calculated by solving the Poisson equation and the current continuity equations for electrons and holes self-consistently. We found that, as the silicon wire became thinner or the length-to-width aspect ratio becomes higher, the I-V data deviated more from the Ohmic relation: the current density at a certain bias voltage was larger. In the case of a 500-nm-long silicon wire with n-type doping of 1 × 1016 cm3, for example, the current density of a silicon wire at a bias voltage of 2 volts increased by nearly threefold as the length-to-width ratio of wires was increased from 1 to 25. This behavior is attributed to an enhanced field at the source due to the strong stray field configuration near the contacts at both ends of a wire and to the large carrier build-up in the middle. Our result suggests that a classical treatment of nanowire transport with a proper account of the nonuniform field distribution along the wire may partly explain the conductivity enhancement phenomenon often observed in various nanowires and nanotubes.

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of 550 μA/μm and –376 μA/μm, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is 0.05 μS and 1.2 μS for the SB-SET and SB-SHT, respectively. In the SBSET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

In this paper, the general characteristics and the scalability of Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are introduced and reviewed. The most important factors, i.e., interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are estimated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are estimated as 1.5 × 1013 traps/cm2, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by N2 annealing. Based on the diode characteristics, various sizes of erbium-silicided/platinum-silicided n/p-type SB-MOSFETs are manufactured and analyzed. The manufactured SB-MOSFETs show enhanced drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are comparable with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

The electron transport characteristics of bilayer graphene were investigated in terms of changes in the temperature from 2 to 300 K. The purpose of this study was a confirming the reported values5 of the carrier density and the mobility for using a ballistic quantum transport experiment. The mechanical exfoliation method was adopted to get the best quality of bilayer graphene and the number of layers of graphene was identified by the Raman spectra. Our bilayer graphene was a slightly n-doped state with the neutrality point at Vg =−7.5 V. Hall measurements provided an accurate means to evaluate the carrier density and the mobility. In magnetic field of −9 to 9 T, clear Shubnikov-de Haas oscillations were measured in bilayer graphene, indicating the presence of a clear electron quantum transport mechanism. The mobility and the carrier density of the bilayer graphene at 2 K were measured to be 9,400 cm2/V · s and 3×1011 cm−2, respectively.

10 and 6 nm erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) were manufactured. The manufactured 10 nm n-type SB-MOSFET showed a large on/off current ratio (> 106) with low leakage current less than 10− 5 μA/μm due to the existence of the robust Schottky barrier between source and channel region. The saturation currents were 550 and 320 μA/μm when drain and gate voltages were 2 V and 3 V, for the 10 and 6 nm erbium-silicided n-type SB-MOSFETs, respectively. The manufactured SB-MOSFETs exhibited superior short channel characteristics due to the existence of Schottky barrier between source and channel region.

In this paper, n/p-type nickel-silicided Schottky diodes were fabricated by incorporating antimony atoms near the nickel silicide/Si junction interface and the electrical characteristics were studied through measurements and simulations. The effective Schottky barrier height (SBH) for electron, extracted from the thermionic emission model, drastically decreased from 0.68 to less than 0.1 eV while that for hole slightly increased from 0.43 to 0.53 eV. In order to identify the current conduction mechanisms, the experimental current-temperature-voltage characteristics for the n-type diode were fitted based on various models for transport of charge carrier in Schottky diodes. As the result, the large change in effective SBH for electron is ascribed to trap-assisted tunneling rather than barrier height inhomogeneity.

The silicon nanocluster floating gate memory device based on the Schottky barrier metal-oxide-semiconductor field effect transistor (SB-MOSFET) was proposed. The silicon nanoclusters were formed via the digital gas-feeding low pressure chemical vapor deposition. Erbium silicide process was used to form the Schottky junctions at the source/drain. In addition to the SB-MOSFET operation, the program/erase times of the nonvolatile memory device were determined to be 10 ms and 100 ms under the + 18 and − 18 V gate bias conditions, respectively. Maximum memory window was 5.5 V and the charge retention characteristics were maintained with a memory window of 0.5 V at 10 6 s.

This paper experimentally investigates the unique behavior of transconductance (gm) in the Schottky-barrier metal-oxide-semiconductor field-effect transistors (SB-MOSFETs) with various silicide materials. When the Schottky-barrier height (SBH) or a scaling parameter is not properly optimized, a peculiar shape of gm is observed. Thus, gm can be used as a novel metric that exhibits the transition of the carrier injection mechanisms from a thermionic emission (TE) to thermally assisted tunneling (TU) in the SB-MOSFETs. When the local maximum point of gm is observed, it can be expected that an incomplete transition occurs between TE and TU in SB-MOSFETs. When a dopant-segregation (DS) technique is implemented in the SB-MOSFETs, however, the carrier injection efficiency from the source to the channel is significantly improved, although the SBH is not minimized. As a consequence, the peculiar shape of the gm disappears, i.e., a complete transition from TE to TU can be enabled by the DS technique.

Enhanced Dopant-segregated Schottky-barrier (DSSB) FinFETs combined with a fully silicided (FUSI) gate were fabricated via single-step Ni-silicidation. Both workfunction control of the gate and a lowered effective SB-height in the source/drain junctions are simultaneously achieved by the dopant-segregated silicidation process. Moreover, the leakage current was significantly reduced with the aid of deep source/drain implantation. Therefore, it can be expected that a DSSB device with a FUSI gate have several advantages as both a logic and nonvolatile memory device. First, for a logic device, it can provide low parasitic resistance and a tunable threshold voltage. Second, for a nonvolatile memory device, the increased workfunction due to the FUSI gate can enhance the erasing characteristics by suppressing the back tunneling of electrons from the gate side as well as the programming characteristics.

A p-channel dopant-segregated-Schottky-barrier (DSSB) device based on a SOI FinFET structure is proposed for silicon-oxide-nitride-oxide-silicon type Flash memory, providing the feasibility of bit-by-bit operation through the aid of a symmetric program/erase operation. This concept is based on utilizing injected holes due to enhanced Fowler-Nordheim tunneling probability triggered by the sharpened energy band bending at the DSSB source/drain junctions as a programming method and the tunneled electrons from a silicon channel as an erasing method. As a result, a threshold voltage window of nearly 4 V and good data retention are achieved within a P/E time of 3.2 μs.