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A 10 Gb/s PAM-4 transmitter (TX) with a modulo-based equalization technique is presented. The proposed feed-forward Tomlinson-Harashima precoding (FF-THP) scheme takes advantage of both Tomlinson-Harashima precoding (THP) and feed-forward equalization (FFE). The vertical eye margin (VEM) is enhanced by removing the precursor inter-symbol interference (ISI) with pretaps while incorporating the modulo operation. The VEMs of equalization methods are derived based on z-domain response (ZDR). The effectiveness of the FF-THP is examined by quantitative analysis and numerical simulation. Especially for a one-pole channel with a precursor, optimized tap coefficients of an FFE and an FF-THP are derived as closed-form concerning the precursor and the first postcursor. Calculations of decision threshold voltage and estimated bathtub curve based on Gaussian noise are featured by using the histogram of an eye diagram. The advantages of the FF-THP over a conventional FFE are measured by a fabricated chip. The proposed TX compensates for a 21 dB channel loss with a level mismatch ratio of 99.1% and with a figure of merit (energy efficiency per sum of channel ISI) of 4.05 pJ/b/ISI. Moreover, the FF-THP achieves 38% and 87.5% improvement on VEM and horizontal eye margin, respectively, compared with an FFE. It is fabricated in 28 nm CMOS technology, occupying an active area of 0.075 mm2.

This brief presents a 2.5 – 28 Gb/s multi-standard transmitter with a two-step time-multiplexing driver. The proposed two-step time-multiplexing driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing the number of stacks compared with a 4-to-1 time-multiplexing driver. In addition, the proposed transmitter can enhance the bandwidth by avoiding the use of a 1-unit-interval (1-UI) pulse which is one of the main design challenges in high-speed transmitters. It also provides a controllable output swing and a 3-tap feed-forward equalization (FFE) by turning-on and –off the driver slices. The output impedance is calibrated by a background feedback loop, resulting in a good signal integrity. The prototype chip fabricated in a 65-nm CMOS technology consists of a four-channel transmitter and a global all-digital phase-locked loop (ADPLL). One channel of the transmitter with the ADPLL occupies an active area of 0.23 mm2 and consume 213 mW at 28 Gb/s.

This paper presents a forwarded-clock receiver (RX) that consists of a weight-adjusting sign-sign Mueller-Muller clock and data recovery (CDR) and an adaptive decision-feedback equalizer (DFE) with a single shared error sampler. Only two samples per bit are utilized for both CDR and adaptive DFE, which minimizes clocking power consumption. In addition, a maximum-eye tracking algorithm is proposed to enhance the vertical eye margin without any extra high-speed analog circuitry. The RX fabricated in a 28nm CMOS technology achieves BER less than 10−12 with a 20dB-loss channel. It occupies an active area of 0.108 mm2, and consumes 56.65 mW at 28 Gb/s.

This paper presents an ac-dc LED driver that consists of two-parallel inverted buck converters. To buffer the twice-line-frequency energy, one inverted buck converter (also known as a floating buck converter) conveys energy to a storage capacitor, simultaneously performing the power factor correction. The other inverted buck converter regulates the LED current to maintain a constant brightness in the LEDs for reducing the light flicker to low-risk levels. The proposed architecture reduces the voltage stress and the size of the storage capacitor, enabling the use of a film capacitor instead of an electrolytic capacitor. Considering the power factor and the flicker standards, a design procedure to achieve a high power factor, while minimizing the storage capacitance and the LED current ripple, is presented. A prototype of the proposed LED driver has been implemented with an on-chip controller IC fabricated in a 0.35-μm CMOS process and its functionality and performance have been verified experimentally. It demonstrates a power factor of 0.94 and a peak power efficiency of 85.4% with an LED current ripple of 6.5%, while delivering 15 W to the LEDs.

In order to suppress the malfunction caused by the shift of the threshold voltage (VTH) of oxide thin film transistors (TFTs) to a negative value, double-gate TFTs are used in the shift register of the gate driving system to control VTH by adjusting the top gate bias. The proposed circuit detects the current consumption of the shift register and adjusts VTH so that the current consumption of the shift register is regulated within the desired value. The system includes a compensation algorithm, which can search for an optimized top gate bias in various circumstances such as process fluctuations and ambient temperature change. The proposed system provides a stable operation compared with a conventional structure especially at high temperature. Experimental results show that, in the conventional system without compensation, the output voltage of the shift register deteriorates at $80\, {}^{\circ} {\rm C}$ and above, and the power consumption increases from 1.15 to 2.14 mW after 21600 s of continuous operation at $60\, {}^{\circ} {\rm C}$ . On the other hand, the proposed system provides a stable gate output up to $100\, {}^{\circ} {\rm C}$ and keeps the power consumption below 1.10 mW by adjusting the top gate bias responding to environment changes.

This paper presents a 36 GS/s data path that is based on CMOS logic. The proposed non-clocked delay generator achieves high bandwidth as well as produces near-1-UI delay by employing digitally controlled cross-coupled latches. In addition, the proposed 4-to-2 serializer with pre-charging/discharging transistors not only reduces a data-dependent jitter but also mitigates non-ideal effects such as charge injection and clock feedthrough by removing the floating nodes of the multiplexer. As a result, the 8-to-2 serializer has extremely low rms jitter of 146 fs and peak-to-peak jitter of 980 fs at the output node. Moreover, thanks to the simple architecture of the 8-to-2 serializer and the delay generator, power consumption is remarkably reduced. The data path that dissipates 21.87 mW from 1.2-V supply is implemented and laid-out in 28-nm CMOS technology.

The shift register of display panel employing double-gate oxide thin-film transistors (TFTs) to compensate the severe degradation of the threshold voltage (V TH) is proposed. In double-gate TFTs, V TH is controlled by adjusting top-gate bias, so that V TH degradation can be stabilised by top-gate bias control. However, an optimum top-gate voltage varies from product to product due to process–voltage–temperature variation. To overcome this variation, a feedback system is designed and fabricated in a 0.18 μm BCDMOS process. The system consists of the shift register current sensing and the searching algorithm for finding optimal top-gate bias of double-gate TFTs. It is verified that proposed system successfully stabilised the operation of the shift register up to 80°C.

A semi-actively controlled impact systemis studied, which adjusts an impulse exerted by the external impact. Also, an active impact control system using a servo valve is introduced, and these performances are compared. The systems should respond to the extremely short impulse and control the impulse within a highly fast interval. Both the semi-active and the active control systems utilize an external orifice in the form of a proportional valve or a servo valve, which adjusts its opening area to control the pressure and piston displacement. These devices overcome the temperature and viscosity variations due to continuant operations, and keep the desired pressure difference and the displacement at a desirable level. In this work, two prototypic impact systems controlled by semi-active and full active operations are designed and manufactured. Through computer simulations and experiments, the possibility of controlling the pressure and displacement of an impact control system is verified.