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This paper presents a wideband, low insertion loss, high attenuation range digital step attenuator (DSA) implemented using SiGe HBTs. In a switched-type topology, the off-state capacitances (COFF) in both reference and attenuation states cause different poles and zeros, which trigger amplitude and phase errors and limit the operating bandwidth. To achieve wide bandwidth, methods to relocate poles and zeros to the highest possible frequencies in both states are investigated. In the reference state, minimizing the size of the shunt switching transistors extends the bandwidth. In the attenuation state, switching in a capacitor at the base of an anti-parallel (AP) SiGe HBT pair series switch reduces the effective COFF, enhancing the bandwidth. The proposed techniques facilitate the realization of a 16-dB attenuator cell to support wide bandwidth and offer lower insertion loss than conventional cascaded 8-dB cell designs. Fabricated in 130-nm SiGe BiCMOS technology, the proposed DSA with an attenuation range of 31.5 dB in 0.5 dB steps operates from DC to 67 GHz and achieves an insertion loss lower than 7.8 dB. The RMS amplitude error is less than 0.4 dB above 1 GHz, while the RMS phase variation is less than 13.1∘.

This letter presents new wideband single-pole double-throw (SPDT) RF switches utilizing SiGe heterojunction bipolar transistors (HBTs) for both series and shunt switches. SiGe HBT, when used as a series switch, exhibits small parasitic components compared to bulk CMOS, which improves insertion loss at high frequency and supports wider bandwidth. For a series switch, three configurations are proposed: using the collector as an input (CI), using the emitter as an input (EI), and using a combination of the two in an antiparallel (AP) fashion. While all three configurations exhibit similar performance, the SPDT switch with the EI SiGe HBT exhibits the best insertion loss and isolation achieving dc-to-above 110-GHz bandwidth, 2.5 dB of insertion loss, and 27.3 dB of isolation at 60 GHz. The SPDT switch with AP SiGe HBT pair exhibits the highest linearity, with 15.6 dBm of input 1-dB compression point (IP 1 dB) at 10 GHz. With 0.61 mW of power dissipation, these new SPDT switches using SiGe HBTs exhibit similar performance to silicon-on-insulator (SOI) CMOS while obtaining higher power capability among conventional series-shunt SPDT designs.

This letter presents the application of the f T -doubler technique, for the first time, to improve the unitygain frequency (f T ) of inverse-mode (TM) silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). An f T -doubler structure, which used three identical SiGe HBTs with the same emitter area of 0.07 (width) × 0.9 (length) μm 2 , is implemented in a commercial 0.13-μm SiGe-BiCMOS technology platform. A peak f T of 77 GHz is extrapolated for the TM f T doubler, whereas a peak f T of a single TM SiGe HBT is found to be 53 GHz, exhibiting an increase of about 46% in f T from the f T -doubler technique. The maximum oscillation frequency of the TM f T doubler using Mason's unilateral gain is about 158 GHz. Tn addition, small-signal model parameters of the TM f T doubler are presented, which show the TM f T -doubler structures can be treated as a single transistor element for highfrequency circuit design.

This paper presents a 2–24 GHz SiGe HBT cascode, non-uniform distributed power amplifier (NDPA). Optimum impedances at each SiGe HBT cascode are obtained by simultaneous characteristic impedance scaling of the collector transmission lines (TLs) and SiGe HBT emitter area tapering. To further boost output power (Pout), a compact, wideband two-section lumped-element output impedance transformer is proposed, which lowers a load impedance from 50 to 25 Ω. Each λ/4 transformer is realized by four cascaded C-L-C π-networks integrated into a single symmetric inductor, for its compact size and high passive efficiency. The proposed SiGe HBT cascode NDPA achieves a saturated Pout of 21.3 dBm at 8 GHz and peak power added efficiency (PAE) of 21.7% at 4 GHz, with its 3 dB bandwidth and PAE higher than 12.2% from 2 to 24 GHz.

This paper presents a new, wideband digital step attenuator (DSA) implemented using SiGe HBTs. The vertical profile of the SiGe HBT presents small parasitic shunt capacitance and, thus, the loss from the switches in a switched-type attenuator is significantly reduced. For a 6-bit DSA covering a maximum attenuation of 31.5 dB with 0.5 dB steps, reduced T-type cells with reverse-saturated SiGe HBTs are used for low attenuation cells and switched pi-type cells with novel anti-parallel (AP) SiGe HBT pair series switches are used for high attenuation cells. In addition to the symmetry of the AP SiGe HBT pair, reduced T-type and switched pi-type cells are placed alternately to distribute parasitic components and to achieve better overall symmetry. As a result, state-of-the-art performance is achieved over a wide bandwidth, from DC-to-60 GHz, with an insertion loss of 7.5 dB at 50 GHz, 31.5 dB of attenuation range and less than 2.8 mW of power consumption.

We provide “best practices” for single-event transient (SET) mitigation using electrostatic discharge (ESD) protection techniques. We investigate the correlation between SET suppression and RF performance when ESD protection circuits for SET mitigation are combined with various RF switches. The three different single-pole single-throw (SPST) switch configurations (conventional design, floating body, and floating body/n-well) were implemented to provide insight on how to best apply dc ESD protection techniques for also achieving robust SET mitigation. Based on two-photon absorption laser experiments and RF measurements, a conventional SPST switch configuration shows relatively poor RF performance but is effective for SET mitigation due to the SET discharge current path provided by ESD protection circuit. On the other hand, the combination of the SPST switch and the ESD circuit, which exhibits the best RF performance among the three configurations, is relatively vulnerable to SETs. Based on these results, strategies and methodologies for ESD protection techniques to effectively mitigate SET are proposed.

The cryogenic performance of radiation-hardened radio-frequency (RF) low-noise amplifiers (LNAs) is presented. The LNA, which was originally proposed for the mitigation of single-event transients (SETs) in a radiation environment, uses inverse-mode silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in its core cascode stages. In this prototype, the upper common-base SiGe HBT is configured in inverse mode for balanced RF performance and reduced SET sensitivity. In order to better exploit the inverse-mode LNAs in a variety of extreme-environment applications, the RF performance of the LNA was characterized using liquid nitrogen to evaluate cryogenic operation down to 78 K. While the SiGe LNA exhibits acceptable RF performance for all temperature conditions, there is a noticeable gain drop observed at 78 K compared to the conventional forward-mode design. This is attributed to the limited high-frequency performance of an inverse-mode SiGe HBT. As a guideline, compensation techniques, including layout modifications and profile optimization, are discussed for the mitigation of the observed gain degradation.

A 6-bit active digital step attenuator (DSA), which simultaneously achieves wide bandwidth, flat gain characteristics, and bidirectional operation, is proposed for wideband phased-array antennas. In addition, it supports bandwidth tuning and equalization function to reduce complexity and physical size of systems. The proposed circuit utilizes an active double-pole double-throw switch, which provides positive gain with four-way switching and bidirectional operation. In addition, the simplified switched T-type topologies are applied to improve the insertion loss and save on chip area for low-attenuation states (0.5, 1, and 2 dB). Implemented in a 130-nm SiGe-BiCMOS technology platform, the proposed active DSA provides the advantages of seamless integration with digital control blocks and wide operational bandwidth due to its low parasitic capacitance. The active DSA exhibits flat in-band gain of >7 dB and the input/output return losses $1.43\times 1.23$ mm2, including pads.

A compact, low loss, wideband digital step attenuator (DSA) is presented. The proposed DSA utilizes amplitude/phase-compensated T-type attenuator cells, in which the locations of poles and zeros are manipulated for minimizing variations in attenuation and phase. In addition, the reduced T-type attenuator cells that eliminate series switch transistors are used to achieve low insertion loss (IL). These techniques provide wideband (dc-20 GHz) operation for the DSA, with significantly decreased attenuation/phase errors and reduced IL. The DSA was implemented in a 130-nm silicon-germanium (SiGe) BiCMOS platform. The full attenuator circuit has binary-coded 6-bit digital control inputs with a least significant bit of 0.5-dB attenuation. It has a root-mean-square (rms) attenuation error of 0.37 dB and an rms phase error of 4°, both at 20 GHz. The IL and the input 1-dB compression point at 10 GHz are 4 dB and 10 dBm, respectively. The active core layout area is 0.14 mm2 (1.0 mm $\times $ 0.14 mm).

The doping profile of silicon-germanium heterojunction bipolar transistors (SiGe HBTs) is modified to enhance inverse-mode (IM) device operation. Device improvements are presented in this paper, along with the impact the alterations have on the radiation effects response. This investigation represents the first published occurrence of a radiation-hardening-by-process approach in a SiGe HBT technology. Results show that improving IM performance can degrade the radiation tolerance of the structure. Total ionizing dose and single-event transient (SET) results are provided along with an analysis that utilizes TCAD simulation. An additional profile modification using an implanted vertical superjunction is included in this paper to expand upon how nonradiation specific device modifications can impact SETs.

The impact of electrostatic discharge (ESD) protection circuits on the single-event transients (SETs) of RF building blocks in a 130-nm SiGe BiCMOS (8HP) platform is investigated. For proof-of-concept that SET mitigation can be accomplished through the use of an ESD protection circuit, a single-pole single-throw (SPST) switch was implemented using triple-well nFETs. For substrate noise coupling suppression, a P+, P− substrate (Psub) and N-well guard ring structures were applied. According to two-photon absorption laser experiment results, the SPST switch with ESD protection exhibits the smallest transient peaks at the RF input/output and $\text{V}_{\mathrm {\mathbf {DD}}}$ ESD terminals. Based on these results, an SET mitigation strategy is proposed while maintaining the optimal circuit performance.

The benefits of using p-n-p silicon–germanium (SiGe) heterojuction bipolar transistors (HBTs) in radio frequency (RF) circuits for the mitigation of single-event transients (SETs) have been investigated. As a representative circuit example, p-n-p SiGe-HBT RF single-pole single-throw (SPST) switches have been designed in a complementary SiGe BiCMOS platform. The fabricated p-n-p-based RF switches provide comparable RF performance to n-p-n-based switches. In terms of SET transient peaks and duration, the p-n-p SiGe HBT RF switches exhibit a significant reduction in SET sensitivity compared with their n-p-n counterparts. In the frequency domain, the p-n-p switches show fewer low-frequency spurs than that of the n-p-n switches. In addition, inverse-mode p-n-p SiGe HBT switches provide the best overall SET response among all RF SPST switches investigated.

Best practice in mitigation strategies for single-event transients (SETs) in radio-frequency (RF) receiver modules is investigated using a variety of integrated receivers utilizing inverse-mode silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs). The receivers were designed and implemented in a 130-nm SiGe BiCMOS technology platform. In general, RF switches, low-noise amplifiers (LNAs), and downconversion mixers utilizing inverse-mode SiGe HBTs exhibit less susceptibility to SETs than conventional RF designs, in terms of transient peaks and duration, at the cost of RF performance. Under normal RF operation, the SET-hardened switch is mainly effective in peak reduction, while the LNA and the mixer exhibit reductions in transient peaks as well as transient duration.

The heterogeneous integration of silicon germanium (SiGe) and gallium arsenide (GaAs) technologies is presented using a novel encapsulated packaging approach with organic laminates. The combination of unique and optimally matched interconnects for each die, and the low-loss nature of the organic substrates, provides wideband performance and system design flexibility. A hybrid receiver front-end is realized on multilayer Rogers RO3003 to demonstrate this concept, incorporating a flip-chip bonded SiGe low-noise amplifier and a ribbon-bonded GaAs mixer. The simulated 3-dB bandwidth of the receiver is 4.5–14.5 GHz with a maximum conversion gain of 1.2 dB. Measured results for the packaged module show a 4–14-GHz 3-dB bandwidth and 0.9-dB maximum conversion gain. These results validate that the package is indeed low loss and preserves system performance over the entire bandwidth. The receiver also exhibits a double side band NFmin of 4 dB and a maximum $P_{\text {1 dB, input}}$ of −5.5 dBm. This is the first time that heterogeneous semiconductor technologies have been integrated and encapsulated within a multilayer organic package using different interconnects for each chip to form a receiver. Moreover, the receiver achieves the widest bandwidth among heterogeneous receivers reported to date.

This letter presents a 28-GHz switchless, SiGe bidirectional amplifier (BDA) using a neutralized differential common-emitter amplifier core. On-chip transformer-based input–output baluns are included in the design for single-ended measurement and characterization. The BDA was implemented using GlobalFoundries 8HP 0.13- $\mu \text{m}$ SiGe BiCMOS technology. The forward and backward gains are 10 and 8.6 dB, with noise figure of 3.9 and 4.2 dB, respectively, at 28 GHz. The input-referred 1-dB compression point at 28 GHz for forward and backward operations is −2.4 and −0.4 dBm, respectively. The BDA consumes 26.9 mW of power with a 1.6-V $V_{\mathbf {CC}}$ at a $V_{\mathbf {BE}}$ bias of 0.86 V. The circuit has dimensions of $0.71\times0.90$ mm2 including bondpads.

Si-based Li-ion battery (LIB) anode materials often possess porous structures to accommodate the intrinsic volumetric expansion of Si upon cycling. However, the porous structure may cause poor initial coulombic efficiency (ICE), inadequate cycle life due to the continuous generation of a solid-electrolyte interface, and incompatibility with calendaring processes. To overcome these issues, we designed an optimized Si/C (P–Si/C) composite anode consisting of Si nanoparticles, graphite, and pitch, with a highly densified structure, suppressing Si expansion and enabling compatibility with the calendaring process. To further enhance the cycle life, the surface of the P–Si/C composite was modified by chemical vapor deposition (CVD) using CH4 gas (C–Si/C). The P–Si/C anode exhibited a high ICE of 88.0% with a rapid surge up to 99.0% after only the 4th cycle. The C–Si/C anode presented an improved capacity retention of 49.5% after the 39th cycle, compared with 46.0% for the P–Si/C anode after the 31st cycle, while maintaining the same ICE. Moreover, anodes prepared with 8 wt% P–Si/C or C–Si/C and 92 wt% graphite (m-P-Si/C and m-C-Si/C, respectively) showed higher capacity retentions compared with pure Si/C anodes. The m-C-Si/C anode exhibited a higher capacity retention of 80.1% after the 40th cycle, compared with 71.2% for the m-P-Si/C anode. The m-C-Si/C anode also displayed an extremely low expansion rate and the majority of the expansion was elastically recovered. This C–Si/C composite provided a controllable means to modify the performance of LIBs by simple mixing with graphite.

A cascode configuration with inverse-mode (IM) common-emitter silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) is proposed for the mitigation of single-event transients (SETs) in low-noise amplifiers (LNAs). Conventionally, despite their SET-mitigation capability, IM SiGe HBTs have been considered to be unsuitable for active gain stages due to severe degradation in RF performance. However, with the benefits of aggressive technology scaling, the high frequency performance of IM SiGe HBTs has been significantly improved, thereby enabling them to be utilized in active gain stages with acceptable RF performance. The cascode with IM common-emitter and common-base SiGe HBTs is used for a 2.4 GHz prototype LNA and it achieves adequate RF gain (10 dB) and noise figure (1.9 dB). With regard to SET mitigation, a through-wafer two-photon absorption pulsed-laser experiment is conducted to test the efficacy of this radiation-hardening approach in an advanced 90 nm SiGe BiCMOS platform. The proposed IM-SiGe-HBT-based LNA exhibits 85% reduction in transient peaks compared to the conventional forward-mode cascode LNA.

A power divider/combiner circuit, which simultaneously achieves wide bandwidth, flat gain characteristics, and bidirectional operation, is proposed for multichannel broadband system applications. The proposed circuit utilizes cascode-based bidirectional amplifier cores, which steer the operation modes between a divider and a combiner depending on the control input, and a two-stage distributed-amplifier topology with artificial transmission lines. Implemented in a 130-nm silicon–germanium BiCMOS technology platform, the proposed divider/combiner provides the advantage of seamless integration with digital control blocks. The power divider/combiner exhibits the flat in-band gain of 9 dB and the operational bandwidth of 2–22 GHz, which covers $S$ -, $C$ -, $X$ -, and $Ku$ -bands. In addition, it shows the amplitude imbalance of 0.8 dB, the phase imbalance of 3.5°, the port-to-port isolation of 22 dB, the output 1-dB compression point of 3 dBm, and good impedance matching under 100-mW dc power consumption.

An X-band power amplifier (PA) implemented in a silicon-germanium (SiGe) heterojunction bipolar transistor technology is presented. The SiGe PA was designed for inverse class-F mode using thin-film microstrip (TFMS) lines, eliminating the use of conventional band-limiting lumped inductors and transformers. Thus, simultaneous high efficiency and minimized in-band variation were achieved for X-band (8–12 GHz) applications. In addition, for boosting peak output power (Pout), the common-base transistor in the PA core was designed to operate in a weak avalanche region, which allowed dynamic collector-to-base voltage to swing beyond the collector-base breakdown voltage with open emitter without performance degradation. The fabricated SiGe PA demonstrates a high power-added efficiency (PAE) of 43.2% and a peak Pout of 24.3 dBm at 10 GHz. Benefitting from the utilization of TFMS lines, the PA exhibits a flat response for both PAE (33.3–44%) and peak Pout (23.1–24.5 dBm) for the entire X-band frequency range. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:2868–2871, 2016

The capability of inverse-mode (IM) silicon- germanium (SiGe) heterojunction bipolar transistors (HBTs) for the mitigation of single-event transients (SETs) under large-signal operation was investigated in an RF down-conversion single- balanced mixer using a through-wafer, two-photon absorption pulsed-laser beam experiment and TCAD heavy-ion simulations. The IM SiGe HBTs replace conventional forward-mode (FM) SiGe HBTs in the differential pair, which provides full current steering for frequency mixing operation. Under steady-state conditions, the IM SiGe HBT differential pair exhibits smaller transient peaks with shorter durations compared to the FM SiGe HBTs. In addition, under the injection of a local oscillator (LO) signal with large swing, the IM SiGe HBTs show faster recovery (50% reduction in the best case) from the impact of SETs. In the frequency domain, it is observed that IM SiGe HBTs produce less distortion at the output for an intermediate frequency below 1 GHz. Based on the performance comparison between FM and IM SiGe HBT down-conversion mixers, system design guidelines to compensate the noise figure degradation associated with using IM SiGe HBTs are discussed.

This paper presents a true time delay (TTD)-based transmit/receive (T /R) chipset with 508 ps time delay and 31.5 dB amplitude control for large-scale wideband timed array. The proposed T /R chipset consists of a true time delay circuit, a switched T -type attenuator, and digital control circuits. To compensate the frequency dependent insertion loss characteristics of single-pole double-throw switches, artificial transmission line (ATL), passive-based attenuator, and wideband bi-directional active double-pole double-throw (DPDT) switches are included in the design. In addition, low-path filters (LPFs) with T -type attenuators are applied to the reference signal path to minimize amplitude variations during time delay control. The proposed T /R chipset demonstrates a record delay-range bandwidth product and a flat in-band characteristic of −3.6 dB with ±3.6 dB variation in both operations (transmit and receive) over 2–20 GHz.

The benefits of using through-silicon-vias (TSVs) in silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) low-noise amplifiers (LNAs) over the conventional wire bonding have been investigated for the first time. The parasitics associated with wire bonding can be significantly minimized with TSVs, thereby reducing the LNA performance degradation at the packaging level. To verify simulations and theoretical analysis, a prototype K-band TSV-integrated LNA was implemented in a SiGe HBT platform. The parasitic inductance of TSVs was effectively utilized as an adjustable matching element for the optimum LNA performance. The proposed LNA exhibits minimal degradation compared to the (unpackaged) LNA with probe-supplied ground. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2703–2706, 2015

This letter proposes a wideband active power divider, which realizes multi-octave bandwidth with positive, flat gain, and good isolation. By combining a single stage amplifier with artificial transmission lines and emitter-follower (EF) output stages, a broadband operational bandwidth (2.5-23.0 GHz) and flat gain response (8.8-11.8 dB) with a small chip size are achieved while maintaining good isolation ( $>$ 25 dB) between the output ports. The measured noise figures (NFs) of the two forward paths are lower than 9 dB, the output P1dB (OP1dB) is greater than −9 dBm and the output IP3 (OIP3) is greater than 0 dBm over the 3 dB bandwidth. The maximum amplitude and phase imbalances of the two output ports are 0.2 dB and 1.6 degrees, respectively. The core area of the active power divider is $0.62 \times 0.50$ mm $^{{\mathbf {2}}}$ . The active power divider consumes 20 mA from a 3.3 V DC supply.

A compact, wideband, and low loss multi-section lumped-element Wilkinson power divider/combiner (WPDC) is reported in this letter. The cascade of four $\lambda/16$ LC $\pi$ -networks for a $\lambda/4$ transformer of WPDC, realized by a symmetric inductor with an embedded capacitor technique, can achieve broadband operation and low insertion loss (IL) while saving Si die area. The measured results show a minimum IL of 0.45 dB at 10 GHz. In addition, the IL lower than 1 dB, the isolation (ISO) better than 10 dB, and return losses (RL) higher than 10 dB are satisfied from 5.2 GHz to 18.8 GHz, demonstrating the proposed scheme is applicable to wideband operation. The measured amplitude and phase error are within 0.06 dB and 1.0 degree from DC to 20 GHz, respectively. The core chip size is $0.32 \times 0.34\ \text{mm}^{2}$ . To the authors' best knowledge, the proposed WPDC shows the lowest IL and widest band operational capability for all published Si-based WPDCs, and thus proves useful for low-cost, highly-integrated phased array and wireless communications systems.

This letter proposes a wideband active double-pole double-throw (DPDT) switch for wideband phased array antennas, which realizes multi-octave bandwidth with positive gain and 4-way switching operation using a bi-directional distributed amplifier technique. The measured gain is 2.0–6.0 dB and the input and output return losses are better than 9 dB from 2–22 GHz. The isolation is over 15 dB and the measured input P1dB is greater than $-$ 9.1 dBm and the output P1dB is greater than $-$ 7.8 dBm from 2–22 GHz. The chip size is $1.07 \times 0.98\ \text{mm}^{2}$ , including pads. The switch consumes 10 mA from a 2.5 V supply. Almost identical RF performance is achieved in each of the 4-way switching operations due to a symmetric circuit topology and careful layout. To the authors' knowledge, this is the first demonstration of the active DPDT switch configuration.

This paper presents an X-band 6-bit phase shifter using active bi-directional double-pole, double-throw (DPDT) switches. The phase shifter is implemented in a 130-nm SiGe BiCMOS technology. Three additional tuning bits are included in the design to achieve accurate phase shifting performance. The phase shifter demonstrates a > 11.5-dB gain in both directions of operation over the 8–12 GHz frequency range, with an RMS amplitude error 10 dB and an input-referred 1 dB compression point of −15 dBm. The circuit has dimensions of 2.6 × 1.5 mm2, including pads.

This paper presents a 5-bit true time delay circuit using a standard 0.18 ㎛ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 ㎓. The RMS group delay and amplitude errors are ＜ 1 ps and ＜2 ㏈, respectively. The measured insertion loss is ＜27 ㏈ and the input and output return losses are ＜12 ㏈ at 5-15 ㎓. The current consumption is nearly zero with 1.8 V supply. The chip size is 1.04 × 0.85 ㎟ including pads.

This article presents a Ku-band switched path type phase shifter in a standard 0.13 µm CMOS technology. The phase shifter consists of phase shifting filter networks, DPDT and SPDT switches, a tuning bit, and digital control logic. The phase coverage of the phase shifter is 354° with the LSB of 5.625°. The measured insertion loss is less than 16 dB. The input and output return losses are more than 12 dB. The RMS phase error and amplitude variation are less than 7.6° and 0.3 dB at 10.7–15 GHz, respectively. When the tuning bit is activated, the RMS phase error of 6.3° and the RMS amplitude variation of 0.4 dB are achieved at 10.7–15 GHz. The input P1dB over ∼11 dBm is achieved at 10–15 GHz. The current consumption is nearly zero with 1.2 V supply voltage. The chip size is 1.46 × 0.82 mm2 including pads. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2120–2124, 2013

A 6-bit active bi-directional silicon-germanium (SiGe) digital step attenuator (DSA) with multi-octave bandwidth using an active double-pole double-throw (DPDT) switch is demonstrated. To compensate the insertion loss (IL) and frequency dependent loss characteristics of conventional passive attenuators without using any additional amplifier and equalizer, the proposed attenuator employs active DPDT switches, which provide 4-way switching and bi-directional operation. The measured gain is 7.0–9.6 dB and the input and output return loss is better than 9 dB for 2–20 GHz. The measured root mean square (RMS) amplitude and phase errors in the major state are less than 0.4 dB and 3.0 degree, respectively. The chip size is 1.43 × 1.23 mm2, including pads. The proposed active bi-directional DSA consumes 30 mA from a 2.5 V supply.

This work proposes an asymmetric SPDT transmit/receive (T/R) switch co-optimized with a low-noise amplifier (LNA) tailored to X-band operation and implemented in an 0.13 µm silicon-germanium (SiGe) BiCMOS technology. The switch achieves very high power handling capability in transmit mode, while maintaining low insertion loss, by utilizing an asymmetric topology. In receive mode, low noise is obtained by integrating a lumped-element matching network used simultaneously as a noise matching network for the LNA, as well as a lumped λ/4 transformer for the SPDT switch isolation. In transmit mode, the SPDT-LNA results in 1.1 dB minimum insertion loss, 26 dB isolation, and 26.9 dBm output P1dB at 10 GHz. In receive mode, the measured minimum noise figure (NF) is 1.9 dB with 15 dB gain at 10 GHz. To the authors' best knowledge, these results are the lowest NF and highest transmit output P1dB for any Si-based SPDT-LNA currently reported at X-band, and represents a significant step towards the realization of next-generation of Si-based high performance T/R modules.

An active bi-directional power dividier/combiner circuit based on a distributed topology is proposed. The use of bi-directional amplifiers (BDAs) provides both dividing and combining functions within the same circuit. By utilizing a distributed topology composed of BDAs and artificial transmission lines, a wide operational bandwidth (2–22 GHz) and a large, flat power gain (9 dB) were achieved under DC power consumption of 100 mW. The maximum amplitude and phase imbalances were 0.7 dB and 3°, respectively.

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-μm silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than 2.5 ° and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is 0.93 mm × 0.68 mm, including pads. To the best of the authors’ knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

A 2.3/3.5 GHz dual-band applicable CMOS power amplifier (PA) is implemented using 0.13-μm CMOS process.To achieve the optimal dual-band characteristics, a switched inductor is used for the driver amplifier (DA) load. To improve the PAE and linearity at back off power, class AB-B combined PA transistor cell is used. The measured maximum output power Psat of the dual-band PA is about 29 dBm and 28 dBm at 2.3 GHz and 3.5 GHz, respectively. The achieved EVM is −30 dB and −26 dB at 23 dBm output power for each band, respectively. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:2799–2802, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26437

Early detection of the protein marker troponin I in patients with a higher risk of acute myocardial infarction can reduce the risk of death from heart attacks. Most troponin assays are currently based on the conventional enzyme linked immunosorbent assay and have detection limits in the nano- and picomolar range. Here, we show that by combining viral nanoparticles, which are engineered to have dual affinity for troponin antibodies and nickel, with three-dimensional nanostructures including nickel nanohairs, we can detect troponin levels in human serum samples that are six to seven orders of magnitude lower than those detectable using conventional enzyme linked immunosorbent assays. The viral nanoparticle helps to orient the antibodies for maximum capture of the troponin markers. High densities of antibodies on the surfaces of the nanoparticles and nanohairs lead to greater binding of the troponin markers, which significantly enhances detection sensitivities. The nickel nanohairs are re-useable and can reproducibly differentiate healthy serum from unhealthy ones. We expect other viral nanoparticles to form similar highly sensitive diagnostic assays for a variety of other protein markers.

Nanowires are a focus of research interests as one-dimensional nanosystems and promise exciting applications in nanotechnology, ranging from nanoelectronic devices to cell separation and magnetic labeling in biomedicine. Avariety of methods have been devised to prepare them from magnetic, semiconductor, inorganic, organic, polymer, metallic, and dielectric materials to provide nanowires with novel optical, electrical, catalytic, and magnetic properties. Multilayered or barcode arrangements of nanowires which incorporate different material components are a special case as a result of their spatial arraying, multiple functionalities, and enhanced properties in comparison to those of their single-component counterparts. For instance, Co–Cu barcode nanowires were explored for their high magnetoresistance compared to that of the well-studied thin films, 17] while the coding of magnetic and optical properties in a single wire was targeted for the separation, detection, and transport of cells. Interested in the transport properties and potential applications of nanowires in nanodevices and biomedicine, we have investigated magnetic nanowires by electrodeposition. For biomedical purposes, however, two issues have to be addressed for the implementation of such nanowires, namely surface modification and biocompatibility. In this respect, the synthesis of iron–gold (Fe–Au) nanowires is appealing not only in terms of magnetic properties but also with respect to biological compatibility. On one hand, iron is favored as it is unique in the field of magnetic materials owing to its high magnetization and physicochemical potentiality. It can be easily converted into oxides, which have been thoroughly studied in the form of magnetic nanoparticles in the biomedical field for their magnetic properties and exceptional biocompatibility. On the other hand, gold is a wellestablished material that displays attractive optical properties, biological compatibility, catalytic activity, and excellent surface effects. Thus, it was anticipated that the integration of these two materials into a one-dimensional barcode arrangement on the nanoscale would produce a new nanostructured material that retains the optical and magnetic properties of the respective components, offering synergistically enhanced performance and functionalities which go beyond those of the individual components. Herein, we report the synthesis and characterization of such a kind of multifunctional magnetic–optical Fe–Au barcode nanostructures, that is, nanowires consisting of alternative Fe magnetic and Au optical segments. The Fe–Au barcode nanowires were constructed using anodic alumina oxide (AAO) templates by pulse electrodeposition thus forming iron and gold segments alternatively in a single bath under desired pulse current densities (e.g. 10 mAcm 2 and 0.5 mAcm ) with regulated pulse durations to control the respective segmental lengths (see Experimental Section). The selection of a current density to electrodeposit Fe or Au was based on the evaluation of the composition versus current density profile (Figure 1a), which was acquired from the analysis of the samples each obtained at a given constant current density, by inductively coupled

This letter proposes a wideband switchless bi-directional distributed amplifier in a commercial 0.13 μm CMOS technology, which realizes multi-octave bandwidth with high gain and low noise figure using distributed amplifier technique and cascode-amplifier pair. The measured gain is over 10 dB and measured noise figure is 3.2-6.5 dB. The input and output return losses are better than 9 dB at 3-20 GHz. The measured output P1dB and OIP3 are larger than 8 dBm and 17 dBm at 4-15 GHz. The chip size is 0.96 × 0.85 mm2 including pads. The proposed switchless bi-directional amplifier has almost the same chip size compared to the conventional uni-directional distributed amplifier. The dc power consumption is around 68 mW at 1.5 V supply voltage. Nearly identical RF performances are achieved in the forward and the backward operations due to the symmetric circuit topology and layout.

This article presents a 5-bit broadband digital step attenuator with low insertion loss and phase error using a standard 0.13 μm CMOS process for the phased array antenna.The maximum attenuation of 31 dB with the LSB of 1 dB is achieved at DC-20 GHz. The measured insertion loss of the reference state is