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Drawing inspiration from modern integrated circuit systems composed of various electronic components built on a single silicon platform, the emerging integrated photonics can also follow a similar trend in the pursuit of expanded optical functionalities in constructing compact optoelectronic systems. Herein, vertically integrated a micro‐scale light‐emitting diode (micro‐LED) array with a photodetector (PD) side‐by‐side through a transparent sapphire substrate is proposed. The downward emitted photons from the micro‐LEDs can easily transmit through the transparent sapphire and then be captured by the PD fabricated on the backside of the sapphire. Additionally, by integrating a feedback electrical circuit, a self‐stabilized light output power is demonstrated from the micro‐LED array in such vertically integrated LED/PD architecture, which cannot only monitor the fluctuation of light intensity from the micro‐LED array over time but also provide a constant output feedback to ensure a stable light output power. Such a compact and stable DUV light source composed of micro‐LED array is then employed for constructing a DUV maskless photolithography system. To best of our knowledge, this is the first demonstration of maskless photolithography based on DUV micro‐LED active matrix. The proposed vertically‐stacked optical device architecture by leveraging the transparent substrate offers a new path toward the realization of future integrated photonic systems. [ABSTRACT FROM AUTHOR]

Guided nanowires grown on polymer surfaces facilitate their seamless integration as flexible devices without post‐growth processing steps. However, this is challenging due to the inability of polymer films to provide the required lattice‐matching effect. In this work, this challenge is addressed by replicating highly aligned nanogrooves from a compact disc (CD) onto a casted flexible polydimethylsiloxane (PDMS) surface. Leveraging the replicated nanogrooves, copper hexadecafluorophthalocyanine (F16CuPc) and various metal phthalocyanines are guided into large‐area, self‐aligned nanowires. Subsequently, by employing specifically designed shadow masks during electrode deposition, these nanowires are seamlessly integrated as either a monolithic flexible photodetector with a large sensing area or on‐chip flexible photodetector arrays. The resulting flexible photodetectors exhibit millisecond and long‐term stable response to UV–vis–NIR light. Notably, they demonstrate exceptional bending stability, retaining stable and sensitive photoresponse even at a curvature radius as low as 0.5 cm and after enduring 1000 bending cycles. Furthermore, the photodetector array showcases consistent sensitivity and response speed across the entire array. This work not only proves the viability of guided nanowire growth on flexible polymer surfaces by replicating CD nanogrooves but also underscores the potential for large‐scale monolithic integration of guided nanowires as flexible devices. [ABSTRACT FROM AUTHOR]

The progressive downscaling of silicon‐based microelectronic devices delivers compact and advanced integrated circuits for fast data processing and computing. Similarly, the miniaturization of conventional optoelectronics is also an important frontier of technology for emerging lighting, imaging, communication, and sensing. Herein, this study reports a miniature dual‐functional diode (DF‐diode) with both light‐emitting and light‐detecting functionalities. The proposed micro‐scale DF‐diode exhibits a record high responsivity of 300 mA W−1 at 265 nm with an ultrafast response rise time of 3.7 ns in light‐detecting mode. While operating in emitting mode, it demonstrates an extraordinarily high −3 dB optical bandwidth above 585 MHz with an enhanced external quantum efficiency performance. Significantly, the development of micro‐scale DF‐diodes has opened up a new avenue toward the realization of an effective and long‐distance solar‐blind optical communication system in the future. [ABSTRACT FROM AUTHOR]

The monolithic integration of gallium phosphide (GaP), with its green band gap, high refractive index, large optical non-linearity, and broad transmission range on silicon (Si) substrates, is crucial for Si-based optoelectronics and integrated photonics. However, material mismatches, including thermal expansion mismatch and polar/non-polar interfaces, cause defects such as stacking faults, microtwins, and anti-phase domains in GaP, adversely affecting its electronic properties. Our paper presents a structural and defect analysis using scanning transmission electron microscopy, high-resolution transmission electron microscopy, and scanning nanobeam electron diffraction of epitaxial GaP islands grown on Si nanotips embedded in SiO2. The Si nanotips were fabricated on 200 mm n-type Si (001) wafers using a CMOS-compatible pilot line, and GaP islands were grown selectively on the tips via gas-source molecular-beam epitaxy. Two sets of samples were investigated: GaP islands nucleated on open Si nanotips and islands nucleated within self-organized nanocavities on top of the nanotips. Our results reveal that in both cases, the GaP islands align with the Si lattice without dislocations due to lattice mismatch. Defects in GaP islands are limited to microtwins and stacking faults. When GaP nucleates in the nanocavities, most defects are trapped, resulting in defect-free GaP islands. Our findings demonstrate an effective approach to mitigate defects in epitaxial GaP on Si nanotip wafers fabricated by CMOS-compatible processes. [ABSTRACT FROM AUTHOR]

Multi-channel neural electrodes as a crucial means are of great significance for information exchange between the brain and computers. Herein, we present a 16-channel Si-based active neural probe system that achieves a monolithic integration between the electrodes and circuits in a single probe, making it a standalone integrated electrophysiology recording system. The ASIC prepared on a base (2×2mm2) is a 16-channel analog frontend (AFE) for neural recording, and each channel has a low-noise amplifier (LNA), a bandpass filter (BPF), a buffer and a current bias circuit. The 258 neural signal recording electrodes (22×24μm2) are densely packed on a 50 μm thick, 100 μm wide, and 3 mm long shank. The ASIC of neural probe, internal interconnecting wires are all implemented in commercial SMIC 0.18 μm CMOS technology. The neural probe system achieves a 3.6 μVrms input-referred noise (IRN) in a bandwidth of 1.1Hz-10 kHz, 70.8 μW power consumption, 0.0785 mm2 area per channel, as well as an AFE gain of 58.1 dB Furthermore, the impedances of the Au electrodes can be obtained as 0.5–2.1 MΩ at a frequency of 1 kHz. The functionality of a 16-channel silicon-based neural probe is validated in an in-vivo experiment on lab rats.

The realization of high quality (0001) GaN on Si(100) is paramount importance for the monolithic integration of Si‐based integrated circuits and GaN‐enabled optoelectronic devices. Nevertheless, thorny issues including large thermal mismatch and distinct crystal symmetries typically bring about uncontrollable polycrystalline GaN formation with considerable surface roughness on standard Si(100). Here a breakthrough of high‐quality single‐crystalline GaN film on polycrystalline SiO2/Si(100) is presented by quasi van der Waals epitaxy and fabricate the monolithically integrated photonic chips. The in‐plane orientation of epilayer is aligned throughout a slip and rotation of high density AlN nuclei due to weak interfacial forces, while the out‐of‐plane orientation of GaN can be guided by multi‐step growth on transfer‐free graphene. For the first time, the monolithic integration of light‐emitting diode (LED) and photodetector (PD) devices are accomplished on CMOS‐compatible SiO2/Si(100). Remarkably, the self‐powered PD affords a rapid response below 250 µs under adjacent LED radiation, demonstrating the responsivity and detectivity of 2.01 × 105 A/W and 4.64 × 1013 Jones, respectively. This work breaks a bottleneck of synthesizing large area single‐crystal GaN on Si(100), which is anticipated to motivate the disruptive developments in Si‐integrated optoelectronic devices. [ABSTRACT FROM AUTHOR]

Nowadays, an increasing share of photovoltaic (PV) systems makes use of module‐ or submodule‐level power electronics (PE). Furthermore, PE is used in stand‐alone devices powered by PV‐storage solutions. One way to facilitate further implementation of PE in PV applications is to integrate PE components into crystalline silicon PV cells. Herein, the COSMOS device is introduced, denoting COmbined Solar cell and metal‐oxide‐semiconductor field‐effect transistor (MOSFET). Specifically, the combined manufacturing of lateral power MOSFETs and interdigitated back contact solar cells with tunnel‐oxide passivated contacts (TOPCon) on a single wafer is reported. Many steps of the proposed process flow are used for the fabrication of both devices, enabling cost‐effective integration of the MOSFET. Both n‐type solar cells with integrated p‐channel MOSFETs (PMOS) and p‐type solar cells with integrated n‐channel MOSFETs (NMOS) are successfully manufactured. NMOS devices perform better in achieving low on‐resistance, while PMOS devices exhibit lower leakage currents. Furthermore, the study reveals integration challenges where off‐state leakage currents of the MOSFET can increase due to illumination and specific configurations of monolithic interconnections between the MOSFET and the solar cell. Nevertheless, for both n‐type and p‐type solar cells, efficiencies exceeding 20% are achieved, highlighting the potential of the proposed process for COSMOS devices. [ABSTRACT FROM AUTHOR]

Abstract Guided nanowires grown on polymer surfaces facilitate their seamless integration as flexible devices without post‐growth processing steps. However, this is challenging due to the inability of polymer films to provide the required lattice‐matching effect. In this work, this challenge is addressed by replicating highly aligned nanogrooves from a compact disc (CD) onto a casted flexible polydimethylsiloxane (PDMS) surface. Leveraging the replicated nanogrooves, copper hexadecafluorophthalocyanine (F16CuPc) and various metal phthalocyanines are guided into large‐area, self‐aligned nanowires. Subsequently, by employing specifically designed shadow masks during electrode deposition, these nanowires are seamlessly integrated as either a monolithic flexible photodetector with a large sensing area or on‐chip flexible photodetector arrays. The resulting flexible photodetectors exhibit millisecond and long‐term stable response to UV–vis–NIR light. Notably, they demonstrate exceptional bending stability, retaining stable and sensitive photoresponse even at a curvature radius as low as 0.5 cm and after enduring 1000 bending cycles. Furthermore, the photodetector array showcases consistent sensitivity and response speed across the entire array. This work not only proves the viability of guided nanowire growth on flexible polymer surfaces by replicating CD nanogrooves but also underscores the potential for large‐scale monolithic integration of guided nanowires as flexible devices.

Modern society is the development stage of informationization and intelligence, and display is the key factor to realize information exchange and intelligence. Among the many current displays, Micro light‐emitting diode (µLED) display is used as a disruptive next‐generation display. Based on the same GaN material and process platform, we propose the vertical integrated device, where Indium Gallium Nitride/Gallium Nitride (InGaN/GaN) based µLED and GaN bipolar junction transistors (BJT) monolithically integrated vertically on a single GaN chip. The ultraviolet optoelectronic characteristics of µLED on BJT (LET) devices were simulated by using Silvaco TCAD software. By optimizing the size and concentration of the epitaxy layer, the optimized integrated device is obtained with high current gain and strong response to UV light. The LET can be used as both receiver and emitter, which is regulated by changing the light input power or base voltage. This device can be driven by the base voltage and UV light alone, which is a multifunctional integrated device for light emitting, detecting, sensing, driving and regulating. [ABSTRACT FROM AUTHOR]

Micro-LED is considered an emerging display technology with significant potential for high resolution, brightness, and energy efficiency in display applications. However, its decreasing pixel size and complex manufacturing process create challenges for its integration with driving units. Recently, researchers have proposed various methods to achieve highly integrated micro-structures with driving unit. Researchers take advantage of the high performance of the transistors to achieve low power consumption, high current gain, and fast response frequency. This paper gives a review of recent studies on the new integration methods of micro-LEDs with different types of transistors, including the integration with BJT, HEMT, TFT, and MOSFET. [ABSTRACT FROM AUTHOR]

The paper reports on high voltage (HV)-isolated MEMS quad–solenoid transformers for compact isolated gate drivers and bias power supplies. The component is wafer-level fabricated via a novel MEMS micro-casting technique, where the tightly coupled quad–solenoid chip consists of monolithically integrated 3D inductive coils and an inserted ferrite magnetic core for high-efficiency isolated power transmission through electromagnetic coupling. The proposed HV-isolated transformer demonstrates a high inductance value of 743.2 nH, along with a small DC resistance of only 0.39 Ω in a compact footprint of 6 mm2, making it achieve a very high inductance integration density (123.9 nH/mm2) and the ratio of L/R (1906 nH/Ω). More importantly, with embedded ultra-thick serpentine-shaped (S-shaped) SiO2 isolation barriers that completely separate the primary and secondary windings, an over 2 kV breakdown voltage is obtained. In addition, the HV-isolated transformer chips exhibit a superior power transfer efficiency of over 80% and ultra-high dual-phase saturation current of 1.4 A, thereby covering most practical cases in isolated, integrated bias power supplies such as high-efficiency high-voltage-isolated gate driver solutions. [ABSTRACT FROM AUTHOR]

Abstract The realization of high quality (0001) GaN on Si(100) is paramount importance for the monolithic integration of Si‐based integrated circuits and GaN‐enabled optoelectronic devices. Nevertheless, thorny issues including large thermal mismatch and distinct crystal symmetries typically bring about uncontrollable polycrystalline GaN formation with considerable surface roughness on standard Si(100). Here a breakthrough of high‐quality single‐crystalline GaN film on polycrystalline SiO2/Si(100) is presented by quasi van der Waals epitaxy and fabricate the monolithically integrated photonic chips. The in‐plane orientation of epilayer is aligned throughout a slip and rotation of high density AlN nuclei due to weak interfacial forces, while the out‐of‐plane orientation of GaN can be guided by multi‐step growth on transfer‐free graphene. For the first time, the monolithic integration of light‐emitting diode (LED) and photodetector (PD) devices are accomplished on CMOS‐compatible SiO2/Si(100). Remarkably, the self‐powered PD affords a rapid response below 250 µs under adjacent LED radiation, demonstrating the responsivity and detectivity of 2.01 × 105 A/W and 4.64 × 1013 Jones, respectively. This work breaks a bottleneck of synthesizing large area single‐crystal GaN on Si(100), which is anticipated to motivate the disruptive developments in Si‐integrated optoelectronic devices.

Ferroelectric devices and monolithic three-dimensional integration technology (M3D) with good CMOS process compatibility have emerged as promising solutions to scaling issue at the device and system levels, respectively. In this study, we developed a monolithic co-integration scheme, which sequentially fabricates CMOS devices and ferroelectric field-effect transistors (FeFETs) on the front-end-of-line (FEOL) area of the same 8-inch wafer. To fabricate FeFETs after CMOS device fabrication and achieve co-integration on the FEOL area, an etch-back process was developed to remove thick oxide over a wide area. FeFET fabrication involves the selective laser spike annealing (LSA) in the source/drain region of the FeFET to implement the low thermal budget process crucial for monolithic integration. In our test, LSA resulted in a lower sheet resistance compared to conventional rapid thermal annealing (RTA), thus validating its performance for dopant activation. The monolithic co-integration completed by incorporating this LSA was evaluated by measuring the electrical characteristics of CMOS, FeFET and FeFET inverter, which was first fabricated in this work. By developing this monolithic co-integration, this work offers an opportunity to integrate diverse new devices in addition to the FeFET with CMOS and achieve further advancements in technology.

The paper investigates the terahertz performance of a mutually injection-locked multi-element high electron mobility avalanche transit time (HEM-ATT) source based on AlGaN/GaN two-dimensional electron gas (2-DEG). Utilizing a nanostrip patch type planar coupling circuit, mutual injection locking between adjacent elements is achieved. The paper provides a comprehensive analysis of the integrated power combining technique in the mutually injection-locked multi-element HEM-ATT oscillator. A ten-element mutually injection-locked integrated power combined source is designed for operation at 1.0 THz, and simulation studies are conducted to examine its DC, large-signal, and avalanche noise characteristics. The capability of generating a narrow-band terahertz wave is verified by introducing various levels of structural mismatches between the elements. Results indicate that the ten-element HEM-ATT oscillator can deliver 2.27 W peak power with a 17% DC to THz conversion efficiency at 1.0 THz. The average noise measure of the oscillator is found to be 12.54 dB. Additionally, the terahertz performance of the mutually injection-locked ten-element HEM-ATT oscillator is compared with other state-of-the-art THz sources to evaluate its potentiality as an excellent integrated THz radiator.

Waveguide-integrated photodetectors (PDs) play a crucial role in mid-infrared (MIR) silicon photonics, serving vital functions in sensing and communication applications. III-V semiconductors are widely used in MIR PDs, and many state-of-the-art III-V PDs on Si still require complicated integration methods. Heteroepitaxial growth technology is a competitive approach for large-scale integration; however, buffers capable of simultaneously achieving heteroepitaxial growth and optical coupling are limited in the MIR region. In this paper, we report a waveguide-integrated InAs PD on Si, incorporating a GaAs/Ge buffer design based on interfacial misfit (IMF) technology. We optimize the geometric structure and calculate the optoelectronic properties at a wavelength of 3 μm. For our simulated parameters, the optimal PD achieves a responsivity of 2.77 A/W and a detectivity of 4.68×109 cm·Hz1/2·W-1 at -1V. This work suggests a promising avenue to further develop high-detectivity and high-speed PDs for MIR silicon photonics.

Scaling on-chip memory capacity is one of the primary approaches to mitigate memory wall bottlenecks. Various 2.5-D/3-D integration schemes, leveraging novel partitioning, are being actively explored to improve system performance. However, fine-grained functional partitioning of memory macros is not widely reported. As static RAM (SRAM) scaling stagnates with emerging CMOS logic roadmap, we propose a partitioning of low-level (faster access) caches in 3-D using an array under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous integration, achieving up to 12% higher operating frequency with 50% leakage power reduction in the memory macros. Applied on a 64-bit mobile system-on-chip (SoC) CPU core, we achieve up to 60% higher energy efficiency compared with 2-D baseline and 14% increase in operating frequency compared with standard memory-on-logic 3-D partitioning scheme.

Hetero‐epitaxy for integration of efficient III‐V lasers on silicon can enable wafer‐scale silicon photonic integrated circuits, which can unleash the full advantages of silicon photonics in production on large silicon wafers with low cost, high throughput, and large bandwidth and large‐scale integration. In this work, efficient III‐V distributed feedback (DFB) lasers selectively grown on (001) silicon‐on‐insulator (SOI) wafers are presented. The selective hetero‐epitaxy of sufficiently large areas of III‐V segments allows the demonstration of DFB lasers on the SOI wafer. The fabricated DFB lasers feature a co‐planar configuration with the Si layer, allowing for efficient coupling between III‐V lasers and Si waveguides. The unique III‐V‐on‐insulator structure also provides strong optical confinement for the lasers. Gratings are designed and fabricated with minimal non‐radiative recombination and a simple process with good tolerance. The optically pumped DFB laser has a low lasing threshold of around 17.5 µJ cm−2, stable single‐mode lasing at 1.5 µm, a side‐mode‐suppression‐ratio of over 35 dB, and a spontaneous emission factor of 0.7. The results here demonstrate a step forward towards wafer‐scale integration with monolithically grown lasers, thus outlining the prospect of fully integrated Si photonics. [ABSTRACT FROM AUTHOR]

The surface morphology of a buffer template is an important factor in the heteroepitaxial integration of optoelectronic devices with a significant lattice mismatch. In this work, InP-based long-wave infrared (~8 µm) emitting quantum cascade lasers with active region designs lattice-matched to InP were grown on GaAs and Si substrates employing InAlGaAs step-graded metamorphic buffer layers, as a means to assess the impact of surface roughness on device performance. A room-temperature pulsed-operation lasing with a relatively good device performance was obtained on a Si template, even with a large RMS roughness of 17.1 nm over 100 µm2. Such results demonstrate that intersubband-operating devices are highly tolerant to large RMS surface roughness, even in the presence of a high residual dislocation density. [ABSTRACT FROM AUTHOR]

Currently, the relevance of optical devices has increased due to the physical limitations of the electrical transmission medium and the proximity of the limit of Moore's Law. Furthermore, the fabrication of optical devices on monolithic silicon substrates has gained importance in recent years thanks to manufacturing technologies in the microelectronics industry. For this reason, this paper aims to carry out the electrical characterization of an optical device manufactured with commercial austria micro system technology of complementary metal oxide semiconductors of 0.35 µm. The methodology consists of implementing an optical device, with an incandescent optical source called a microlamp, a waveguide and a photodiode. The microlamp was projected between two metal layers connected by tungsten vias that act as filaments covered by SiO2 dielectric to prevent oxidation. The results of the electrical characterization of the optical device show that the microlamp reaches a maximum current of 48 mA and stops working at higher currents. The waveguide was designed with a SiO2 core and it was discovered that the TiN layers were found to be part of the waveguide causing it to behave as an emitter in the 2.5-5 µm region. [ABSTRACT FROM AUTHOR]

Integrating quantum dot (QD) gain elements onto Si photonic platforms via direct epitaxial growth is the ultimate solution for realizing on‐chip light sources. Tremendous improvements in device performance and reliability have been demonstrated in devices grown on planar Si substrates in the last few years. Recently, electrically pumped QD lasers deposited in narrow oxide pockets in a butt‐coupled configuration and on‐chip coupling have been realized on patterned Si photonic wafers. However, the device yield and reliability, which ultimately determines the scalability of such technology, are limited by material uniformity. Here, detailed analysis is performed, both experimentally and theoretically, on the material asymmetry induced by the pocket geometry and provides unambiguous evidence suggesting that all pockets should be aligned to the [1 1¯0$\bar{1}\ 0$] direction of the III‐V crystal for high yield, high performance, and scalable on‐chip light sources at 300 mm scale. [ABSTRACT FROM AUTHOR]

This work presents a MEMS resonator used as an ultra-high resolution water vapor sensor (humidity sensing) to detect human activity through finger movement as a demonstrator example. This microelectromechanical resonator is designed as a clamped-clamped beam fabricated using the top metal layer of a commercial CMOS technology (0.35 μm CMOS-AMS) and monolithically integrated with conditioning and readout circuitry. Sensing is performed through the resonance frequency change due to the addition of water onto the clamped-clamped beam coming from the moisture created by the evaporation of water in the human body. The sensitivity and high-speed response to the addition of water onto the metal bridge, as well as the quick dewetting of the surface, make it suitable for low-power human activity sensing. [ABSTRACT FROM AUTHOR]

Programmable photonic circuits require an electronic control layer to configure and stabilize the optical functionality at run‐time. Such control action is normally implemented by supervising the status of the circuit with integrated light monitors and by providing feedback signals to integrated actuators. This paper demonstrates that the control action can be effectively performed with electrical signals that are time‐multiplexed directly on the photonic chip. To this aim, the necessary electronic functionalities are monolithically integrated in a conventional 220 nm silicon photonics platform with no changes to the standard fabrication process. By exploiting a non‐conventional structure to implement metal‐oxide–semiconductor field‐effect transistors, an electronic controller is co‐designed into a programmable photonic circuit to enable a time‐multiplexed readout of integrated photodetectors and sequential activation of thermal phase shifters with on‐chip electronic memory. The accuracy of the time‐multiplexed control, achieved on a time scale of less than 10 ms, is demonstrated by penalty‐free routing of 10 Gbit s−1 modulated signals. This approach can be straightforwardly applied to large‐scale photonic chips to reduce the number of required electrical input/output connections. [ABSTRACT FROM AUTHOR]

Next‐generation shortwave infrared (SWIR) imaging systems generally require a multidimensional information sensing capability (including intensity, wavelength, polarization, phase, etc.), a highly integrated photodetector unit, and information processing, allowing for miniaturization and low‐cost production. However, traditional polarized SWIR imaging systems with integrated polarizer arrays as supplementary filters and silicon‐based amplifying circuits are complicated and very expensive. Here, a SWIR polarization‐sensitive photodetector and a monolithic integrated polarization amplification system (MIPAS) based on well‐aligned carbon nanotube (CNT) arrays are demonstrated. The polarization‐sensitive CNT photodetector exhibits anisotropic ratios of ≈5.18 and ≈7.56 at 1800 and 2000 nm wavelengths, respectively, and high‐resolution characteristics that can be utilized to image SWIR laser spots with a radius of less than 10 µm. Furthermore, MIPAS including a CNT field‐effect transistor, a CNT loading resistor, and a polarization‐sensitive CNT photodetector is used to increase the anisotropic ratio of the CNT photodetector. The amplified anisotropic ratio is improved up to 173 and 243 at 1800 and 2000 nm wavelengths, respectively, which is the maximum reported in the SWIR band. Our work demonstrates that the CNT polarization‐sensitive photodetector has the potential for SWIR polarization imaging with a monolithic integrated polarization amplification system. [ABSTRACT FROM AUTHOR]

A photoelectrochemical (PEC) water splitting device based on a dual‐junction monolithic tandem cell that utilizes NiOOH/FeOOH/BiVO4/SnO2/Ta:SnO2 (TTO)/tunnel oxide passivated contact (TOPCon) Si is reported. The PEC device achieves a maximum photocurrent density of 1.4 mA cm−2 (equal to a solar‐to‐hydrogen conversion efficiency of 1.72%) in 1.0 m potassium borate solution (pH 9) when illuminated with air mass 1.5 G simulated solar irradiation, which is the highest value among dual‐junction monolithic photoelectrochemical cells except for III–V materials. The TOPCon Si not only works as an appropriate bottom photoelectrode for subsequent high‐temperature BiVO4 processing but also offers a high photovoltage of 590 mV. Transparent and conductive TTO grown by pulsed laser deposition serves as a recombination layer to achieve effective integration. In addition, the TTO provides chemical and physical protection, allowing the surface of the TOPCon Si to exhibit 24 h of tandem cell stability under weak base electrolyte conditions. The SnO2 hole‐blocking layer inserted between TTO and BiVO4 enhances the charge separation of BiVO4, allowing the device to achieve high efficiency. Artificial leaf‐type monolithic tandem cells consisting of NiFe/BiVO4/SnO2/TTO/TOPCon Si/Ag/Ti/Pt with a solar‐to‐hydrogen efficiency of 0.44% are also demonstrated. [ABSTRACT FROM AUTHOR]

In this work, dual-gate enhancement-mode (E-mode) device based NAND circuit (DG-NAND) and the NAND block with double E-mode devices (DD-NAND) are developed and fabricated based on the GaN MIS-HEMTs (metal-insulator-semiconductor-high-electron-mobility-transistors) platform. The DG-NAND circuit has an area of 0.118 mm2 with the probe pad, which is 24% lower than the area of the DD-NAND circuit. Both static and dynamic experimental results validate the advantages of performance improvement of NAND circuits designed by dual-gate technology at an input voltage of 9 V. This paper demonstrates the design potential of dual-gate NAND in an all-GaN MIS-HEMTs platform through compact design.

Monolithically integrated pixels, with stacked PbS colloidal quantum dot (CQD) photodiodes and organic blocking diodes, are developed as the building block for constructing a short‐wavelength infrared (SWIR) crossbar imaging array. Arising from the back‐to‐back stacked configuration and a favorable energy level alignment, holes are blocked from the photodiode at zero and forward biases, which results in the normally‐OFF behavior of the pixels. Based on such device characteristics, the monolithically integrated pixels can effectively suppress electrical crosstalk under illumination in the crossbar array and consume nearly zero standby power. Furthermore, an 8×8 crossbar imaging array with both high imaging quality and low power consumption is achieved, which features as a high‐performance visible–SWIR imaging sensor. [ABSTRACT FROM AUTHOR]

A Schottky barrier high-electron-mobility avalanche transit time (HEM-ATT) structure is proposed for terahertz (THz) wave generation. The structure is laterally oriented and based on AlGaN/GaN two-dimensional electron gas (2-DEG). Trenches are introduced at different positions of the top AlGaN barrier layer for realizing different sheet carrier density profiles at the 2-DEG channel; the resulting devices are equivalent to high–low, low–high and low-high–low quasi-Read structures. The DC, large-signal and noise simulations of the HEM-ATTs were carried out using the Silvaco ATLAS platform, non-sinusoidal-voltage-excited large-signal and double-iterative field-maximum small-signal simulation models, respectively. The breakdown voltages of the devices estimated via simulation were validated by using experimental measurements; they were found to be around 17–18 V. Under large-signal conditions, the series resistance of the device is estimated to be around 20 Ω. The large-signal simulation shows that the HEM-ATT source is capable of delivering nearly 300 mW of continuous-wave peak power with 11% conversion efficiency at 1.0 THz, which is a significant improvement over the achievable THz power output and efficiency from the conventional vertical GaN double-drift region (DDR) IMPATT THz source. The noise performance of the THz source was found to be significantly improved by using the quasi-Read HEM-ATT structures compared to the conventional vertical Schottky barrier IMPATT structure. These devices are compatible with the state-of-the-art medium-scale semiconductor device fabrication processes, with scope for further miniaturization, and may have significant potential for application in compact biomedical spectroscopy systems as THz solid-state sources. [ABSTRACT FROM AUTHOR]

This work reviews the design and applicability of beam-forming networks based on Coherently Radiating Periodic Structures (CORPS-BFN) at Terahertz (THz) frequency bands. These versatile networks offer two operation modes: a continuous beam steering – feeding an antenna array with a linearly progressive phase distribution – using a reduced number of phase controls; or a multi-beam operation, generating independent, overlapped beams. These networks are built upon the concatenation of power combiners/dividers (PCDs) with isolated outputs. The isolation is provided by monolithically integrated resistors, implemented with Ti/TiO 2 thin films for the first time. In this work, a planar prototype of a 2 × 3 (inputs/outputs) microstrip CORPS-BFN for operation in the WR3.4/WM-864 band (220–330 GHz) on a thin 50 μ m Indium Phosphide (InP) substrate is designed, fabricated, and characterized. The measured S-parameters show a reflection coefficient better than -15 dB and an insertion loss between 1.6 and 3.2 dB in the whole band. In addition, an isolation better than 20 dB between the input ports has been measured. An overall remarkable agreement is observed between the measurements and the simulations. Last, the applications, scalability and efficiency of this type of networks at the targeted band are discussed in detail. [ABSTRACT FROM AUTHOR]

Micro-LED is considered an emerging display technology with significant potential for high resolution, brightness, and energy efficiency in display applications. However, its decreasing pixel size and complex manufacturing process create challenges for its integration with driving units. Recently, researchers have proposed various methods to achieve highly integrated micro-structures with driving unit. Researchers take advantage of the high performance of the transistors to achieve low power consumption, high current gain, and fast response frequency. This paper gives a review of recent studies on the new integration methods of micro-LEDs with different types of transistors, including the integration with BJT, HEMT, TFT, and MOSFET.

The monolithic integration structure of the AlGaN/InGaN/GaN−based high electron mobility transistor (HEMT) and light−emitting diode (LED) is attractive in LED lighting and visible light communication (VLC) systems owing to the reduction in parasitic elements by removing metal interconnections. Due to the band−offset and polarization effect, inserting a certain thickness in the InGaN layer into the traditional AlGaN/GaN single heterostructure increases the density of 2DEG to nearly twice the original. At the same time, inserting the InGaN quantum well layer can also improve the luminous efficiency of LED. In this paper, the physical models of two−dimensional electron gas (2DEG) densities and the threshold voltage of AlGaN/InGaN/GaN HEMTs are established and verified with experimental results from the literature. According to the calculation results, the two−dimensional electron gas (2DEG) density in the AlGaN/InGaN/GaN HEMT is 1.47 × 1013 cm−2, and the two−dimensional hole gas (2DHG) density is 0.55 × 1013 cm−2, when Al% = 0.2, In% = 0.1, dAlGaN = 20 nm. In addition, a physical model for the radiative recombination rate in the monolithic integration structure of HEMT−LED is proposed. This work provides a design guideline for AlGaN/InGaN/GaN HEMT and its application in visible light communication systems. [ABSTRACT FROM AUTHOR]

Epitaxial growth of III–V materials on Si is a promising approach for large-scale, relatively low-cost, and high-efficiency Si-based multi-junction solar cells. Several micron-thick III–V compositionally graded buffers are typically grown to reduce the high threading dislocation density that arises due to the lattice mismatch between III–V and Si. Here, we show that optically transparent n-In0.1Al0.9As/n-GaAs strained layer superlattice dislocation filter layers can be used to reduce the threading dislocation density in the GaAs buffer on Si while maintaining the GaAs buffer thickness below 2 μm. Electron channeling contrast imaging measurements on the 2 μm n-GaAs/Si template revealed a threading dislocation density of 6 × 107 cm−2 owing to the effective n-In0.1Al0.9As/n-GaAs superlattice filter layers. Our GaAs/Si tandem cell showed an open-circuit voltage of 1.28 V, Si bottom cell limited short-circuit current of 7.2 mA/cm2, and an efficiency of 7.5%. This result paves the way toward monolithically integrated triple-junction solar cells on Si substrates. [ABSTRACT FROM AUTHOR]

In this study, AlGaN/GaN light-emitting HEMTs (LE-HEMT) with a single quantum well inserted in different locations in the epitaxy layers are fabricated and analyzed. For both structures, light-emitting originated from electrons in the 2DEG and holes from the p-GaN for radiative recombination is located in the quantum well. To investigate the importance of the location of single quantum well, optical characteristics are compared by simulation and experimental results. The experimental results show that the main light-emitting wavelength is shifted from 365 nm in the UV range to 525 nm in the visible range when the radiative recombination is confined in the quantum well and dominates among other mechanisms. Epi B, which has a quantum well above the AlGaN barrier layer in contrast to Epi A which has a quantum well underneath the barrier, shows better intensity and uniformity in light-emitting. According to the simulation results showing the radiative distribution and electron concentrations for both structures, the lower quantum efficiency is due to the diverse current paths in Epi A. On the other hand, Epi B shows better quantum confinement and therefore better luminescence in the same bias condition, which is consistent with experimental observations. These findings are critical for advancing the performance of LE-HEMTs. [ABSTRACT FROM AUTHOR]

Photonic Integrated Circuits (PICs) are taking a major role in the telecommunications and datacenter markets. The increased complexity of coexisting and fast evolving standards for Passive Optical Networks (PONs) suggests the introduction of PICs will be the next step in PON related optoelectronics. The PICs ecosystem has greatly matured in the past years, becoming a solution that can cope with the requirements of industry and academia, and presenting the flexibility of combining multiple platforms available towards viable commercial solutions. In this review, the evolution of PONs and PICs is presented, with a focus on the optoelectronic integration of PICs for PONs and coherent PONs. To demonstrate the potential of PICs and their combination with electronics, a quasi-coherent receiver based on co-hosted PIC and Application Specific Integrated Circuit (ASIC) is presented and characterized. [ABSTRACT FROM AUTHOR]

The rapidly increasing demand for wearable electronic devices has motivated research in low-cost and flexible printed batteries with diverse form factors and architectures. In the past, technological achievements in the field have been emphasized, overlooking the industrial and market requirements. However, different applications require different battery chemistries and formats, that greatly impacts the manufacturing process and competition landscape. These chemistries and formats should therefore be selected carefully to maximize the chances for commercial success. As some of these technologies are starting to be marketed for portable electronics, there is a pressing need to evaluate different printing technologies and compare them in terms of the processing constraints and product requirements of specific electronic devices. By evaluating the intrinsic strengths and current limitations of printed battery technologies, development pathways can be prioritized, and potential bottlenecks can be overcome to accelerate the path to market.

In this work, we demonstrate a fully screen printed supercapacitor (SC) with a monolithic structure. The monolithic SCs were prepared by screen printing different SC layers on top of each other. After the layers were printed, an aqueous electrolyte was added to the screen printed separator, and the printed structure was sealed. The prepared monolithic SCs showed similar electrical characteristics to a face-to-face laminated stacked SC with a paper separator. Interfaces between the screen printed SC layers were observed with a scanning electron microscope. Results show that the screen printing process is reproducible and can be used to fabricate SCs reliably. This fabrication process also eliminates an assembly step that is common in laminated stacked SCs. Hence the introduced screen printing process shows feasible and scalable fabrication for the monolithic SCs. Advanced fabrication of the printed monolithic SCs can benefit different applications, such as wireless sensor devices with environmentally sustainable energy storage units, and the integration of an energy storage unit on the same substrate with the printed circuits. [Display omitted] • Development of a printable separator enables layer-by-layer fabrication. • Monolithic supercapacitors fabricated using screen printing. • Fully printed supercapacitor based on sustainable and non-harmful materials. [ABSTRACT FROM AUTHOR]

The paper reports on high voltage (HV)-isolated MEMS quad–solenoid transformers for compact isolated gate drivers and bias power supplies. The component is wafer-level fabricated via a novel MEMS micro-casting technique, where the tightly coupled quad–solenoid chip consists of monolithically integrated 3D inductive coils and an inserted ferrite magnetic core for high-efficiency isolated power transmission through electromagnetic coupling. The proposed HV-isolated transformer demonstrates a high inductance value of 743.2 nH, along with a small DC resistance of only 0.39 Ω in a compact footprint of 6 mm2, making it achieve a very high inductance integration density (123.9 nH/mm2) and the ratio of L/R (1906 nH/Ω). More importantly, with embedded ultra-thick serpentine-shaped (S-shaped) SiO2 isolation barriers that completely separate the primary and secondary windings, an over 2 kV breakdown voltage is obtained. In addition, the HV-isolated transformer chips exhibit a superior power transfer efficiency of over 80% and ultra-high dual-phase saturation current of 1.4 A, thereby covering most practical cases in isolated, integrated bias power supplies such as high-efficiency high-voltage-isolated gate driver solutions.

The surface morphology of a buffer template is an important factor in the heteroepitaxial integration of optoelectronic devices with a significant lattice mismatch. In this work, InP-based long-wave infrared (~8 µm) emitting quantum cascade lasers with active region designs lattice-matched to InP were grown on GaAs and Si substrates employing InAlGaAs step-graded metamorphic buffer layers, as a means to assess the impact of surface roughness on device performance. A room-temperature pulsed-operation lasing with a relatively good device performance was obtained on a Si template, even with a large RMS roughness of 17.1 nm over 100 µm2. Such results demonstrate that intersubband-operating devices are highly tolerant to large RMS surface roughness, even in the presence of a high residual dislocation density.

This work presents a MEMS resonator used as an ultra-high resolution water vapor sensor (humidity sensing) to detect human activity through finger movement as a demonstrator example. This microelectromechanical resonator is designed as a clamped-clamped beam fabricated using the top metal layer of a commercial CMOS technology (0.35 μm CMOS-AMS) and monolithically integrated with conditioning and readout circuitry. Sensing is performed through the resonance frequency change due to the addition of water onto the clamped-clamped beam coming from the moisture created by the evaporation of water in the human body. The sensitivity and high-speed response to the addition of water onto the metal bridge, as well as the quick dewetting of the surface, make it suitable for low-power human activity sensing.

Intelligent display with multifunctional integration is becoming the frontier and focus of current research on novel display technology. How to realize the single chip integration of lighting with other functions such as switching and driving remain the technical and scientific problems that are desiderated to solve. This article proposes a novel idea of a light‐emitting triode (LET), in which light‐emitting diode (LED) and bipolar junction transistor (BJT) are vertically integrated on a single GaN chip with the same GaN processing. The photoelectrical performances of this "LED on BJT" structure are investigated using finite element simulation. It is verified that LET with electrical–optical modulation and amplification capabilities could be achieved simultaneously. By optimizing the device structure and the doping concentrations of each epitaxial layers, the LET can be operated at a low modulation current injection in the range of tens of microamperes. Therefore, the LET is expected to be directly driven by IC circuits without additional amplifier circuits. Meanwhile, the LET cut‐off frequency can reach more than 80 MHz, allowing the applications of pulse width modulation (PWM) driving and visible light communications. [ABSTRACT FROM AUTHOR]

Off‐grid devices require autonomous power supply systems that can be achieved via coupling a solar cell with a supercapacitor in one integrated multifunctional device that is able to harvest energy from the environment, store, and release it on demand. Herein, a straight‐forward approach is proposed to realize a monolithic photosupercapacitor rechargeable under illumination by integrating a silicon (Si) solar cell with an electrochemical double‐layer capacitor (EDLC) based on mesoporous N‐doped carbon nanospheres (MPNC) in a three‐electrode configuration, i.e., via a shared electrode. The optimized porous structure of the MPNC‐EDLC electrodes results in a high storage efficiency of 95% and a superior performance compared to an activated carbon based EDLC. When monolithically integrated with a highly compatible and technologically robust Si solar cell in a photosupercapacitor, fast charging up to 0.63 V (2.5 V for a module of four photosupercapacitors connected in series) in less than 5 s is attained even under weak illumination conditions, with an outstanding peak overall efficiency of 11.8%. These results show high potential toward the development of photorechargeable and decentralized power sources for deployed smart electronic devices. [ABSTRACT FROM AUTHOR]