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In this paper, a decoder for Low-Density ParityCheck codes is proposed. The system employs a genetic algorithm aided by syndrome weight selection and distance logic. Genetic algorithms were chosen due to their capability to perform heuristic searches using evolution-based convergence while also exploring wide spaces. The paper has considered the performance of the decoder over an impulse noise channel, typical to power line communications, and a type of disturbance commonly found in most transmission mediums and devices. The resulting system is shown to perform as well as the standard sum-product decoder, with the additional advantage of not requiring knowledge of the channel information (noise type or power). A parallel decoding topology is proposed, where error rate performance can be improved by the addition of concurrent decoders. Furthermore, this scheme allows for genetic algorithm complexity to be reduced, as the addition of parallel blocks can compensate the individual loss in error rate performance.

In this paper, we implement the Successive Cancellation SC decoding algorithm for Polar Codes by using Euclidean distance estimates as the metric of the algorithm. This implies conversion of the classic statistical recursive expressions of the SC decoder into a suitable form, adapting them to the proposed metric, and properly expressing the initialization values for this metric. This leads to a simplified version of the logarithmic SC decoder, which offers the advantage that the algorithm can be directly initialised with the values of the received channel samples. Simulations of the BER performance of the SC decoder, using both the classic statistical metrics, and the proposed Euclidean distance metric, show that there is no significant loss in BER performance for the proposed method in comparison with the classic implementation. Calculations are simplified at the initialization step of the algorithm, since neither is there a need to know the noise power variance of the channel, nor to perform complex and costly mathematical operations like exponentiations, quotients and products at that step. This complexity reduction is especially important for practical implementations of the SC decoding algorithm in programmable logic technology like Field Programmable Gate Arrays FPGAs.