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An 8.8-mW, low-noise, 40.5-GHz frequency synthesizer is proposed. The synthesizer system consists of a subsampling phase-locked loop (SSPLL) with 100-MHz crystal reference, a 900-MHz high-frequency-reference (HFR) PLL, and a novel subsampling lock detector (SSLD). The SSLD keeps monitoring the locking status of the SSPLL by sampling the SSPLL output with the HFR 900-MHz reference and automatically controls the SSPLL for frequency acquisition if it loses lock or locks to a wrong 100-MHz harmonic. This is done without using a power-consuming divider-based frequency-locked loop in conventional SSPLL. Due to the relatively low-frequency operation and moderate noise requirement of HFR, as well as the low-power SSLD, the proposed system achieves low power consumption and jitter simultaneously. The measured results show 8.8-mW power consumption and 228-fs rms jitter with in-band and out-band phase noises of −96.6 dBc/Hz at a 1-MHz offset and −106.9 dBc/Hz at a 10-MHz offset, respectively. [ABSTRACT FROM AUTHOR]

In this paper, the challenges of designing distributed amplifiers at frequencies close to $f_{\text {max}}$ of transistors are tackled. By using bandpass transmission lines, the maximum operation frequency of the distributed amplifier is increased compared to low-pass transmission lines. Moreover, a novel gain-boosted cascode structure with an internal feedback is employed to cancel a part of the loss in the input line and boost the bandwidth and the highest operation frequency of the amplifier. The proposed amplifier operates up to frequencies as high as 0.67 $f_{\text {max}}$ of the transistors. Two proof-of-concept prototypes are fabricated in a 0.13- $\mu \text{m}$ SiGe process with $f_{\text {max}}$ of 210 GHz. The first prototype shows an average gain of 14.4 dB from 52 to 142 GHz (bandwidth of 90 GHz at the center frequency of 97 GHz) while the second one achieves an average gain of 18.6 dB from 48 to 135 GHz (bandwidth of 87 GHz at the center frequency of 91.5 GHz). [ABSTRACT FROM AUTHOR]

In this paper, we present a new architecture for implementation of millimeter-wave (mm-wave) and terahertz (THz) radiator arrays based on standing-wave properties. This structure is a continuous distributed coherent array that avoids lossy and parasitic coupling networks. Moreover, it can be scaled simply by extending the size of the structure and replicating the unit cell. The absence of coupling parasitics in addition to the unique characteristics of standing waves allows us to extend the tuning range without using varactors. The 0.34-THz four-element radiator array is designed and fabricated in a 130-nm SiGe BiCMOS process using microstrip transmission lines as the standing-wave mediums and on-chip patch antennas to radiate the desired fourth harmonic of the oscillation. The circuit was measured with no post processing or silicon lens and has 5.9% frequency tuning range (332.5–352.8 GHz) with less than 6-dB output power variation across the band. It consumes 425-mW power from 1.8-V supply and the radiated power is −10.5 dBm at center frequency with −98.2 dBc/Hz phase noise at 10-MHz offset frequency. [ABSTRACT FROM PUBLISHER]

Based on time-variant behavior of metal-oxide–semiconductor field-effect transistors in large-signal operations, harmonic translations and their mutual effects are analyzed. Large amplitudes at terminal voltages of these transistors push them into different regions of operation. In this paper, harmonic translations are derived as a result of such changes in operation region of transistors. Operation in triode region for a portion of oscillation cycle results in iterative harmonic translations between fundamental frequency and second harmonic. They boost each other constructively for significantly stronger oscillation, more second harmonic output power, and enhanced dc-to-RF efficiency. Based on this analysis, a 215-GHz signal source, implemented in a TSMC 65-nm CMOS LP is presented. The proposed oscillator achieves a maximum output power of 5.6 dBm and a dc-to-RF efficiency of 4.6%. The measured phase noise is −94.6 dBc/Hz at 1-MHz offset. The proposed oscillator occupies only 0.08 mm2 of chip area. [ABSTRACT FROM PUBLISHER]

A highly efficient push–push voltage-controlled oscillator (VCO) with a new inductive frequency tuning topology for (sub) terahertz frequencies is presented. The tuning technique is based on a variable inductance seen at the emitter node of a base-degenerated transistor. The variable inductor exhibits high quality factor and high tuning range due to the tunable transistor transconductance via bias current. Fabricated in a 0.13-\mu\m SiGe BiCMOS process, the VCO achieves a tuning range of 3.5% and an output power of -7.2 dBm at 201.5 GHz. The dc power consumption of the VCO is 30 mW, resulting in a high dc to RF power efficiency of 0.6% and a figure of merit (FoMT) of -165, which is the highest FoM for any silicon-based VCO reported to date at this frequency range. To demonstrate the functionality of the tuning technique, three VCO prototypes at different oscillation frequencies, including one operating in the 222.7–229-GHz range, are implemented and measured. [ABSTRACT FROM PUBLISHER]

A 2-D electrical filter is introduced that is compatible with today's conventional integrated circuit processes. The rich 2-D propagation properties of the medium are used to introduce a novel high quality factor filter called an electrical prism. The pro- posed filter shows a quality factor much larger than the quality factor of the individual components at high millimeter-wave and terahertz frequencies. This structure also provides a negative effective index in a low-pass LC lattice. Based on this idea, we show filters with quality factors of 130 at 230 GHz and 420 at 460 GHz consisting of elements with the quality factor of 10 and 20, respectively. The effect of component loss on the filter quality factor is discussed in this paper. The negative effective index and the filter behavior of the lattice is verified by measuring a prototype on a CMOS process at 32-40 GHz. There is good agreement among the theory, simulation, and experimental results. [ABSTRACT FROM AUTHOR]

In this paper, we study an electrical nonlinear medium consisting of voltage-dependent capacitors and inductors to generate sharp pulses from a lower frequency sinusoid. First, we analyze the optimum conditions for maximum harmonic generation in a uniform nonlinear line. Next, we extend the nonlinear line to a two-dimensional nonlinear lattice that is compatible with CMOS technology. Compared with the nonlinear line, the lattice relies on spatial power combining, higher cut-off frequency, and nonlinear wave interaction to enhance the pulse amplitude and sharpness. To show the feasibility of this method, we implement the first CMOS nonlinear lattice in a 0.13-\mum CMOS process, and successfully demonstrate 2.7-Vpp, 6.3-ps pulses from a 22-GHz input signal. [ABSTRACT FROM AUTHOR]

A new two-element phase-locked loop (PLL)-coupled array for the implementation of millimeter-wave (mm-wave) and subterahertz (sub-THz) phased arrays is presented. This architecture avoids using lossy phase shifter to create the required phase shift between the adjacent elements in a phased-array system. The required phase shift is generated by utilizing a dual nested loop PLL. The two PLL loops work together to stabilize the frequency and create the required phase shift. Moreover, it can be scaled simply by adding more unit cells to the architecture. A 112–121-GHz two-element phased array is designed and fabricated in a standard 65-nm CMOS process. It consumes 147-mW power and provides a phase shift of 46.7° ranging from 58.53° to 105.2° at 117 GHz. [ABSTRACT FROM AUTHOR]

After completing two years as Editors-in-Chief of this Transactions, it is a good time to say a few words on how this journal is accomplishing its mission of serving the microwave community. [ABSTRACT FROM AUTHOR]