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Abstract This paper presents a novel filtering algorithm for the resolver position signal based on recursive least squares (RLS) and phase‐locked loop (PLL). The proposed RLS‐PLL‐based algorithm designs a harmonic iterative estimation and elimination mechanism, which can accurately estimate and eliminate the specified harmonic contained in the resolver online and obtain an ideal reconstructed position signal. The convergence analysis, parameter design and pseudo code of the proposed algorithm are all provided. The advantage of the presented method mainly lies in that it has excellent position signal filtering performance in the entire operating condition, including low speed, high speed, steady state, and dynamic. Experimental results demonstrate that compared to the results achieved with the conventional look‐up table (LUT) method and the advanced type‐III angle tracking observe (ATO), the proposed RLS‐PLL‐based algorithm has improved filtering performance. Under some typical operating conditions, the harmonic content of the position signal reconstructed by the new method is reduced by an order of magnitude.

Abstract This paper introduces a novel cascading frequency regulation scheme (CFRS) for VSC‐HVDC to provide strong support for the connected weak AC grid without phase‐locked loop and remote‐communication considering the cost‐effective property. The proposed CFRS utilises a DC voltage synchronisation control to enable the self‐synchronisation of VSC‐HVDC without phase‐locked loop, while the corresponding inertia response can be exerted via utilising the stored HVDC capacitor energy. Meanwhile, the DC voltage acts as the reflection of system frequency, enabling the coordination between two‐end VSC stations without communication. More importantly, to fully utilise the VSC‐HVDC potentials, the CFRS that sequentially activates HVDC capacitor and primary frequency control is implemented so that the energy loss and the detrimental control impacts on the sending‐end systems can be minimised while making sure the requirement of system frequency support. Analytical derivations have been done to evaluate the contribution of the proposed CFRS to system frequency regulation. Furthermore, the effectiveness of the proposed scheme has been well validated in PSCAD/EMTDC under several power system contingencies by fully comparing with existing control schemes. The proposed CFRS stands out by the reduced complexity of the control structure, the robustness for connecting the very weak AC grid and the fast frequency regulation ability with consideration of cost‐effective property.

Abstract Having a robust and accurate grid synchronization unit for distributed generators (DGs) has been accentuated due to rapidly growing integration of inverter‐based DGs to the autonomous microgrids. Although most of the synchronization methods are based on the phased locked loops (PLL) technique, digital filters could result in more salient dynamic performance in non‐ideal sinusoidal situations. This paper presents a novel digital filter as a grid synchronization method that overcomes the flaws of conventional PLLs under harmonic distorted and unbalanced cases as well as large delay of window‐based digital filters. For the sake of computational advantages, the proposed method is executed in two distinct offline and online stages. In the offline stage, the second‐order Taylor series expansion approximation of the bandpass oscillatory signal calculates the state‐transition matrices and state vectors. Then, by applying the concept of Kalman filter, the state vectors are updated in the online calculation section much easier and faster compared to all‐online approach. Compared to the existing methods, the proposed method generates a dynamic response with less settling time, more accuracy, and immunity against harmonic distortion, imbalances, and noise.

Abstract As an essential apparatus in resonance grounding systems, the arc suppression coil is widely used in rejecting the single‐line‐to‐ground (SLG) fault of distribution networks. However, the resistive ground‐fault current cannot be compensated by an arc suppression coil (ASC). As a novel active arc suppression device, the hybrid flexible arc suppression device (HFASD) composed of ASC and flexible arc suppression device (FASD) can eliminate the capacitive component of ground‐fault current and the resistive component of ground‐fault current. After the SLG fault occurs, the FASD from stand‐alone mode to grid‐connected mode may lead to switching transients, affecting the stability of distribution networks. The soft grid connection (SGC) strategy can achieve low or without transient response during the grid synchronization of FASD to the grid. Thus, the HFASD based on SGC strategy and segmented proportional‐integral‐differential (SPID) and second‐order generalized integrator phase‐locked loop (SOGI‐PLL) control method is proposed for rejecting the current and voltage overshoot responses during the process of grid synchronization of FASD in this paper. Simulation and experimental results verify the effectiveness of the proposed method, and the benefit of the proposed method is indicated in comparison with the non‐SGC (NSGC) strategy.

Abstract Sorted QR decomposition (SQRD) has been extensively adopted for various multiple‐input‐multiple‐output (MIMO) detectors, in which the sorting process incurs severe latency when it comes to larger‐scale MIMO situations. This paper proposes a group‐SQRD (GSQRD) algorithm to alleviate the latency problem of general SQRD architectures for larger‐scale MIMO systems. Via predictively sorting a group of 4 columns at one stage, the GSQRD could eliminate the processing latency by 41% for decomposing 16×16 complex‐valued matrices. Additionally, this percentage even rises up to 68% for decomposing 128×128 matrices. To analyse the side effects, the GSQRD is applied in various MIMO detectors in a simulation link, which exhibits a negligible performance degradation for MIMO detection. Moreover, GSQRD is a hardware‐friendly algorithm because the division and square root operations in GSQRD are converted to multiplications for simplifying the hardware implementation. Based on this algorithm, two corresponding hardware architectures, which contains 2 and 4 columns respectively in a sorting group, are also implemented with 65‐nm CMOS technology. These architectures can work at 513 MHz to decompose 16×16 complex‐valued matrices. The processing latencies are respectively 0.32 and 0.26 μs, superior to the state‐of‐art designs.

Abstract Grid integration of inverters using renewable sources of energy is essential for providing a secure and clean source of power supply. Many techniques developed so far control the grid current to realize the regulation of power flow to the power grid. However, implementation of communication assisted synchronization methods for single‐phase full‐bridge inverters is not found to be discussed in the literature. The focus of this research is to conceptualize, simulate, and implement two control techniques, namely Phase Shift Control (PSC) and Controller Area Network Assisted Proportional Resonant Control (CANAPRC) for single‐phase inverters. In the PSC method, the inverter injects the desired real power into the grid by controlling the phase angle between converter and grid voltages. A low complexity synchronization procedure was adopted using single‐phase PLL to generate a reference voltage signal using the PSC method. In contrast, the CANAPRC method outputs a current reference created by the resonant controller using a communication network. The inverter can pump the required real and reactive power to the grid with reduced harmonics, enhanced power‐sharing and transient stability using the two strategies. Simulations in MATLAB R2016a analyze the two models out effectively. Prototype models validate the proposed control strategies.

Abstract Traditional permanent magnet synchronous generator (PMSG)‐based wind turbine (WT) normally utilises phase lock loop (PLL) for obtaining accurate phase angle of AC grid to make sure of maximum power point tracking (MPPT). However, a weak AC system with a low short circuit ratio (SCR) and high control bandwidth of PLL might have impaired effects on the stability of the system. To overcome these, a novel power synchronous control of PMSG‐based WT with grid forming ability of PMSG for integrating very weak AC system is first proposed in this study. Grid‐side converter (GSC) of PMSG emulates the inertia response of synchronous generator (SG) by artificially coupling the DC‐link voltage with the grid frequency based on the certain droop property, while the converter voltage magnitude is regulated according to DC‐link voltage deviation by controlling the modulation index of GSC. This novel scheme can realise the grid synchronisation without PLL by mimicking the natural characteristic of SG. Small‐signal analysis of the proposed scheme indicates the DC‐link capacitor energy can be exerted for system inertia support during system disturbances, while the system damping can be provided by spontaneously alternating converter voltage magnitude. More importantly, MPPT property of PMSG is not compromised while providing inertia and damping for the system, and the related inertia and damping coefficient of WT with the proposed control can be easily tuned for satisfying the system requirement. Non‐linear simulations of one PMSG connected with one large SG considering a sudden change of active power reference and variable wind speeds have been studied to verify the effectiveness of the proposed grid‐forming control.

Abstract Design of a low cost Schottky diode based single‐balanced mixer (SBM) in full V‐band with an ultra‐wide intermediate frequency (IF) bandwidth is presented here. By loading multiple quarter‐wavelength short‐ended stubs at both radio frequency (RF) and local oscillator (LO) frequency on the multistage stepped impedance matching networks, a broadband grounding circuit is provided for IF signal and thus output power nulls are eliminated over an ultra‐wide IF band. The hybrid network is constructed by a 3 dB branch coupler and a 90‐degree delay line, which enables the required balanced outputs with equal amplitude and 180‐degree phase difference. A prototype of the SBM is designed, fabricated and tested. Measured results demonstrate that, for RF and LO frequency over entire V‐band, the mixer has a conversion loss from 6.8 to 11.4 dB with an ultra‐wide IF range of 0.01–22 GHz.

Abstract This study proposes a variable boundary‐layer full‐order sliding‐mode observer (FOSMO) with a fuzzy proportional plus integral (PI) phase‐locked loop (PLL) for the sensorless control of a permanent‐magnet synchronous machine (PMSM). The sigmoid switching function‐based FOSMO, which includes feedback speed information, is presented and considered as the conventional method. To address the contradiction between the convergence performance and the chatter‐reduction ability of the sliding‐mode control, a fuzzy logic controller (FLC) is introduced to adjust the boundary‐layer thickness according to the estimation error. Furthermore, a real‐time parameter tuning module is integrated into the PI regulator of the conventional PLL to adjust its noise bandwidth. Hence, adverse effects of disturbance and external noise, especially under transient operations, can be eliminated. An overall PMSM sensorless field‐oriented control scheme incorporating the proposed method is designed, and the corresponding experimental platform is constructed. Several groups of comparative experiments reveal that system chatters are largely reduced using the proposed method under both of the high‐ and low‐speed running conditions and the dynamic anti‐interference performance can also be significantly improved under load and speed disturbances. Therefore, the feasibility and effectiveness of the proposed variable boundary‐layer FOSMO + fuzzy‐PI PLL method are validated.

Abstract Synchronverter (SV) control has emerged as a popular method for distributed energy resources (DERs), to emulate response of a synchronous generator. In this work, a simple gradient descent based pre‐synchronization control for SV scheme is proposed that varies the reference frequency in SV control alone. Thus, local load connection to DER can remain intact during synchronization with proposed pre‐synchronization method, unlike virtual current based methods. Normally, phase‐locked loop used for synchronization purpose, uses a first order loop filter such as a PI controller. In the proposed pre‐synchronization control, the inherent low pass filter of SV scheme itself is used as a loop filter. Transient response analysis is presented in this work, based on small signal transfer functions derived from the proposed method. From the theoretical analysis of proposed pre‐synchronisation control, design of the parameters is presented. Thus, there is no trial and error basis for parameters tuning in the proposed method, as compared to virtual current based methods. Validation of proposed pre‐synchronisation control through experiments are presented for all initial conditions. The transient response analysis, effectiveness of proposed method during local load changes and grid integration are verified by experimental results.

Abstract The parallel analogue to digital converter (ADC) structure with mixers such as digital bandwidth‐interleaving ADC (DBI‐ADC) is a practical structure for realising the wideband data acquisition system. The system calibration relies on accurate system frequency response measurement. However, existing measurement methods require complex synchronous circuits or are susceptible to noise. This paper proposes a new frequency response measurement method, which can be realised by a simple circuit without any synchronisation measures. At the same time, frequency response measurement can ensure sufficient accuracy. Simulation and experiment results show that the method is effective and feasible.

Abstract This paper presents a millimeter‐wave (mm‐wave) V‐band mixer. The source‐driven transformer‐coupled up‐converter topology can alleviate the local oscillator (LO) leakage problem. The proposed V‐band up‐converter has been implemented on 65 nm CMOS technology. The experimental results show that the LO leakage level can be reduced to –43.1 dB. The up‐converter occupies 0.11 mm2 in area excluding signal pads.

Abstract This paper presents a high conversion gain and highly linearised up‐conversion mixer designed in 65 nm CMOS process, which translates intermediate frequency of 2.4 GHz and local oscillator frequency of 21.6–24 GHz in radio frequency. In the proposed mixer, the tranconductance stage consists of a common source route with neutralisation technique and dual capacitive cross coupled‐common gate route to achieve high linearity and stability. In addition, it also includes dual negative resistance switches with improved inter‐stage matching network to enhance the conversion gain and to decrease the noise figure. The mixer achieves the conversion gain of 4.7 dB, the measured output 1‐dB compression point of 0.41 dBm and noise figure of 3.8 dB at 24 GHz. In an automotive radar application, the proposed mixer showed a high conversion gain, an excellent output 1‐dB and a low noise figure with power consumption of approximately 5.2 mW at a 1.2 V supply.