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In the quantum mechanical simulation of exploratory semiconductor devices, continuum methods based on a k ⋅ p/envelope function model have the potential to significantly reduce the computational burden compared to prevalent atomistic methods. However, full-zone k ⋅ p/envelope function simulation approaches are scarce and existing implementations are not self-consistent with the calculation of the electrostatic potential due to the lack of a stable procedure and a proper normalization of the multi-band envelope functions. Here, we therefore present a self-consistent procedure based on a full-zone spectral k ⋅ p/envelope function band structure model. First, we develop a proper normalization for the multi-band envelope functions in the presence of transmitting boundary conditions. This enables the calculation of the free carrier densities. Next, we construct a procedure to obtain self-consistency of the carrier densities with the electrostatic potential. This procedure is stabilized with an adaptive scheme that relies on the solution of Poisson's equation in the Gummel form, combined with successive underrelaxation. Finally, we apply our procedure to homostructure In 0.53 Ga 0.47 As tunnel field-effect transistors (TFETs) and staggered heterostructure GaAs 0.5 Sb 0.5 /In 0.53 Ga 0.47 As TFETs and show the importance of self-consistency on the device predictions for scaled dimensions. [ABSTRACT FROM AUTHOR]

In this work, we study oxide defects in various III-V/high-k metal-oxide-semiconductor (MOS) stacks. We show that the choice of a given starting measurement voltage with respect to the MOS flat-band voltage affects the observed capacitance-voltage hysteresis. We discuss how this behavior can be used to study the distribution of oxide defect levels. With the help of comprehensive experimental data, we show that Al2O3 and HfO2 have different hysteresis characteristics related to different oxide defect distributions. In case of an Al2O3/HfO2 bilayer stack with Al2O3 on the channel side (interfacial layer, IL), as the IL thickness reduces from 3 nm to 0 nm, the hysteresis behavior switches from the typical Al2O3 behavior to the one corresponding to HfO2. We link the characteristic behavior of two dielectrics to the defect level distributions inside their respective band-gaps through a simple energy-driven charging model. Based on the experimental data and simulation results, we show that Al2O3, despite having a lower peak defect density as compared to HfO2, shows a very wide, almost continuous distribution of defect levels across and around the InGaAs channel energy band gap. These results explain the often reported poor reliability of III-V devices with Al2O3-based gate stacks. [ABSTRACT FROM AUTHOR]

The conduction and valence band offsets between a strained silicon-germanium layer and a silicongermanium substrate are reported for arbitrary substrate and channel crystal orientations. The offsets are calculated both for the case of biaxial stress, corresponding approximately to the stress state of a thin strained channel in a planar field-effect transistor (FET), and for uniaxial stress, which is the approximate stress state for strained channels in a FinFET configuration. Significant orientation dependence is found for the conduction band offset, overall leading to the strongest electron quantum confinement in biaxial-tensile stressed channels on {100}-oriented substrates, and uniaxialtensile stressed channels in the ⟨100⟩ and ⟨101⟩ directions. For biaxially stressed layers on {111} substrates, the conduction band offset is significantly smaller than for {100} or {110} directions. For the valence band offset, the dependence on crystal orientation is found to be small. [ABSTRACT FROM AUTHOR]

Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET. [ABSTRACT FROM AUTHOR]

Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET. [ABSTRACT FROM AUTHOR]

In this article, we explore different device and standard cell architectures for scaling the Germanium fin field-effect transistor (FinFET) and nanosheet (NS) at the sub-5-nm node. It is demonstrated that the Germanium device provides approximately 70% improvement in drive current and $3.4\times $ less device resistance. The main concern for Germanium devices remains the high leakage current due to the gate-induced drain leakage, which limits their usage to high-speed applications. Overall, Germanium devices require fewer boosters than silicon to scale beyond the 5-nm node. Contact resistivity is found to be a critical knob for Germanium and it can be relaxed to 3e $- 9\,\,\Omega $ -cm2 to meet the power and performance targets for the sub-5-nm node. Moving to the NS helps in relaxing this constraint further. [ABSTRACT FROM AUTHOR]

We examine the power-performance variability of a projected sub-5-nm GaAsSb/InGaAs vertical tunnel FET considering various process control tolerances in the state-of-the-art device integration and propose countermeasures in device design. Nominal and three-sigma-corner device characteristics generated in quantum-mechanical/TCAD simulations are used to calibrate a semiempirical compact model, based on which the nominal and variability-inclusive energy-delay landscapes are extracted from ring-oscillator circuit simulations at sub-500-mV supply voltages. Variations in four parameters are identified as of major impact on the worst-case speed loss and iso-speed energy penalty: dopant pocket thickness, gate work function, hetero-band offset, and body thickness (in descending order). Variability-resilient device options are explored against pocket thickness variation, including: 1) pocket desensitization with increased thickness and reduced doping concentration and 2) broken-gap tunnel FET with a negative effective band gap. Reengineered devices achieve $< 18\times $ speed loss and $< 3\times $ energy penalty for (0.1–1) ns gate delay with respect to the nominal corner. [ABSTRACT FROM AUTHOR]

2-D material FETs hold the promise of excellent gate control, but the impact of nonidealities on their performance remains poorly understood. This is because of the need, so far, to use computationally intensive nonequilibrium Green’s function (NEGF) simulations. Here, we therefore use a semiclassical model to investigate the role of nonidealities in the scaling of back-gated (BG) and top-gated (TG) monolayer MoS2 FETs. We verify the electrostatics and transport of the semiclassical model with density functional theory-based NEGF simulations and calibrate nonidealities, such as interface traps (${D}_{\textsf {it}}$) and Schottky contact barrier height ($\phi _{\textsf {SB}}$) to experimental monolayer and bilayer MoS2 FETs. We find that among the nonidealities, ${D}_{\textsf {it}}$ has the strongest subthreshold swing impact with 70 mV/dec obtainable in BG devices for a ${D}_{\textsf {it}}$ of $5\times {10}^{11}$ cm−2eV $^{-1}$ , an equivalent oxide thickness (EOT) of 1 nm, and a channel length (${L}_{\textsf {ch}}$) of 5 nm. For scaled EOT, $\phi _{\textsf {SB}}$ only strongly impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ for the TG case, as the overlapping gate thins the Schottky barriers in the BG case. We show in TG devices that a spacer of only 5 nm results in a 1000-fold drop in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ because of the nonidealities. We propose positive spacer oxide charge as a solution and show that a charge density of above 1013 cm−2 is required to fully recover the device performance. [ABSTRACT FROM AUTHOR]

In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling. [ABSTRACT FROM PUBLISHER]

Most experimental reports of tunneling field-effect transistors show defect-related performance degradation. Charging of oxide traps causes Fermi-level pinning, and Shockley–Read–Hall (SRH)/trap-assisted tunneling (TAT) cause unwanted leakage current. In this paper, we study these degradation mechanisms using the pulsed I-V technique. Our simulations show pulsed I-V can fully suppress oxide trap charging, unlike SRH and TAT. We discuss several circuit-related pitfalls, and we demonstrate improved transfer characteristics by suppressing oxide trap charging using cryogenic pulsed I-V. [ABSTRACT FROM PUBLISHER]

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSix) and achieve ultralow contact resistivity ( \rho c ) of (1.3 – 1.5) \times 10^-9 ~\Omega \cdot \text cm^2 on Si:P. This PCAI + TiSix technique utilizes light amorphization (low-energy implantation), thin Ti and TiSix film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSix-induced \rho c reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced \rho c variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low \rho c is strongly correlated with the formation of interfacial TiSix crystallites between amorphous TiSi alloy and Si. [ABSTRACT FROM PUBLISHER]

In this paper, we have developed a straightforward MOS admittance-based technique for defect density extraction, utilizing analytical equations for MOS capacitors with border traps (BTs). We show that these equations can provide an efficient technique to obtain the BT density directly from the measured data without any requirement of numerically involved techniques. This is demonstrated by applying the methodology on measured C–V data from Al2O3- and HfO2-based MOSCAPs. The extracted densities show less than 5% difference from the values extracted using the fitting-based methodology used in previous reports. We show that, due to the analytical nature of these equations, they can be used to understand the impact of each defect parameter on the admittance. We extensively prove the applicability of the analytical solution for a very wide range of parameter values. In addition, we lay out a methodology for defect density extraction, which can be easily automated for the characterization of large scale data sets of high-k dielectrics on III–V MOS devices. [ABSTRACT FROM PUBLISHER]

The effective bandgap for heterojunction band-to-band tunneling ( $ {{E}}_{{\text {g,eff}}}$ ) is a crucial design parameter for a heterojunction tunneling FET (TFET). However, there is significant uncertainty on $ {{E}}_{{\text {g,eff}}}$ , especially for In0.53Ga0.47As/ GaAs0.5Sb0.5. This makes the prediction of TFET performance difficult. We calibrate $ {{E}}_{{\text {g,eff}}}$ by fabricating heterojunction p+/i/n+ diodes, comparing the simulated and the measured current–voltage and capacitance–voltage curves, while taking $ {{E}}_{{\text {g,eff}}}$ as a fitting parameter. Our calibration significantly reduces the uncertainty on $ {{E}}_{{\text {g,eff}}}$ compared with the range found in the literature. The comparison with the previous work on highly doped heterojunction diodes suggests that dopant-dependent bandgap narrowing reduces $ {{E}}_{{\text {g,eff}}}$ and therefore significantly impacts the performance of highly doped TFET. [ABSTRACT FROM AUTHOR]

The electrostatic and leakage effects of extended defects on Si and Ge MOSFETs are investigated. A technology computer-aided design model of extended defects is developed based upon measured device electrical properties. A single extended defect is introduced into simulated 2-D planar and 3-D FinFET structures. It is found that a 2-D extended defect is a source of variability in planar transistors, with the electrical effects depending on its position along the channel. A 2-D extended defect increases the threshold voltage and subthreshold swing when it is in the channel and increases the leakage current when it is in the drain. The dislocation effect on transistor characteristics increases with decreasing transistor width. The effect is less pronounced in FinFETs due to the well-controlled electrostatics and the small dislocation volume. [ABSTRACT FROM PUBLISHER]

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow. [ABSTRACT FROM AUTHOR]

In this work, we discuss how the position of the flat band voltage with respect to the starting voltage of the C-V measurement sweep can influence the estimation of the hysteresis in high-k/InGaAs MOS devices. We show that, with the support of experimental data and conceptual oxide defect band calculations, the interpretation and subsequent parameter extraction from flat-band voltage shifts observed in III-V MOS devices is more complex as compared to Si gate stacks. It is demonstrated that such complication arises due to the wider distribution of defect levels in the dielectric band gap in the case of InGaAs/high-k stack as compared to standard Si/SiO2/HfO2MOS. In particular, for Al2O3 deposited on InGaAs, two wide, partially overlapping oxide defect bands are identified, centered ~1.5 eV and ~0.5 eV above and below the channel conduction band, respectively. Such defect levels are expected to affect the device operation and reliability. [ABSTRACT FROM AUTHOR]

A simple analytical low-field electron mobility model to be employed for technology computer-aided design of thin-body MOSFETs based on III-V compound semiconductors is presented. The scattering sources accounted for in the model are Coulomb centers, lattice vibrations (i.e., phonons), and surface roughness. The dependence of the thin-body effective thickness on the transverse electric field is calculated through 1-D Schrödinger–Poisson numerical simulations and is introduced in the model by means of an appropriate analytical function. Then, the free-electron density distribution is determined by considering both quantization effects and oxide–semiconductor interface traps. The model is calibrated on the experimental data collected on In0.53Ga0.47As-on-InP thin-body MOSFETs featuring body thicknesses as low as 5 nm. In particular, the model accurately reproduces CG – V\mathrm{ GS} characteristics, effective mobility against inversion layer charge plots, and I\mathrm{ DS} – V\mathrm{ GS} curves at low V\mathrm{ DS} . [ABSTRACT FROM AUTHOR]

Silicon-Germanium (SiGe), used to boost pFET performance and enhance the properties of high- k metal gate devices, is grown by selective epitaxy on silicon. Since device parameters depend critically on the deposited SiGe thickness, we apply several advanced techniques to control deposition. Feedback and feed-forward of growth rate data is used to control deposition tools. We also apply a pattern-density based predictive growth rate, since pattern density effects cause the deposited thickness to be different across different product chips under otherwise identical conditions. We use run to run analysis of deposition data and a feature of the deposition tool to tune cross wafer deposition rates for optimized uniformity. Finally, we consider local (within chip) growth rate variation. We demonstrate that the deposited layer thickness is in acceptable range for device performance across a product chip. [ABSTRACT FROM AUTHOR]

In this paper, we present results of a study on border trap capture/emission (C/E) process and its effect on small signal admittance of III–V devices. A MOS admittance model using a non-radiative multi-phonon phenomenon as the basis of the border trap capture/emission process is developed and utilized to investigate the effect of parameters like temperature, gate voltage, oxide thickness and trap distribution on capture/emission process. The simulation results are found to match closely with experimentally observed temperature, voltage and dielectric thickness dependencies in experimental admittance data. [ABSTRACT FROM AUTHOR]

The effective bandgap is a crucial design parameter of heterojunction tunneling field-effect transistors. In this letter, we demonstrate a method to measure the effective bandgap directly from the band-to-band tunneling current of a heterojunction Esaki diode, of which we only require knowledge of the electrostatic potential profile. The method is based on a characteristic exponentially increasing current with forward bias, caused by sharp energy filtering at cryogenic temperature. We apply this method experimentally to a n+In0.53Ga0.47As/pGaAs0.5Sb0.5 Esaki diode and define requirements to apply it to other heterojunctions. [ABSTRACT FROM AUTHOR]

The gate-stack quality of planar MOSFETs fabricated in Ge-on-Si substrates and passivated by a GeOx interfacial layer is evaluated by low-frequency noise analysis. It is shown that for both n- and p-channel transistors predominantly 1/ f^\gamma noise ( $\gamma \sim 1$ ) has been observed, which originates from number and correlated mobility fluctuations. The oxide trap density and mobility scattering coefficient derived from the input-referred voltage noise power spectral density are demonstrated to be significantly higher for nMOSFETs than for pMOSFETs with the same gate-stack, which explains the low electron mobility. [ABSTRACT FROM PUBLISHER]

Complementary logic based on tunnel field-effect transistors (TFETs) would drastically reduce power consumption thanks to the TFET's potential to obtain a sub-60mV/dec subthreshold swing (SS). However, p-type TFETs typically do not meet the performance of n-TFETs for direct bandgap III-V configurations. The p-TFET SS stays well above 60mV/dec, due to the low density of states in the conduction band. We therefore propose a source configuration in which a highly doped region is maintained only near the tunnel junction. In the remaining part of the source, the hot carriers in the exponential tail of the Fermi-Dirac distribution are blocked by reducing the doping degeneracy, either with a source section with a lower doping concentration or with a heterostructure. We apply this concept to n-p-i-p configurations consisting of In0.53Ga0.47As and an InP-InAs heterostructure. 15-band quantum mechanical simulations predict that the configurations with our source design can obtain sub-60mV/dec SS, with an on-current comparable to the conventional source design. [ABSTRACT FROM AUTHOR]

Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V \(_{\rm TH}\) shifts and fluctuations, which are even visible during the I \(_{D}\) –V \(_{G}\) tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodology for random telegraph noise assessment capable of determining the capture and emission times \(\tau _{c}\) and \(\tau _{e}\) , and their impact on V \(_{\rm TH}\) as a function of gate voltage V \(_{G}\) and temperature T. This information is crucial for developing circuit simulators that assess the impact of single traps in the full V \(_{G}\) swing and operational temperatures. [ABSTRACT FROM PUBLISHER]