12 results on '"Miyanami, Y."'
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2. Systematic study of interfacial reactions induced by metal electrodes in high-k/InGaAs gate stacks
3. Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process
4. Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates
5. A planar transistor for the 32-nm node and beyond with an ultra-shallow junction fabricated using in-situ doped selective Si epitaxy
6. A Promising Planar Transistor with in-situ Doped Selective Si Epitaxy Technology (GORES MOSFET) for 32nm node and beyond
7. Scalable eSiGe S/D Technology with Less Layout Dependence for 45-nm Generation
8. High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates
9. A Raised Source/Drain Extension pFET on Si (110) Realized by In-situ Doped Selective Epitaxy Technology
10. Gate Overlapped Raised Extension Structure (GORES) MOSFET by Using In-situ Doped Selective Si Epitaxy
11. A Raised Source/Drain Extension pFET on Si [110] Realized by In-situ Doped Selective Epitaxy Technology.
12. Scalable eSiGe S/D Technology with Less Layout Dependence for 45-nm Generation.
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