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We describe a rapid and simple method to create Ag nanostructures by using direct mechanical patterning of ionic Ag ink coating under gentle pressure, then thermal annealing to reduce the ionic Ag ink to a metallic Ag layer. The ionic liquid-phase Ag coating is easily obtained by spin-coating ionic Ag ink that has appropriate Ag concentration and can be either printed or imprinted on the desired substrate by using a soft elastomer patterning mold, then reduced to the Ag nanostructure by subsequent thermal annealing. More specifically, we present two methods: transfer printing and soft nanoimprinting. In transfer printing, the ionic Ag ink is first inked onto the elastomer mold which then contacts the target substrate to transfer the Ag nanopattern. In soft nanoimprinting, the elastomer mold conducts soft imprinting to engineer the ionic Ag ink coating to the Ag nanostructure. We systematically investigate the optimal patterning conditions by controlling the initial Ag ink concentration and the coating, printing, imprinting, and annealing conditions, to derive Ag architecture that has tunable photonic functionality. As an example, we demonstrate polarization-sensitive reflective color filters that exploit shape-tunable Ag nanostructures fabricated by soft nanoimprinting using a controllably-stretched elastomer mold.

Hyocheong Chae,1,2,&ast; Hongmin Chu,1,3,&ast; Junghun Lee,1 Hagdong Kim,1 Dongha Kim,1 Sebong Park,1 Kwanghwan Lim,1 Minsu Jeong,1 Kyungho Kang,1 Gyeongchan Kim,1 Joo Hyun Lee,1 Sehun Jung,1 Jaehyo Kim,4 Yongjoo Kim,5 Myungseok Ryu1,6 On behalf of Korean Medical Society of Acupotomology KM Doctors Group1Departmental Research Committee, Korean Medical Society of Acupotomology, Seoul, Republic of Korea; 2Sunyujae Korean Medicine Clinic, Yongin, Republic of Korea; 3Department of Korean Internal Medicine, College of Korean Medicine, Wonkwang University, Iksan, Republic of Korea; 4Department of Meridian & Acupoint, College of Korean Medicine, Wonkwang University, Iksan, Republic of Korea; 5College of Korean Medicine, Sangji University, Wonju, Republic of Korea; 6Clinic Department, Daemyeong Korean Medicine Clinic, Seoul, Republic of Korea&ast;These authors contributed equally to this workCorrespondence: Myungseok Ryu, Clinic Department of Daemyung Korean Medicine Clinic, Wonwoo b/d 3rd fl, Yangpyeong-ro, Yeongdeungpo-gu, Seoul, 07208, Republic of Korea, Tel +82-2-2671-7191, Fax +82-2-2676-1297, Email yeonbu16@gmail.comObjective: Shoulder pain is a common complaint in outpatient clinics and can result in an inability to work or perform household activities, leading to significant socioeconomic burden. Acupotomy, as one kind acupuncture that has flat knife-shaped tip, has been widely used for treating shoulder pain. However, despite the widespread use of acupotomy in primary medical institutions, large sample size clinical trials have not sufficiently been performed. In this respect, this multi-center retrospective study aimed to investigate the effectiveness and safety of acupotomy in reducing shoulder pain and disability using data from multi-center primary care clinics.Methods: This study was conducted in 25 Korean medicine clinics affiliated with the Korean Medical Society of Acupotomology, Republic of Korea, from August 2021 to December 2021. The medical records of patients who visited the clinics complaining of shoulder pain were gathered, and among them were those of patients who underwent acupotomy treatment and those who received acupuncture combined therapy. The Numeric Rating Scale (NRS), SPADI (Shoulder Pain and Disability Index), Range of Motion (ROM) and adverse event were evaluated at each visit. A linear mixed-effects models and paired t-test were used to identify the effectiveness of the treatment.Results: Overall analysis showed that the NRS score of patients decreased from 4.95 ± 1.97 before treatment to 3.78 ± 2.03 after treatment (n = 332, difference in NRS score, 1.17; 95% CI: 0.96– 1.38, t = 10.89 p < 0.001). SPADI score decreased from 19.05 ± 20.44 at baseline before treatment to 12.12 ± 17.26 after the last visit, which was statistically significant (n = 332, mean difference in SPADI score, 6.93; 95% CI: 4.71– 9.15, t = 6.150, p < 0.001). No serious adverse event was reported in both groups.Conclusion: This study showed the effectiveness of acupotomy therapy for shoulder pain, and as the treatment sessions increased, the effect of pain reduction and shoulder function improvement were also increased.Keywords: acupotomy, shoulder pain, retrospective study, multicenter study

Optically variable devices (OVDs) are in tremendous demand as optical indicators against the increasing threat of counterfeiting. Conventional OVDs are exposed to the danger of fraudulent replication with advances in printing technology and widespread copying methods of security features. Metasurfaces, two-dimensional arrays of subwavelength structures known as meta-atoms, have been nominated as a candidate for a new generation of OVDs as they exhibit exceptional behaviors that can provide a more robust solution for optical anti-counterfeiting. Unlike conventional OVDs, metasurface-driven OVDs (mOVDs) can contain multiple optical responses in a single device, making them difficult to reverse engineered. Well-known examples of mOVDs include ultrahigh-resolution structural color printing, various types of holography, and polarization encoding. In this review, we discuss the new generation of mOVDs. The fundamentals of plasmonic and dielectric metasurfaces are presented to explain how the optical responses of metasurfaces can be manipulated. Then, examples of monofunctional, tunable, and multifunctional mOVDs are discussed. We follow up with a discussion of the fabrication methods needed to realize these mOVDs, classified into prototyping and manufacturing techniques. Finally, we provide an outlook and classification of mOVDs with respect to their capacity and security level. We believe this newly proposed concept of OVDs may bring about a new era of optical anticounterfeit technology leveraging the novel concepts of nano-optics and nanotechnology.

Humidity-responsive structural coloration is actively investigated to realize real-time humidity sensors for applications in smart farming, food storage, and healthcare management. Here, humidity-tunable nano pixels are investigated with a 700 nm resolution that demonstrates full standard RGB (sRGB) gamut coverage with a millisecond-response time. The color pixels are designed as Fabry-Pérot (F-P) etalons which consist of an aluminum mirror substrate, humidity-responsive polyvinyl alcohol (PVA) spacer, and a top layer of disordered silver nanoparticles (NPs). The measured volume change of the PVA reaches up to 62.5% when the relative humidity (RH) is manipulated from 20 to 90%. The disordered silver NP layer permits the penetration of water molecules into the PVA layer, enhancing the speed of absorption and swelling down to the millisecond level. Based on the real-time response of the hydrogel-based F-P etalons with a high-throughput 3D nanoimprint technique, a high-resolution multicolored color print that can have potential applications in display technologies and optical encryption, is demonstrated.

A new SRAM-based pixel circuit is presented for use in a high-voltage digitally-driven pixel array in a micro-display panel. The pixel circuit is based on the standard 6T SRAM structure, but uses two more transistors of which gate dc-bias is controlled to adjust the pull-up strength of the inverters in the SRAM. This allows the pixel circuit to be operated with low-voltage row- and column-line signals while holding the stored logic in a high-voltage level. As a result, power and area of the pixel driving circuits are greatly reduced. The added two transistors do not necessitate area overhead if the pixels are to be individually separated with rectangular shape, which is true in many cases. To verify proper operation and power reduction efficacy of the proposed SRAM pixel circuit, a simple $100\times 200$ digital pixel array, together with row- and column-line drivers, is implemented using a 0.13-$\mu \text{m}$ CMOS technology and 1.5-V/3.3-V supplies. The measurement results show that, with the optimum bias for the two added transistors, total power dissipation including pixel array and driver power can be reduced by about as much as 78 %, which is very close to the theoretical limit of 79 % (= (1.5/3.3) 2 ).

Effects of Co interlayer and 200 °C post-annealing treatment on interfacial adhesion energy of SiNx/Cu structure were systematically investigated. Initial interfacial adhesion energy of SiNx/Cu structure measured by double cantilever beam test was 0.92 J/m2. The interfacial adhesion energy increased to 2.94 J/m2 with Co interlayer between SiNx and Cu films. After post-annealing treatment at 200 °C for 500 h, the interfacial adhesion energy of SiNx/Co/Cu structure decreased to 0.95 J/m2. X-ray photoelectron spectroscopy analysis revealed that the interfacial adhesion energy increased for SiNx/Co/Cu thin films due to CoSi2 reaction layer at SiNx/Co interface, but sharply decreased during post-annealing treatment by SiO2 formation at SiNx/Co interface.

In this study, an estimation of the future probable rainfall in Seoul, Korea, was performed, using non-stationary frequency analysis according to climate change and it was compared with the current probable rainfall. Hourly rainfall data provided by the Korea Meteorological Administration with durations of 1, 2, 3, 6, 12, 24, and 48-h were used as input. For the future projection of precipitation, the RCP 8.5 scenario was selected with the same durations. Moreover, the future hourly rainfall was extracted from using the daily precipitation from 29 Global Climate Models (GCMs), based on the statistical temporal down-scaling method and their corresponding bias corrections. Subsequently, the annual maximum precipitation was extracted for each year. In this study, both stationary and non-stationary frequency analysis was applied based on the observed and predicted time series data sets. In particular, for the non-stationary frequency analysis, the Differential Evolution Markov Chain technique, which combines the Bayesian-based Differential Evolution and Markov chain Monte Carlo methods, was adopted. Finally, the current and future intensity-duration-frequency curves were derived from the optimal probability distribution, and each probable rainfall was estimated. The results of the 29-scenario are presented with quantile estimations. The non-stationary frequency analysis results for Seoul revealed rainfalls of 94.4 mm/h for 30 y, 101.7 mm/h for 50 y, and 111.5 mm/h for 100 y return periods. The average value of the 29-GCM model ensemble was estimated to be approximately 5 mm/h higher than that obtained from the stationary frequency analysis. Considering the changes in hydrological characteristics due to climate change in Seoul, the results of this study could be utilized to pro-actively respond to natural disasters due to such phenomena.

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology for WLAN CMOS PAs is proposed to obtain broadband performances with a compact area using the wafer-level package technology. To achieve a highly linear output power with high efficiency across a 1-GHz bandwidth in a 5G-band PA, a reconfigurable interstage matching network and a broadband compact output transformer are proposed. For applications requiring a high linear transmission power, an integrated CMOS PA in a full transmitter chain must support the operation with external HBT-based PAs. A structure involving a main internal PA with an external PA driver is proposed to support the external PA mode with low-current consumption. The proposed structure does not require additional components or an output port and does not have the performance degradation of the main internal PA. The implemented 2.4G-band/5G-band CMOS PA using 40-nm CMOS technology has an average output power in the ranges of 19.1–19.2/18.6–18.8 dBm in the respective ranges of 2.4–2.5/4.9–5.9 GHz and concurrently complies with the −32-dB error vector magnitude (EVM) requirement. The power-added efficiencies (PAEs) for the 2.4G-band/5G-band CMOS PA with a −32-dB EVM is 12.9%/12.2% at 2.45/5.5 GHz. To the best of the authors’ knowledge, the presented PA exhibits the state-of-the-art minimum variation with high PAE and an output power in the range of 4.9–5.9 GHz compared to the fully integrated WiFi CMOS PAs reported thus far.

Low-dimensional light-emitting materials have been actively investigated due to their unprecedented optical and optoelectronic properties that are not observed in their bulk forms. However, the emission from low-dimensional light-emitting materials is generally weak and difficult to use in nanophotonic devices without being amplified and engineered by optical cavities. Along with studies on various planar optical cavities over the last decade, the physics of cavity-emitter interactions as well as various integration methods are investigated deeply. These integrations not only enhance the light-matter interaction of the emitters, but also provide opportunities for realizing nanophotonic devices based on the new physics allowed by low-dimensional emitters. In this review, the fundamentals, strengths and weaknesses of various planar optical resonators are first provided. Then, commonly used low-dimensional light-emitting materials such as 0D emitters (quantum dots and upconversion nanoparticles) and 2D emitters (transition-metal dichalcogenide and hexagonal boron nitride) are discussed. The integration of these emitters and cavities and the expect interplay between them are explained in the following chapters. Finally, a comprehensive discussion and outlook of nanoscale cavity-emitter integrated systems is provided.

Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

This paper proposes a fully integrated linear wireless LAN (WLAN) CMOS power amplifier (PA) with parallel-combined transistors and selective adaptive biasing. An adaptive bias circuit is applied to one of the parallel-combined transistors to take advantage of both the parallel-combined transistor method and adaptive biasing at the target output power region. By using the proposed biasing, the linear output power can be maximized, resulting in a higher power added efficiency (PAE). The experimental results show that the fully integrated CMOS PA has a saturated output power of 26.9 dBm at 2.48 GHz with a PAE of 40.3% at a 3.3-V supply voltage. The PA is also tested with the modulation and coding scheme 7 (MCS7) 802.11n signal (64-QAM 65Mbps with 20MHz). It satisfies a −28 dB error vector magnitude (EVM) and spectrum mask requirements at an output power of 19.8 dBm with a PAE of 18.8% without applying pre-distortion. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1374–1377, 2016

This letter presents a fully integrated dual-mode power amplifier (PA) with an autotransformer-based parallel combining transformer (ABPCT), fabricated with a standard 40-nm CMOS process. In comparison with a parallel combining transformer, the proposed ABPCT can offer high-efficiency performance in both high-power (HP) and low-power (LP) modes, and does so with a compact die area. With an 802.11g signal (64-QAM 54 Mbps) of 20-MHz channel bandwidth, the fully integrated dual-mode PA achieves 19.7 and 15.7 dBm average output powers with PAEs of 17.1% and 13%, in HP and LP modes, respectively, while satisfying a −25 dB error vector magnitude and spectral mask requirements. Operating the PA in the LP mode can save more than 40% of the current consumption at a 10-dBm average output power when compared with that in the HP mode.

A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves ?28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.

Effects of wet chemical treatment and thermal cycle conditions on the quantitative interfacial adhesion energy of Cu/SiNx thin film interfaces were evaluated by 4-point bending test method. The test samples were cleaned by chemical treatment after Cu chemical-mechanical polishing (CMP). The thermal cycle test between Cu and SiNx capping layer was experimented at the temperature, -45 to 175 o C for 250 cycles. The measured interfacial adhesion energy increased from 10.57 to 14.87 J/m 2 after surface chemical treatment. After 250 thermal cycles, the interfacial adhesion energy decreased to 5.64 J/m 2 and 7.34 J/m 2 for without chemical treatment and with chemical treatment, respectively. The delaminated interfaces were confirmed as Cu/SiNx interface by using the scanning electron microscope and energy dispersive spectroscopy. From X-ray photoelectron spectroscopy analysis results, the relative Cu oxide amounts between SiNx and Cu decreased by chemical treatment and increased after thermal cycle. The thermal stress due to the mismatch of thermal expansion coefficient during thermal cycle seemed to weaken the Cu/SiNx interface adhesion, which led to increased CuO amounts at Cu film surface.

The 65nm CMOS wireless connectivity SoC which support 802.11 a/b/g/n, BT and NFC is implemented. The SoC cover 13.6MHz band for NFC, 2.4GHz and 5GHz band for BT and 802. 11a/b/g/n. The SoC includes RF Transceiver, Baseband modem for 802.11 a/b/g/n, BT and NFC and ARM9 core with various peripherals. The Soc is fabricated using 65nm CMOS process with 5.5 × 5.5 mm2 die area. The power consumption of 802.11n is about 160mW and 180mW for 2.4GHz receiver mode and transceiver mode except PA respectively and 170mW and 190mW for 5GHz case. The 802.11n maximum throughput is measured to 150Mbps. The 802.11 a/b/g/n receiver noise figure is about 4∼5dB at 2.4∼2.5GHz band and 4.8∼5.7GHz band. The sensitivity is about −88.7dBm at MCS0 mode. The sensitivity of BT is about −94dBm. NFC operation range is up to 3.5cm.

For a few years, new mobile broadcasting services were launched in Korea, Japan, Europe and China. The mobile broadcasting markets are maturing rapidly for applications such as mobile cellular phones, car navigation, PMP and so on. The market drives low-cost, low-power and small size significantly for mobile applications and drives multiple functionality and multiple bands [1]. To meet the market requirements, more integration of system blocks and functionality is needed. To achieve this goal, the 65nm CMOS and multistandard and multiband receiver SoC may be suitable solution.

This paper provides a complex band-pass filter (BPF) for low-IF conversion digital audio broadcasting (DAB) and terrestrial-digital multimedia broadcasting (T-DMB) tuner with I/Q gain and phase mismatch calibration. This calibration can be implemented in the first stage of complex BPF using feed-through resistor calibration scheme. The automatic tuning circuit with programmable clock is also presented. The measurement results show 1.536 MHz bandwidth with 2.048 MHz IF center frequency and 50 dB stop band attenuation at 0.7 MHz frequency offset. The in-band and out-band 3rd order intermodulation distortion (IMD3) are 55 and 60 dBc, respectively. After I/Q mismatch calibrating, 20 dB image rejection ratio (IRR) improvement is obtained from 38 dB to 58 dB in this work. The automatic tuning circuit guarantees less than +/- 4 % cut-off frequency variation covering the several clock requirements from demodulator ICs. The complex BPF is fabricated in 0.13 mum RF CMOS technology and consumes 9 mA with 1.2 V power supply.

A UHF mobile single chip RFID reader is implemented in 0.18 mum CMOS process. Developed IC achieves DA output power of 3 dBm, OIP3 of 14.8 dBm, phase noise of -100 dBc/Hz at 100 kHz offset, noise figure of 35.5 dB for talk mode, 6.2 dB for listen before talk (LBT) mode, and current consumption of 108 mA from a 1.8 V supply. With an external PA, Tx output generates output power of 27 dBm with OIP3 of 42.5 dBm. A leakage signal cancellation scheme is employed to suppress inevitable Tx leakage into Rx input. At a distance of 90 cm between antenna and tag the average recognition ratio is increased from 0% to 42.8% by the leakage canceller.

A low power high linear transmitter for mobile WiBro and WiMAX is developed. The transmitter is fabricated in a 0.18 mum 1P6M CMOS process for low power characteristics and SoC compatibility. To achieve high linearity performance with low power consumption, the transmitter employs new linearization methods. Linear transconductor is used for the transmitter mixer. The transconductor utilizes a negative feedback amplifier and a current mirror amplifier (CMA). In addition, a multiple-gated transistor (MGTR) with two auxiliary transistors and resistive source degeneration are used for the driver amplifier. With the proposed linearization techniques, a high linearity of 30.5 dBm OIP3 is achieved with 97.2 mW power consumption from a 1.8 V supply.

A CMOS driver amplifier employs two design techniques to improve its linearity in wide output power level. First, multiple-gated transistor (MGTR) technique with two auxiliary transistors extends the linear region further compared with MGTR with single auxiliary transistor. Second, resistive source degeneration significantly suppresses the unwanted 2nd-harmonic feedback effect caused by an inductive source degeneration. A 2.4-GHz differential driver amplifier has been implemented in 0.18 mum CMOS for Mobile WiMAX and Korean WiBro applications. It shows that the linear region with OIP3 of >+20dBm is extended up to an output power of -5 dBm, while achieving a maximum OIP3 of +28 dBm, OPldB of +7.8 dBm, and a power gain of 9.2 dB with dc power consumption of 1.8V and 18.7 mA.

A 0.18mum CMOS dual-band low-IF mobile-TV tuner IC for T-DMB/DAB that supports Band-III and L-band is presented. By modifying a few metals and via masks, the IC can support VHF and UHF bands for ISDB-T partial reception. The chip meets all the specifications of both applications with a sensitivity of

The image rejection mixer for digital audio broadcasting and digital multimedia broadcasting (DAB/DMB) is described. The mixer is implemented in a 0.18mum six-layer metal CMOS process and occupies a 2.25mm2. To obtain the ultimate level of image rejection without additional tuning, the double quadrature architecture is used and to linearize the RF buffer, differential transconductance linearization technique is used (Tae wook Kim, et al., 2005). The fabricated mixer exhibits 65 dB image rejection ratio, 41dB adjacent channel rejection ratio, 100 kHz ~ 1.65MHz image rejection bandwidth, 16dB gain, 35dBmV input-referred third order intercept point (IIP3), and 15mA current consumption from 1.8V supply

A direct-conversion satellite tuner-demodulator IC is realized using 0.18/spl mu/m CMOS technology. The IC down-converts a 950-2150MHz satellite broadcasting signal to base band and demodulates the signal to an MPEG data stream. The IC conforms to both DVB-S and DSS standards. Experimental results show a 9dBm IIP3 while consuming 230mA from 1.8V supply.