Search

High-tech firms face constant innovation and challenges due to a rapidly changing tech environment. Open innovation strategies are an important solution for fostering rapid and efficient innovation by leveraging external capabilities. This study explores the critical factors that influence open innovation strategies in high-tech companies, assessing their importance and providing key insights for promoting these strategies. Through a comprehensive literature review and expert interviews, 16 key factors impacting open innovation were identified. A hierarchical research model was developed using the ser-M (subject, environment, resource, mechanism) framework, focusing on subject, environment, resource, and mechanism for a corporate strategy analysis. A survey and an AHP analysis were conducted with 30 participants, comprising engineers and open innovation experts, all with over a decade of experience in the field within Korean high-tech companies. The analysis focused on four critical elements: subject, environment, resource, and mechanism; subject emerged as the most critical factor for successfully implementing open innovation strategies. Specifically, the will of chief executives, the direction of decision-making, and technological environment changes were found to be significant contributors. The consensus between engineers and experts confirms that while environmental and resource factors are vital, strong leadership and effective decision-making are paramount for successful open innovation in high-tech companies.

Cache side-channel attacks have been serious security threats to server computer systems, thus researchers have proposed software-based defense approaches that can detect the security attacks. Profiling-based detectors are lightweight detection solutions that rely on hardware performance counters to identify unique cache performance behaviors by cache side-channel attacks. The detectors typically need to set appropriate criteria to differentiate between attack processes and normal applications. In this paper, we explore the limitations of profiling-based detectors that rely on hardware performance counters. We present an attack scenario, called Vizard, that can bypass the existing profiling-based detectors by manipulating cache performance behaviors of an attack process. Our analysis discloses that cache side-channel attacks include idle periods that can be exploited as attack windows for creating cache events. Vizard generates counterbalancing cache events within the attack windows to hide particular cache performance behaviors of cache side-channel attacks. Our evaluation exhibits that Vizard can effectively bypass profiling-based detectors while maintaining high attack success rates. Our research work represents that attackers can bypass the existing detection approaches by manipulating performance counters.

This article presents a high-performance, low-power analog convolutional neural network (CNN) circuit integrated into a CMOS image sensor (CIS) for face detection applications. The main block of the proposed in-column analog CNN circuits is an analog multiplication-and-accumulation (MAC) circuit consisting of an operational transconductance amplifier-based switched capacitor circuit enabling the programmable weight function. With the proposed MAC, a 3-layer analog CNN processor is implemented into the column-parallel readout circuit in conventional CIS. Furthermore, for low-power CNN operations, we use a low-resolution analog-to-digital converter with the proposed nonlinear quantization method resulting in an increase in the accuracy of face detection from 92.8% to 98.75% at 120 frame rates with 2.8 V/1.5 V supply voltage. A prototype sensor with $160\times120$ effective image resolution was fabricated using a 110 nm CMOS image sensor process. The measurement results showed that the maximum power consumption was 0.57 mW and 4.02 mW at 1 and 120 frame rates, respectively.

This paper presents a CMOS image sensor (CIS) with built-in lane detection computing circuits for automotive applications. We propose on-CIS processing with an edge detection mask used in the readout circuit of the conventional CIS structure for high-speed lane detection. Furthermore, the edge detection mask can detect the edges of slanting lanes to improve accuracy. A prototype of the proposed CIS was fabricated using a 110 nm CIS process. It has an image resolution of 160 (H) × 120 (V) and a frame rate of 113, and it occupies an area of 5900 μm × 5240 μm. A comparison of its lane detection accuracy with that of existing edge detection algorithms shows that it achieves an acceptable accuracy. Moreover, the total power consumption of the proposed CIS is 9.7 mW at pixel, analog, and digital supply voltages of 3.3, 3.3, and 1.5 V, respectively.

In this paper, we propose a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) that has built-in mask circuits to selectively capture either edge-detection images or normal 8-bit images for low-power computer vision applications. To detect the edges of images in the CIS, neighboring column data are compared in in-column memories after column-parallel analog-to-digital conversion with the proposed mask. The proposed built-in mask circuits are implemented in the CIS without a complex image signal processer to obtain edge images with high speed and low power consumption. According to the measurement results, edge images were successfully obtained with a maximum frame rate of 60 fps. A prototype sensor with 1920 × 1440 resolution was fabricated with a 90-nm 1-poly 5-metal CIS process. The area of the 4-shared 4T-active pixel sensor was 1.4 × 1.4 µm2, and the chip size was 5.15 × 5.15 mm2. The total power consumption was 9.4 mW at 60 fps with supply voltages of 3.3 V (analog), 2.8 V (pixel), and 1.2 V (digital).

In order to increase the operating speed of a CMOS image sensor (CIS), a new technique of digital correlated double sampling (CDS) is described. In general, the fixed pattern noise (FPN) of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC) has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA) that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.

In this paper, a 120 frames per second (fps) low noise CMOS Image Sensor (CIS) based on a Two-Step Single Slope ADC (TS SS ADC) and column self-calibration technique is proposed. The TS SS ADC is suitable for high speed video systems because its conversion speed is much faster (by more than 10 times) than that of the Single Slope ADC (SS ADC). However, there exist some mismatching errors between the coarse block and the fine block due to the 2-step operation of the TS SS ADC. In general, this makes it difficult to implement the TS SS ADC beyond a 10-bit resolution. In order to improve such errors, a new 4-input comparator is discussed and a high resolution TS SS ADC is proposed. Further, a feedback circuit that enables column self-calibration to reduce the Fixed Pattern Noise (FPN) is also described. The proposed chip has been fabricated with 0.13 μm Samsung CIS technology and the chip satisfies the VGA resolution. The pixel is based on the 4-TR Active Pixel Sensor (APS). The high frame rate of 120 fps is achieved at the VGA resolution. The measured FPN is 0.38 LSB, and measured dynamic range is about 64.6 dB.

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm2 with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency.

In this paper, we present a multi-resolution mode CMOS image sensor (CIS) for intelligent surveillance system (ISS) applications. A low column fixed-pattern noise (CFPN) comparator is proposed in 8-bit two-step single-slope analog-to-digital converter (TSSS ADC) for the CIS that supports normal, 1/2, 1/4, 1/8, 1/16, 1/32, and 1/64 mode of pixel resolution. We show that the scaled-resolution images enable CIS to reduce total power consumption while images hold steady without events. A prototype sensor of 176 × 144 pixels has been fabricated with a 0.18 μm 1-poly 4-metal CMOS process. The area of 4-shared 4T-active pixel sensor (APS) is 4.4 μm × 4.4 μm and the total chip size is 2.35 mm × 2.35 mm. The maximum power consumption is 10 mW (with full resolution) with supply voltages of 3.3 V (analog) and 1.8 V (digital) and 14 frame/s of frame rates.