Search

This study presents, experimentally, similarity and Froude number similitude (FNS) in the dimensionless features of two solitary waves propagating over a horizontal bed, using two wave gauges and a high-speed particle image velocimetry (HSPIV). The two waves have distinct wave heights H0 (2.9 and 5.8 cm) and still water depths h0 (8.0 and 16.0 cm) but identical H0/h0 (0.363). Together with the geometric features of free surface elevation and wavelength, the kinematic characteristics of horizontal and vertical velocities, as well as wave celerity, are elucidated. Illustration of the hydrodynamic features of local and convective accelerations are also made in this study. Both similarity and FNS hold true for the dimensionless free surface elevation (FSE), wavelength and celerity, horizontal and vertical velocities, and local and convective accelerations in the horizontal and vertical directions. The similarities and FNSs indicate that gravity dominates and governs the wave kinematics and hydrodynamics.

For providing new insights into the effect of the leading waves on the velocity distribution of the generated bore, a case study of the undular bore (or weak bore) with the water depth ratio 1.70 is tested in a flume, using flow visualization technique (FVT) and high-speed particle image velocimetry (HSPIV). The undular bore, generated right downstream of a suddenly lifted gate, propagates first over a horizontal bottom and then travels over a 1:20 sloping bottom. The wave gauges were used to measure the free surface elevations of the generated bore at different positions. A complete evolution of the free surface elevations of the generated bore accompanied by the dispersive leading waves, measured at different shoreward positions, is elucidated first. Illustrations of variations in wave period and height of each leading wave in the onshore direction are also made. Based on visualized images and velocity fields measured, the following flow features at different stages of the generated bores are explored: (1) The temporal and spatial variations in the flow field of the generated bore with respect to passing of the leading waves; (2) The influence of the leading waves on shifting of the velocity distribution of the generated bore, along with illustrations of flow acceleration or deceleration in the onshore direction; (3) Flow reversal zone and shear layer formation near the sloping bottom; (4) Development of a vortex train (or street) in the shear layer between two opposite currents consisting of the onshore run-up flow and the offshore flow reversal right over the sloping bottom.

This paper describes a four-layer-stacked chip with 45-nm dynamic random access memory (DRAM) dice and 65-nm logic controller, which are interconnected by backside-via-last through-silicon via (TSV) processes. Fabrication of backside-via-last process and multiple die stacking using chip-to-chip bonding are presented with electrical connection between TSV (5- $\mu \text{m}$ -diameter/50- $\mu \text{m}$ -length) and Cu interconnects. Excellent fabrication of stacked dice verified that the micro bumps with 12- $\mu \text{m}$ diameter are bonded using three step temperature bonding profile. Further stacked DRAM/Logic performance and system verifications are demonstrated successfully using 3-D heterogeneous integration.

The hydrodynamic characteristics, including local and convective accelerations as well as pressure gradient in the horizontal direction, of the external stream of an undular bore propagating on a 1:20 sloping beach are experimentally studied. A bore with the water depth ratio of 1.70 was generated downstream of a suddenly lifted gate. A high-speed particle image velocimetry was employed to measure the velocity fields during the run-up and run-down motions. The time series of free surface elevation and velocity field/profile of the generated bore, comprising a pure bore accompanied by a series of dispersive leading waves, are first demonstrated. Based on the fast Fourier transform (FFT) and inverse FFT (IFFT) techniques, the free surface elevation of leading waves and the counterpart of pure bore are acquired separately at a specified measuring section (SMS), together with the uniform horizontal velocity of the pure bore. The effect of leading-wave-induced velocity shift on the velocity profiles of the generated bore are then evaluated at the SMS. To understand the calculation procedure of accelerations and pressure gradient, three tabulated forms are provided as illustrative examples. Accordingly, the relationships among the partially depth-averaged values of the non-dimensional local acceleration, convective acceleration, total acceleration and pressure gradient of the generated/pure bore acquired at the SMS versus the non-dimensional time are elucidated. The trends in the non-dimensional accelerations and pressure gradient of the external stream of generated bore are compared with those of the pure bore. During the run-up motion from the instant of arrival of the bore front to the moment of the peak level at the SMS, continuous decrease in the onshore uniform horizontal velocity, and successive deceleration of the pure bore in the onshore direction are evidenced, exhibiting the pure bore under the adverse pressure gradient with decreasing magnitude. However, the pure bore once ridden by the leading waves is decelerated/accelerated spatially and accelerated/decelerated temporally in the onshore direction during the rising/descending free surface of each leading wave. This fact highlights the effect of pre-passing/post-passing of the leading wave crest on the velocity distribution of generated bore. It is also found that, although the leading waves have minor contribution on the power spectrum of the free surface elevation as compared with that of the pure bore, the leading waves do play an important role on the magnitudes of both accelerations and pressure gradient. The largest magnitude of the acceleration contributed by the leading waves is around 26 times the counterpart contributed by the pure bore. Further, during the run-down motion right after the moment for the peak level of the bore, a linear increase in the magnitude of the offshore uniform horizontal velocity and a constant local acceleration with increasing time are both identified. The partially depth-averaged value of the non-dimensional pressure gradient is equal to a small negative constant (&minus, 0.0115) in the offshore direction, indicating that the bore is subject to a constant favorable pressure gradient.

An experimental results on the spatio-temporal variation of velocity field and vortex structure, generated from the separated boundary layers on the offshore side of the still-water shoreline, during the run-down process of non-breaking solitary waves over a 1:3 sloping beach are presented. Three waves having the incident wave-height to water-depth ratios (H0/h0) of 0.363, 0.263, and 0.171 were generated in a wave flume. Two flow visualization techniques and high-speed particle image velocimetry were employed. The primary topics and new findings are: (1) Mechanism of the incipient flow separation, accompanied by formation of the separated shear layer from the beach surface, is elucidated under the adverse pressure gradient, using the fine data of velocity measurements very close to the sloping boundary. (2) Occurrence of hydraulic jump subsequently followed by development of the tongue-shaped free surface and projecting jet is demonstrated through spatio-temporal variation in the Froude number. It is confirmed by a change in the Froude number from supercritical to subcritical range as the free surface rapidly rises from the onshore to offshore side. (3) A complete evolution of the primary vortex structure (including the core position, vortex size, and velocity distribution passing through the vortex core) is first introduced systematically, together with the illustration of temporal variation in the topological structure. The non-dimensional shoreward distance of the vortex core section decreases with the increase in the non-dimensional time. However, the non-dimensional size height of the primary vortex increases with increasing non-dimensional time. (4) Two universal similarity profiles for both the wall jet flow and the shear layer flow demonstrate independency of the two similarity profiles of the wave-height to water-depth ratio and the beach slope. The similarity profiles indicate the promising collapse of the data from three previous studies for 1:20, 1:10, and 1:5 sloping beaches.

The characteristics of horizontal velocity in the bottom boundary-layer flow induced by a solitary wave propagating over a horizontal bottom are presented experimentally, using high-speed particle image velocimetry (HSPIV). The ratio of wave height to water depth varies from 0.096 to 0.386 and the flow inside the boundary layer is laminar. The results show that the horizontal velocity profiles can be mainly classified into two categories with respect to the passing of the solitary wave-crest at the measuring section: the pre-passing (or acceleration) phases under favorable pressure gradient and post-passing (or deceleration) phases under adverse pressure gradient. For the velocity distributions obtained during the pre-passing phases, a nonlinear regression analysis was used to precisely determine the time-dependent characteristic length and velocity scales underlying these profiles. A similarity profile of the horizontal velocity is established first using the time-dependent free-stream velocity and boundary layer thickness as the characteristic velocity and length scales, respectively. In addition, the displacement thickness, the momentum thickness, and the energy thickness are also considered as alternative length scales. All these four representative thicknesses are closely related to each other, demonstrating that any one amongst them can be regarded as the characteristic length scale. The forms of similarity profiles for the non-dimensional velocity distributions are somewhat analogous to the results of steady boundary layer flow over a thin plate under with pressure gradient, but with different coefficients or powers. While during the post-passing phases, flow reversal which acts like an unsteady wall jet and moves in the opposite direction against the wave propagation occurs after the passage of solitary wave-crest. The thickness of flow reversal layer increases with time. A similarity profile is proposed for the velocity distributions corresponding to occurrence of the extreme value in the maximum negative velocity of flow reversal. Variations of the maximum negative velocity and the thickness of flow reversal with the time right after the start of flow reversal are also discussed in detail. Moreover, the non-dimensional time leads of the horizontal velocities at different heights in the boundary layer over the free-stream velocity are evidenced to be more noticeable toward the bottom, and also in lower ratio of wave height to water depth. A similarity profile for the non-dimensional time lead versus the non-dimensional height above the bottom surface is also presented.

This study investigates experimentally similarity and Froude number similitude (FNS) in the dimensionless flow features of three solitary waves traveling on a 1:3 sloping beach. These three waves, designated as cases A, B, and C, respectively, have different heights H0 (=5.8 cm, 2.9 cm, and 1.815 cm) and still water depths h0 (=16.0 cm, 8.0 cm, and 5.0 cm), but identical ratios H0/h0 (=0.363). A high-speed particle image velocimetry system is employed to obtain the free surface profiles (FSPs) and velocity fields/profiles. These features include the free surface elevation (FSE)/FSP time series; velocity fields and profiles, positions, and propagation speeds of flow demarcation curves; times and maximum onshore distances of the maximum run-up heights (MRHs); and times and onshore distances of hydraulic jumps for cases A and B. When the swash tip of a solitary wave reaches the MRH, the contact point becomes almost immobile for a short time interval, with the contact angle changing from obtuse, via right, to acute angle. For cases A and B, the similarities in the dimensionless MRHs and times, at which the run-down motions of the wave tips start, are affirmed. These facts highlight that the swash tips and contact points are subject to complex interactions among gravity force, viscous friction, and surface tension of fluid. Case C, having the smallest length scale, is only focused on the arrival or starting time of the MRH or run-down motion and the MRH and used as a counterexample to demonstrate the absence of similarity or FNS due to the relatively prominent effects of viscous friction and surface tension.

Experimental results are presented regarding the free-surface elevations, velocity fields, and horizontal pressure gradients of dambreak-generated undular bores propagating over a horizontal bottom. Ultrasonic wave gauges, high-speed particle image velocimetry, and a flow visualization method are used to investigate the flow fields. Features of the full-depth velocity field and pressure gradient (equal to minus the sum of the local and convective accelerations) in the free stream over the boundary layer are elucidated with respect to the phase of the free-surface elevation and are categorized into four temporal stages. For stage I with rising free-surface elevations, a successive increase in the magnitude of the pressure gradient (with a negative value) corresponds to a favorable pressure gradient in the free stream. Around the zero-up/down-crossing phase of each leading wave evolving in stage II, the pressure gradient has a negative/positive maximum, revealing the maximum favorable/adverse pressure gradient in the free stream. However, the pressure gradient is zero at each crest or trough phase, showing an instantaneous zero pressure gradient. Within stage III characterized by a constant free-surface elevation, the pressure gradient is almost zero. In stage IV with descending free-surface elevations, the pressure gradient first increases from nearly zero to a positive maximum (representing the maximum adverse pressure gradient), then keeps this value for a period of time, and eventually decreases to zero. Subsequently, flow reversal with an increase in thickness over the bottom and free-stream velocity equal to zero takes place.

Memristor devices are promising as high-density computing logic for non-high-speed normally off applications using heterogeneous technologies. This brief proposes a set-triggered-parallel-reset memristor logic (STPR-ML)-based on back-end-of-line-based bipolar-type memristor devices to reduce the area overhead and increase compatibility with standard and nonstandard CMOS processes. The proposed STPR-ML has two subsets: with and without nonvolatile storage capability. Two types of physical structures are also proposed for STPR-ML: 2-D and 3-D. A test chip using 2-D $\hbox{HfO}_{x}$ memristor devices was fabricated using a CMOS process to confirm the functionality of the nand , nor , and xor gates used in STPR-ML. The proposed STPR-ML achieves a $2\sim 8\times$ reduction in area compared with CMOS logic gates with four or more inputs.

In this investigation, a system-in-package (SiP) that consists of a very low-cost interposer with through-silicon holes (TSHs) and with chips on its top and bottom sides (a real 3-D IC integration) is studied. Emphasis is placed on the fabrication of a test vehicle to demonstrate the feasibility of this SiP technology. The design, materials, and process of the top chip, bottom chip, TSH interposer, and final assembly will be presented. Shock and thermal cycling tests will be performed to demonstrate the integrity of the SiP structure.

Numerous laboratory-scale physical experiments and numerical simulations have been carried out to explore the shoaling dynamics of internal solitary waves (ISWs) on slope topographies. Detailed features during wave breaking have been investigated under relatively low Reynolds numbers, but for real ocean-scale or lake-scale scenarios with a much higher Reynolds number, laboratory-scale modeling is inadequate to capture the three-dimensional turbulent characteristics in the wave shoaling process. As a result, a three-dimensional large-eddy simulation (LES) is performed in the present study to investigate the shoaling process of the elevation-typed ISWs traveling on uniform slopes in a two-layer fluid system. Scale effects due to the Reynolds numbers (varied from 103 to 105) and three-dimensional characteristics during wave shoaling are also explored and discussed. Detailed ISW-slope interaction dynamics, including the typical shoaling features, the characteristics of internal boluses, and both the velocity field and the energy transformation, are systematically obtained and analyzed. It is found that, while reaching the maximum vertical displacement (i.e., maximum run-up height), the frontal part of the heavier lower-layer fluid can evolve into the internal bolus if the internal Iribarren number, Ir, defined as the ratio of the topographic slope and the square root of the incident wave steepness, is less than 0.65. The maximum wave-induced velocities and energy loss are also well related to Ir. Empirical regressed equations for seven important physical parameters during the shoaling process are also proposed. The extreme velocities, wave energy loss, and three-dimensionality of the flow field are all identified to be very sensitive to Reynolds numbers, indicating that traditional two-dimensional laboratory-scale modeling tools may be insufficient to accurately capture the shoaling mechanisms of the ISWs of elevation type.

ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bit line (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read disturbance into consideration. PSRC narrows the reference current distribution to achieve high read yield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) read-write random access time among megabit scaled embedded NVM macros has been demonstrated.

Thin-wafer handling is one of the key enabling technologies for 2.5D/3D IC integration. Usually, it temporary bonds the TSV (through-silicon via)/RDL (redistribution layer) wafer (e.g., passive and active interposers) to a supporting carrier wafer with an adhesive, backgrinds the TSV/RDL interposer wafer to very thin (≤100μm), goes through all the necessary processes, and then de-bonds the thin TSV/RDL interposer wafer from the carrier wafer. In this study, a different route will be taken which eliminates the temporary bonding and de-bonding processes. Emphasis is placed on using a heat-spreader wafer as a supporting carrier wafer during the manufacturing processes and after the assembly is completed (diced), the heat-spreader remains on the thin TSV/RDL interposer. This is a very simple and low-cost thin-wafer handling method for 2.5D/3D IC integration.

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored.

In this paper, the optimization of Cu chemical-mechanical polishing (CMP) performance (dishing) for the removal of thick Cu-plating overburden due to Cu plating for deep through silicon via (TSV) in a 300-mm wafer is investigated. Moreover, backside isolation oxide CMP for TSV Cu exposure is examined. To obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu-polishing process. First, a bulk of Cu is removed with the slurry of high Cu removal rate and second, the Cu surface is planarized with the slurry of high Cu passivation capability. The Cu dishing can be improved up to 97% for the 10-μm-diameter TSVs on a 300-mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly optimized Cu-plating overburden for TSVs and redistribution layers. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a larger TSV diameter still keep in a plateau-like shape after CMP.

In this work, we utilize a photo-chemical etching (PCE) method to form through-glass-via (TGV). The PCE is a low cost, damage-free and potentially large-area method for TGV formation. An ultra-violet (355 nm) pulse laser was used to illuminate the glass surface. The illuminated region will crystallize after thermal annealing in a furnace. The crystallized glass shows much faster etching rate than the amorphous region in HF solution. For a relatively thick (600 nm) glass, a via-hole with diameter of around 60 μm was demonstrated in laser energy of 11 J/cm2. No laser damages were observed. In comparison, at least 10 times higher energy was required to drill a glass directly. Micro-cracks were form around the glass-via. In addition, a 40 selectivity was achieved to the crystallized and amorphous region. This simple and useful method paves a straight road for 3-D integration.

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined.

In this study, the electrical performance of a general TSV structure for high-frequency 3D IC integration applications is investigated. Emphasis is placed on the proposal of an analytical model and the analytical equations of a TSV with all its key parameters. Also, the model and equations are verified, both in the frequency and time domains, by more detailed finite element analyses. Finally, a TSV electrical design guideline is proposed.

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieves the function of monitoring the SiO2 thickness completeness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.

This study investigates the resistance switching characteristics of Cr 2 O 3 -based resistance random access memory (RRAM) with Pt/Cr 2 O 3 /TiN and Pt/Cr 2 O 3 /Pt structures. Only devices with Pt/Cr 2 O 3 /TiN structure exhibit bipolar switching behavior after the forming process because TiN was able to work as an effective oxygen reservoir but Pt was not. Oxygen migration between Cr 2 O 3 and TiN was observed clearly before and after resistance switching from Auger electron spectroscopy (AES) analysis. Both low resistance state, ON state, and high resistance state, OFF state, of Pt/Cr 2 O 3 /TiN structures are stable and reproducible during a successive resistive switching. The resistance ratio of ON and OFF state is over 10 2 , on top of that, the retention properties of both states are very stable after 10 4 s with a voltage of −0.2 V.

In this study, thin wafer handling of 300mm wafer for 3D IC Integration is investigated. Emphasis is placed on the determination of the effect of a dicing tape on thin-wafer handling of wafers with Cu-Au pads, Cu-Ni-Au UBM, and TSV interposer with RDL. Also, thin-wafer handling critical issues such as the chip/interposer wafer, carrier wafer, temporary bonding, thinning, backside process, de-bonding, and assembly are presented and their potential solutions are discussed. Finally, state-of-the-art of materials and equipments for thin-wafer handling are examined.

The feasibility of a 3D IC integration SiP has been demonstrated in this investigation. The heart of this SiP is a TSV (through-silicon via) interposer with RDL (redistribution layer) on both sides, IPD (integrated passive devices) and SS (stress sensors). This interposer is used to support (with microbumps) a stack of four memory chips with TSVs, one thermal chip with heater and one mechanical chip with SS, and then overmolded on its top side for pick and place purposes. The interposer’s bottom-side is attached to an organic substrate (with ordinary lead-free solder bumps), which is lead-free solder-balled on a PCB (printed circuit board). Key enabling technologies such as TSV etching, chemical mechanical polishing (CMP), thin-wafer handling, thermal management, and microbumping, assembly and reliability are highlighted.

This paper proposes a 3D IC integration TSV testing apparatus, primarily using at least one set of TSV component testing devices with a specific design. Under complex technological conditions, such as varying depth-width ratios of TSVs and heterogeneous IC integration, as well as the principle of different coupling parasitic parameters between TSVs, the TSV coupling measuring device designed for specific purposes in coordination with a measuring method for high-frequency coupling TSV S-parameters, achieving the function of monitoring the SiO2 thickness of TSVs. This feasible approach further allows judgment of whether subsequent processes can continue, effectively reducing costs.

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

Thermal performance of 3D IC integration is investigated in this study. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, the thermal behavior of a TSV cell is examined. Furthermore, 3D heat transfer simulations are adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.

Especially for microcontroller and mobile applications, embedded nonvolatile memory is an important technology offering to reduce power and provide local persistent storage. This article describes a new resistive RAM device with fast write operation to improve the speed of embedded nonvolatile memories.

In this paper, we propose a new test method to detect write disturbance fault (WDF) for magnetic RAM (MRAM). Furthermore, an adaptive diagnosis algorithm (ADA) is also introduced to identify and diagnose the WDF for MRAM. The proposed test method can evaluate process stability and uniformity. We also develop a built-in self-test (BIST) circuit that supports the proposed WDF diagnosis test method. A 1-Mb toggle MRAM prototype chip with the proposed BIST circuit has been designed and fabricated using a special 0.15-μm CMOS technology. The BIST circuit overhead is only about 0.05% with respect to the 1-Mb MRAM. The test time is reduced by about 30% as compared with the test method without using the decision write mechanism. The chip measurement results show the efficiency of our proposed method.